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[WebAssembly] Add support for memcmp expansion (#148298)
Fixes #61400 Added test case in llvm/test/CodeGen/WebAssembly/memcmp-expand.ll
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‎llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

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@@ -46,6 +46,10 @@ WebAssemblyTargetLowering::WebAssemblyTargetLowering(
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: TargetLowering(TM), Subtarget(&STI) {
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auto MVTPtr = Subtarget->hasAddr64() ? MVT::i64 : MVT::i32;
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// Set the load count for memcmp expand optimization
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MaxLoadsPerMemcmp = 8;
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MaxLoadsPerMemcmpOptSize = 4;
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// Booleans always contain 0 or 1.
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setBooleanContents(ZeroOrOneBooleanContent);
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// Except in SIMD vectors

‎llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp

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@@ -141,6 +141,21 @@ InstructionCost WebAssemblyTTIImpl::getCastInstrCost(
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return BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I);
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}
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WebAssemblyTTIImpl::TTI::MemCmpExpansionOptions
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WebAssemblyTTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const {
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TTI::MemCmpExpansionOptions Options;
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Options.AllowOverlappingLoads = true;
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// TODO: Teach WebAssembly backend about load v128.
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Options.LoadSizes.append({8, 4, 2, 1});
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Options.MaxNumLoads = TLI->getMaxExpandSizeMemcmp(OptSize);
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Options.NumLoadsPerBlock = Options.MaxNumLoads;
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return Options;
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}
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InstructionCost WebAssemblyTTIImpl::getMemoryOpCost(
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unsigned Opcode, Type *Ty, Align Alignment, unsigned AddressSpace,
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TTI::TargetCostKind CostKind, TTI::OperandValueInfo OpInfo,

‎llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h

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@@ -73,6 +73,10 @@ class WebAssemblyTTIImpl final : public BasicTTIImplBase<WebAssemblyTTIImpl> {
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getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
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TTI::CastContextHint CCH, TTI::TargetCostKind CostKind,
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const Instruction *I = nullptr) const override;
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TTI::MemCmpExpansionOptions
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enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const override;
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InstructionCost getMemoryOpCost(
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unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace,
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TTI::TargetCostKind CostKind,

‎llvm/test/CodeGen/WebAssembly/memcmp-expand.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s
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target triple = "wasm32-unknown-unknown"
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declare i32 @memcmp(ptr, ptr, i32)
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define i1 @memcmp_expand_3(ptr %a, ptr %b) {
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; CHECK-LABEL: memcmp_expand_3:
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; CHECK: .functype memcmp_expand_3 (i32, i32) -> (i32)
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; CHECK-NEXT: # %bb.0:
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; CHECK-NEXT: i32.load16_u $push7=, 0($0):p2align=0
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; CHECK-NEXT: i32.load16_u $push6=, 0($1):p2align=0
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; CHECK-NEXT: i32.xor $push8=, $pop7, $pop6
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; CHECK-NEXT: i32.const $push0=, 2
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; CHECK-NEXT: i32.add $push3=, $0, $pop0
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; CHECK-NEXT: i32.load8_u $push4=, 0($pop3)
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; CHECK-NEXT: i32.const $push13=, 2
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; CHECK-NEXT: i32.add $push1=, $1, $pop13
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; CHECK-NEXT: i32.load8_u $push2=, 0($pop1)
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; CHECK-NEXT: i32.xor $push5=, $pop4, $pop2
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; CHECK-NEXT: i32.or $push9=, $pop8, $pop5
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; CHECK-NEXT: i32.const $push10=, 65535
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; CHECK-NEXT: i32.and $push11=, $pop9, $pop10
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; CHECK-NEXT: i32.eqz $push12=, $pop11
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; CHECK-NEXT: return $pop12
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%cmp_3 = call i32 @memcmp(ptr %a, ptr %b, i32 3)
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%res = icmp eq i32 %cmp_3, 0
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ret i1 %res
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}
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define i1 @memcmp_expand_5(ptr %a, ptr %b) {
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; CHECK-LABEL: memcmp_expand_5:
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; CHECK: .functype memcmp_expand_5 (i32, i32) -> (i32)
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; CHECK-NEXT: # %bb.0:
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; CHECK-NEXT: i32.load $push7=, 0($0):p2align=0
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; CHECK-NEXT: i32.load $push6=, 0($1):p2align=0
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; CHECK-NEXT: i32.xor $push8=, $pop7, $pop6
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; CHECK-NEXT: i32.const $push0=, 4
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; CHECK-NEXT: i32.add $push3=, $0, $pop0
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; CHECK-NEXT: i32.load8_u $push4=, 0($pop3)
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; CHECK-NEXT: i32.const $push11=, 4
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; CHECK-NEXT: i32.add $push1=, $1, $pop11
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; CHECK-NEXT: i32.load8_u $push2=, 0($pop1)
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; CHECK-NEXT: i32.xor $push5=, $pop4, $pop2
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; CHECK-NEXT: i32.or $push9=, $pop8, $pop5
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; CHECK-NEXT: i32.eqz $push10=, $pop9
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; CHECK-NEXT: return $pop10
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%cmp_5 = call i32 @memcmp(ptr %a, ptr %b, i32 5)
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%res = icmp eq i32 %cmp_5, 0
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ret i1 %res
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}
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define i1 @memcmp_expand_7(ptr %a, ptr %b) {
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; CHECK-LABEL: memcmp_expand_7:
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; CHECK: .functype memcmp_expand_7 (i32, i32) -> (i32)
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; CHECK-NEXT: # %bb.0:
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; CHECK-NEXT: i32.load $push7=, 0($0):p2align=0
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; CHECK-NEXT: i32.load $push6=, 0($1):p2align=0
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; CHECK-NEXT: i32.xor $push8=, $pop7, $pop6
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; CHECK-NEXT: i32.const $push0=, 3
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; CHECK-NEXT: i32.add $push3=, $0, $pop0
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; CHECK-NEXT: i32.load $push4=, 0($pop3):p2align=0
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; CHECK-NEXT: i32.const $push11=, 3
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; CHECK-NEXT: i32.add $push1=, $1, $pop11
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; CHECK-NEXT: i32.load $push2=, 0($pop1):p2align=0
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; CHECK-NEXT: i32.xor $push5=, $pop4, $pop2
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; CHECK-NEXT: i32.or $push9=, $pop8, $pop5
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; CHECK-NEXT: i32.eqz $push10=, $pop9
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; CHECK-NEXT: return $pop10
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%cmp_7 = call i32 @memcmp(ptr %a, ptr %b, i32 7)
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%res = icmp eq i32 %cmp_7, 0
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ret i1 %res
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}
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; INFO: Negative test
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; Should not expand even with simd128
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define i1 @memcmp_expand_129(ptr %a, ptr %b) {
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; CHECK-LABEL: memcmp_expand_129:
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; CHECK: .functype memcmp_expand_129 (i32, i32) -> (i32)
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; CHECK-NEXT: # %bb.0:
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; CHECK-NEXT: i32.const $push0=, 129
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; CHECK-NEXT: call $push1=, memcmp, $0, $1, $pop0
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; CHECK-NEXT: i32.eqz $push2=, $pop1
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; CHECK-NEXT: return $pop2
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%cmp_129 = call i32 @memcmp(ptr %a, ptr %b, i32 129)
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%res = icmp eq i32 %cmp_129, 0
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ret i1 %res
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}
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define i1 @memcmp_expand_2(ptr %a, ptr %b) {
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; CHECK-LABEL: memcmp_expand_2:
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; CHECK: .functype memcmp_expand_2 (i32, i32) -> (i32)
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; CHECK-NEXT: # %bb.0:
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; CHECK-NEXT: i32.load16_u $push1=, 0($0):p2align=0
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; CHECK-NEXT: i32.load16_u $push0=, 0($1):p2align=0
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; CHECK-NEXT: i32.eq $push2=, $pop1, $pop0
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; CHECK-NEXT: return $pop2
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%cmp_2 = call i32 @memcmp(ptr %a, ptr %b, i32 2)
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%res = icmp eq i32 %cmp_2, 0
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ret i1 %res
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}
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define i1 @memcmp_expand_2_align(ptr align(2) %a, ptr align(2) %b) {
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; CHECK-LABEL: memcmp_expand_2_align:
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; CHECK: .functype memcmp_expand_2_align (i32, i32) -> (i32)
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; CHECK-NEXT: # %bb.0:
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; CHECK-NEXT: i32.load16_u $push1=, 0($0)
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; CHECK-NEXT: i32.load16_u $push0=, 0($1)
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; CHECK-NEXT: i32.eq $push2=, $pop1, $pop0
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; CHECK-NEXT: return $pop2
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%cmp_2 = call i32 @memcmp(ptr %a, ptr %b, i32 2)
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%res = icmp eq i32 %cmp_2, 0
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ret i1 %res
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}
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define i1 @memcmp_expand_8(ptr %a, ptr %b) {
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; CHECK-LABEL: memcmp_expand_8:
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; CHECK: .functype memcmp_expand_8 (i32, i32) -> (i32)
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; CHECK-NEXT: # %bb.0:
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; CHECK-NEXT: i64.load $push1=, 0($0):p2align=0
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; CHECK-NEXT: i64.load $push0=, 0($1):p2align=0
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; CHECK-NEXT: i64.eq $push2=, $pop1, $pop0
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; CHECK-NEXT: return $pop2
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%cmp_8 = call i32 @memcmp(ptr %a, ptr %b, i32 8)
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%res = icmp eq i32 %cmp_8, 0
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ret i1 %res
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}
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; TODO: Should be using a single load i64x2 or equivalent in bitsizes
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define i1 @memcmp_expand_16(ptr %a, ptr %b) {
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; CHECK-LABEL: memcmp_expand_16:
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; CHECK: .functype memcmp_expand_16 (i32, i32) -> (i32)
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; CHECK-NEXT: # %bb.0:
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; CHECK-NEXT: i64.load $push7=, 0($0):p2align=0
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; CHECK-NEXT: i64.load $push6=, 0($1):p2align=0
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; CHECK-NEXT: i64.xor $push8=, $pop7, $pop6
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; CHECK-NEXT: i32.const $push0=, 8
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; CHECK-NEXT: i32.add $push3=, $0, $pop0
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; CHECK-NEXT: i64.load $push4=, 0($pop3):p2align=0
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; CHECK-NEXT: i32.const $push11=, 8
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; CHECK-NEXT: i32.add $push1=, $1, $pop11
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; CHECK-NEXT: i64.load $push2=, 0($pop1):p2align=0
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; CHECK-NEXT: i64.xor $push5=, $pop4, $pop2
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; CHECK-NEXT: i64.or $push9=, $pop8, $pop5
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; CHECK-NEXT: i64.eqz $push10=, $pop9
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; CHECK-NEXT: return $pop10
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%cmp_16 = call i32 @memcmp(ptr %a, ptr %b, i32 16)
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%res = icmp eq i32 %cmp_16, 0
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ret i1 %res
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}

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