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[AMDGPU] gfx1250 kernel descriptor update (#155008)
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8 files changed

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8 files changed

+622
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‎llvm/docs/AMDGPUUsage.rst

Lines changed: 68 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -5405,7 +5405,21 @@ The fields used by CP for code objects before V3 also match those specified in
54055405

54065406
Used by CP to set up
54075407
``COMPUTE_PGM_RSRC1.FP16_OVFL``.
5408-
28:27 2 bits Reserved, must be 0.
5408+
27 1 bit RESERVED GFX6-GFX120*
5409+
Reserved, must be 0.
5410+
FLAT_SCRATCH_IS_NV GFX125*
5411+
0 - Use the NV ISA as indication
5412+
that scratch is NV. 1 - Force
5413+
scratch to NV = 1, even if
5414+
ISA.NV == 0 if the address falls
5415+
into scratch space (not global).
5416+
This allows global.NV = 0 and
5417+
scratch.NV = 1 for flat ops. Other
5418+
threads use the ISA bit value.
5419+
5420+
Used by CP to set up
5421+
``COMPUTE_PGM_RSRC1.FLAT_SCRATCH_IS_NV``.
5422+
28 1 bit RESERVED Reserved, must be 0.
54095423
29 1 bit WGP_MODE GFX6-GFX9
54105424
Reserved, must be 0.
54115425
GFX10-GFX12
@@ -5487,15 +5501,16 @@ The fields used by CP for code objects before V3 also match those specified in
54875501

54885502
Used by CP to set up
54895503
``COMPUTE_PGM_RSRC2.SCRATCH_EN``.
5490-
5:1 5 bits USER_SGPR_COUNT The total number of SGPR
5491-
user data
5492-
registers requested. This
5493-
number must be greater than
5494-
or equal to the number of user
5495-
data registers enabled.
5504+
5:1 5 bits USER_SGPR_COUNT GFX6-GFX120*
5505+
The total number of SGPR
5506+
user data
5507+
registers requested. This
5508+
number must be greater than
5509+
or equal to the number of user
5510+
data registers enabled.
54965511

5497-
Used by CP to set up
5498-
``COMPUTE_PGM_RSRC2.USER_SGPR``.
5512+
Used by CP to set up
5513+
``COMPUTE_PGM_RSRC2.USER_SGPR``.
54995514
6 1 bit ENABLE_TRAP_HANDLER GFX6-GFX11
55005515
Must be 0.
55015516

@@ -5504,8 +5519,25 @@ The fields used by CP for code objects before V3 also match those specified in
55045519
which is set by the CP if
55055520
the runtime has installed a
55065521
trap handler.
5507-
GFX12
5508-
Reserved, must be 0.
5522+
ENABLE_DYNAMIC_VGPR GFX120*
5523+
Enables dynamic VGPR mode, where
5524+
each wave allocates one VGPR chunk
5525+
at launch and can request for
5526+
additional space to use during
5527+
execution in SQ.
5528+
5529+
Used by CP to set up
5530+
``COMPUTE_PGM_RSRC2.DYNAMIC_VGPR``.
5531+
6:1 6 bits USER_SGPR_COUNT GFX125*
5532+
The total number of SGPR
5533+
user data
5534+
registers requested. This
5535+
number must be greater than
5536+
or equal to the number of user
5537+
data registers enabled.
5538+
5539+
Used by CP to set up
5540+
``COMPUTE_PGM_RSRC2.USER_SGPR``.
55095541
7 1 bit ENABLE_SGPR_WORKGROUP_ID_X Enable the setup of the
55105542
system SGPR register for
55115543
the work-group id in the X
@@ -5598,7 +5630,7 @@ The fields used by CP for code objects before V3 also match those specified in
55985630

55995631
GFX6
56005632
roundup(lds-size / (64 * 4))
5601-
GFX7-GFX11
5633+
GFX7-GFX12
56025634
roundup(lds-size / (128 * 4))
56035635
GFX950
56045636
roundup(lds-size / (320 * 4))
@@ -5722,7 +5754,30 @@ The fields used by CP for code objects before V3 also match those specified in
57225754
with a granularity of 128 bytes.
57235755
12 1 bit RESERVED Reserved, must be 0.
57245756
13 1 bit GLG_EN If 1, group launch guarantee will be enabled for this dispatch
5725-
30:14 17 bits RESERVED Reserved, must be 0.
5757+
16:14 3 bits RESERVED GFX120*
5758+
Reserved, must be 0.
5759+
NAMED_BAR_CNT GFX125*
5760+
Number of named barriers to alloc for each workgroup, in granularity of
5761+
4. Range is from 0-4 allocating 0, 4, 8, 12, 16.
5762+
17 1 bit RESERVED GFX120*
5763+
Reserved, must be 0.
5764+
ENABLE_DYNAMIC_VGPR GFX125*
5765+
Enables dynamic VGPR mode, where each wave allocates one VGPR chunk
5766+
at launch and can request for additional space to use during
5767+
execution in SQ.
5768+
5769+
Used by CP to set up ``COMPUTE_PGM_RSRC3.DYNAMIC_VGPR``.
5770+
20:18 3 bits RESERVED GFX120*
5771+
Reserved, must be 0.
5772+
TCP_SPLIT GFX125*
5773+
Desired LDS/VC split of TCP. 0: no preference 1: LDS=0, VC=448kB
5774+
2: LDS=64kB, VC=384kB 3: LDS=128kB, VC=320kB 4: LDS=192kB, VC=256kB
5775+
5: LDS=256kB, VC=192kB 6: LDS=320kB, VC=128kB 7: LDS=384kB, VC=64kB
5776+
21 1 bit RESERVED GFX120*
5777+
Reserved, must be 0.
5778+
ENABLE_DIDT_THROTTLE GFX125*
5779+
Enable DIDT throttling for all ACE pipes
5780+
30:22 9 bits RESERVED Reserved, must be 0.
57265781
31 1 bit IMAGE_OP If 1, the kernel execution contains image instructions. If executed as
57275782
part of a graphics pipeline, image read instructions will stall waiting
57285783
for any necessary ``WAIT_SYNC`` fence to be performed in order to

‎llvm/include/llvm/Support/AMDHSAKernelDescriptor.h

Lines changed: 42 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -83,26 +83,32 @@ enum : uint8_t {
8383

8484
// Compute program resource register 1. Must match hardware definition.
8585
// GFX6+.
86-
#define COMPUTE_PGM_RSRC1(NAME, SHIFT, WIDTH) \
87-
AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC1_ ## NAME, SHIFT, WIDTH)
86+
#define COMPUTE_PGM_RSRC1(NAME, SHIFT, WIDTH) \
87+
AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC1_##NAME, SHIFT, WIDTH)
8888
// [GFX6-GFX8].
89-
#define COMPUTE_PGM_RSRC1_GFX6_GFX8(NAME, SHIFT, WIDTH) \
90-
AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC1_GFX6_GFX8_ ## NAME, SHIFT, WIDTH)
89+
#define COMPUTE_PGM_RSRC1_GFX6_GFX8(NAME, SHIFT, WIDTH) \
90+
AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC1_GFX6_GFX8_##NAME, SHIFT, WIDTH)
9191
// [GFX6-GFX9].
92-
#define COMPUTE_PGM_RSRC1_GFX6_GFX9(NAME, SHIFT, WIDTH) \
93-
AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC1_GFX6_GFX9_ ## NAME, SHIFT, WIDTH)
92+
#define COMPUTE_PGM_RSRC1_GFX6_GFX9(NAME, SHIFT, WIDTH) \
93+
AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC1_GFX6_GFX9_##NAME, SHIFT, WIDTH)
9494
// [GFX6-GFX11].
9595
#define COMPUTE_PGM_RSRC1_GFX6_GFX11(NAME, SHIFT, WIDTH) \
9696
AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC1_GFX6_GFX11_##NAME, SHIFT, WIDTH)
97+
// [GFX6-GFX120].
98+
#define COMPUTE_PGM_RSRC1_GFX6_GFX120(NAME, SHIFT, WIDTH) \
99+
AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC1_GFX6_GFX120_##NAME, SHIFT, WIDTH)
97100
// GFX9+.
98-
#define COMPUTE_PGM_RSRC1_GFX9_PLUS(NAME, SHIFT, WIDTH) \
99-
AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC1_GFX9_PLUS_ ## NAME, SHIFT, WIDTH)
101+
#define COMPUTE_PGM_RSRC1_GFX9_PLUS(NAME, SHIFT, WIDTH) \
102+
AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC1_GFX9_PLUS_##NAME, SHIFT, WIDTH)
100103
// GFX10+.
101-
#define COMPUTE_PGM_RSRC1_GFX10_PLUS(NAME, SHIFT, WIDTH) \
102-
AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC1_GFX10_PLUS_ ## NAME, SHIFT, WIDTH)
104+
#define COMPUTE_PGM_RSRC1_GFX10_PLUS(NAME, SHIFT, WIDTH) \
105+
AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC1_GFX10_PLUS_##NAME, SHIFT, WIDTH)
103106
// GFX12+.
104107
#define COMPUTE_PGM_RSRC1_GFX12_PLUS(NAME, SHIFT, WIDTH) \
105108
AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC1_GFX12_PLUS_##NAME, SHIFT, WIDTH)
109+
// [GFX125].
110+
#define COMPUTE_PGM_RSRC1_GFX125(NAME, SHIFT, WIDTH) \
111+
AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC1_GFX125_##NAME, SHIFT, WIDTH)
106112
enum : int32_t {
107113
COMPUTE_PGM_RSRC1(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6),
108114
COMPUTE_PGM_RSRC1(GRANULATED_WAVEFRONT_SGPR_COUNT, 6, 4),
@@ -121,8 +127,10 @@ enum : int32_t {
121127
COMPUTE_PGM_RSRC1(CDBG_USER, 25, 1),
122128
COMPUTE_PGM_RSRC1_GFX6_GFX8(RESERVED0, 26, 1),
123129
COMPUTE_PGM_RSRC1_GFX9_PLUS(FP16_OVFL, 26, 1),
124-
COMPUTE_PGM_RSRC1(RESERVED1, 27, 2),
125-
COMPUTE_PGM_RSRC1_GFX6_GFX9(RESERVED2, 29, 3),
130+
COMPUTE_PGM_RSRC1_GFX6_GFX120(RESERVED1, 27, 1),
131+
COMPUTE_PGM_RSRC1_GFX125(FLAT_SCRATCH_IS_NV, 27, 1),
132+
COMPUTE_PGM_RSRC1(RESERVED2, 28, 1),
133+
COMPUTE_PGM_RSRC1_GFX6_GFX9(RESERVED3, 29, 3),
126134
COMPUTE_PGM_RSRC1_GFX10_PLUS(WGP_MODE, 29, 1),
127135
COMPUTE_PGM_RSRC1_GFX10_PLUS(MEM_ORDERED, 30, 1),
128136
COMPUTE_PGM_RSRC1_GFX10_PLUS(FWD_PROGRESS, 31, 1),
@@ -131,19 +139,29 @@ enum : int32_t {
131139

132140
// Compute program resource register 2. Must match hardware definition.
133141
// GFX6+.
134-
#define COMPUTE_PGM_RSRC2(NAME, SHIFT, WIDTH) \
135-
AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC2_ ## NAME, SHIFT, WIDTH)
142+
#define COMPUTE_PGM_RSRC2(NAME, SHIFT, WIDTH) \
143+
AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC2_##NAME, SHIFT, WIDTH)
136144
// [GFX6-GFX11].
137145
#define COMPUTE_PGM_RSRC2_GFX6_GFX11(NAME, SHIFT, WIDTH) \
138146
AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC2_GFX6_GFX11_##NAME, SHIFT, WIDTH)
147+
// [GFX6-GFX120].
148+
#define COMPUTE_PGM_RSRC2_GFX6_GFX120(NAME, SHIFT, WIDTH) \
149+
AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC2_GFX6_GFX120_##NAME, SHIFT, WIDTH)
139150
// GFX12+.
140151
#define COMPUTE_PGM_RSRC2_GFX12_PLUS(NAME, SHIFT, WIDTH) \
141152
AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC2_GFX12_PLUS_##NAME, SHIFT, WIDTH)
153+
// [GFX120].
154+
#define COMPUTE_PGM_RSRC2_GFX120(NAME, SHIFT, WIDTH) \
155+
AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC2_GFX120_##NAME, SHIFT, WIDTH)
156+
// [GFX125].
157+
#define COMPUTE_PGM_RSRC2_GFX125(NAME, SHIFT, WIDTH) \
158+
AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC2_GFX125_##NAME, SHIFT, WIDTH)
142159
enum : int32_t {
143160
COMPUTE_PGM_RSRC2(ENABLE_PRIVATE_SEGMENT, 0, 1),
144-
COMPUTE_PGM_RSRC2(USER_SGPR_COUNT, 1, 5),
161+
COMPUTE_PGM_RSRC2_GFX6_GFX120(USER_SGPR_COUNT, 1, 5),
145162
COMPUTE_PGM_RSRC2_GFX6_GFX11(ENABLE_TRAP_HANDLER, 6, 1),
146-
COMPUTE_PGM_RSRC2_GFX12_PLUS(RESERVED1, 6, 1),
163+
COMPUTE_PGM_RSRC2_GFX120(ENABLE_DYNAMIC_VGPR, 6, 1),
164+
COMPUTE_PGM_RSRC2_GFX125(USER_SGPR_COUNT, 1, 6),
147165
COMPUTE_PGM_RSRC2(ENABLE_SGPR_WORKGROUP_ID_X, 7, 1),
148166
COMPUTE_PGM_RSRC2(ENABLE_SGPR_WORKGROUP_ID_Y, 8, 1),
149167
COMPUTE_PGM_RSRC2(ENABLE_SGPR_WORKGROUP_ID_Z, 9, 1),
@@ -178,8 +196,8 @@ enum : int32_t {
178196
// Compute program resource register 3 for GFX10+. Must match hardware
179197
// definition.
180198
// GFX10+.
181-
#define COMPUTE_PGM_RSRC3_GFX10_PLUS(NAME, SHIFT, WIDTH) \
182-
AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC3_GFX10_PLUS_ ## NAME, SHIFT, WIDTH)
199+
#define COMPUTE_PGM_RSRC3_GFX10_PLUS(NAME, SHIFT, WIDTH) \
200+
AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC3_GFX10_PLUS_##NAME, SHIFT, WIDTH)
183201
// [GFX10].
184202
#define COMPUTE_PGM_RSRC3_GFX10(NAME, SHIFT, WIDTH) \
185203
AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC3_GFX10_##NAME, SHIFT, WIDTH)
@@ -212,10 +230,13 @@ enum : int32_t {
212230
COMPUTE_PGM_RSRC3_GFX10_PLUS(RESERVED2, 12, 1),
213231
COMPUTE_PGM_RSRC3_GFX10_GFX11(RESERVED3, 13, 1),
214232
COMPUTE_PGM_RSRC3_GFX12_PLUS(GLG_EN, 13, 1),
215-
COMPUTE_PGM_RSRC3_GFX10_GFX120(RESERVED4, 14, 3),
233+
COMPUTE_PGM_RSRC3_GFX10_GFX120(RESERVED4, 14, 8),
216234
COMPUTE_PGM_RSRC3_GFX125(NAMED_BAR_CNT, 14, 3),
217-
COMPUTE_PGM_RSRC3_GFX10_PLUS(RESERVED5, 17, 14),
218-
COMPUTE_PGM_RSRC3_GFX10(RESERVED5, 31, 1),
235+
COMPUTE_PGM_RSRC3_GFX125(ENABLE_DYNAMIC_VGPR, 17, 1),
236+
COMPUTE_PGM_RSRC3_GFX125(TCP_SPLIT, 18, 3),
237+
COMPUTE_PGM_RSRC3_GFX125(ENABLE_DIDT_THROTTLE, 21, 1),
238+
COMPUTE_PGM_RSRC3_GFX10_PLUS(RESERVED5, 22, 9),
239+
COMPUTE_PGM_RSRC3_GFX10(RESERVED6, 31, 1),
219240
COMPUTE_PGM_RSRC3_GFX11_PLUS(IMAGE_OP, 31, 1),
220241
};
221242
#undef COMPUTE_PGM_RSRC3_GFX10_PLUS

‎llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

Lines changed: 18 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -6410,12 +6410,24 @@ bool AMDGPUAsmParser::ParseDirectiveAMDHSAKernel() {
64106410
return TokError("amdgpu_user_sgpr_count smaller than than implied by "
64116411
"enabled user SGPRs");
64126412

6413-
if (!isUInt<COMPUTE_PGM_RSRC2_USER_SGPR_COUNT_WIDTH>(UserSGPRCount))
6414-
return TokError("too many user SGPRs enabled");
6415-
AMDGPU::MCKernelDescriptor::bits_set(
6416-
KD.compute_pgm_rsrc2, MCConstantExpr::create(UserSGPRCount, getContext()),
6417-
COMPUTE_PGM_RSRC2_USER_SGPR_COUNT_SHIFT,
6418-
COMPUTE_PGM_RSRC2_USER_SGPR_COUNT, getContext());
6413+
if (isGFX1250()) {
6414+
if (!isUInt<COMPUTE_PGM_RSRC2_GFX125_USER_SGPR_COUNT_WIDTH>(UserSGPRCount))
6415+
return TokError("too many user SGPRs enabled");
6416+
AMDGPU::MCKernelDescriptor::bits_set(
6417+
KD.compute_pgm_rsrc2,
6418+
MCConstantExpr::create(UserSGPRCount, getContext()),
6419+
COMPUTE_PGM_RSRC2_GFX125_USER_SGPR_COUNT_SHIFT,
6420+
COMPUTE_PGM_RSRC2_GFX125_USER_SGPR_COUNT, getContext());
6421+
} else {
6422+
if (!isUInt<COMPUTE_PGM_RSRC2_GFX6_GFX120_USER_SGPR_COUNT_WIDTH>(
6423+
UserSGPRCount))
6424+
return TokError("too many user SGPRs enabled");
6425+
AMDGPU::MCKernelDescriptor::bits_set(
6426+
KD.compute_pgm_rsrc2,
6427+
MCConstantExpr::create(UserSGPRCount, getContext()),
6428+
COMPUTE_PGM_RSRC2_GFX6_GFX120_USER_SGPR_COUNT_SHIFT,
6429+
COMPUTE_PGM_RSRC2_GFX6_GFX120_USER_SGPR_COUNT, getContext());
6430+
}
64196431

64206432
int64_t IVal = 0;
64216433
if (!KD.kernarg_size->evaluateAsAbsolute(IVal))

‎llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp

Lines changed: 33 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -2284,24 +2284,38 @@ Expected<bool> AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1(
22842284
CHECK_RESERVED_BITS(COMPUTE_PGM_RSRC1_BULKY);
22852285
CHECK_RESERVED_BITS(COMPUTE_PGM_RSRC1_CDBG_USER);
22862286

2287-
if (isGFX9Plus())
2287+
// Bits [26].
2288+
if (isGFX9Plus()) {
22882289
PRINT_DIRECTIVE(".amdhsa_fp16_overflow", COMPUTE_PGM_RSRC1_GFX9_PLUS_FP16_OVFL);
2289-
2290-
if (!isGFX9Plus())
2290+
} else {
22912291
CHECK_RESERVED_BITS_DESC_MSG(COMPUTE_PGM_RSRC1_GFX6_GFX8_RESERVED0,
22922292
"COMPUTE_PGM_RSRC1", "must be zero pre-gfx9");
2293+
}
22932294

2294-
CHECK_RESERVED_BITS_DESC(COMPUTE_PGM_RSRC1_RESERVED1, "COMPUTE_PGM_RSRC1");
2295+
// Bits [27].
2296+
if (isGFX1250()) {
2297+
PRINT_PSEUDO_DIRECTIVE_COMMENT("FLAT_SCRATCH_IS_NV",
2298+
COMPUTE_PGM_RSRC1_GFX125_FLAT_SCRATCH_IS_NV);
2299+
} else {
2300+
CHECK_RESERVED_BITS_DESC(COMPUTE_PGM_RSRC1_GFX6_GFX120_RESERVED1,
2301+
"COMPUTE_PGM_RSRC1");
2302+
}
22952303

2296-
if (!isGFX10Plus())
2297-
CHECK_RESERVED_BITS_DESC_MSG(COMPUTE_PGM_RSRC1_GFX6_GFX9_RESERVED2,
2298-
"COMPUTE_PGM_RSRC1", "must be zero pre-gfx10");
2304+
// Bits [28].
2305+
CHECK_RESERVED_BITS_DESC(COMPUTE_PGM_RSRC1_RESERVED2, "COMPUTE_PGM_RSRC1");
22992306

2307+
// Bits [29-31].
23002308
if (isGFX10Plus()) {
2301-
PRINT_DIRECTIVE(".amdhsa_workgroup_processor_mode",
2302-
COMPUTE_PGM_RSRC1_GFX10_PLUS_WGP_MODE);
2309+
// WGP_MODE is not available on GFX1250.
2310+
if (!isGFX1250()) {
2311+
PRINT_DIRECTIVE(".amdhsa_workgroup_processor_mode",
2312+
COMPUTE_PGM_RSRC1_GFX10_PLUS_WGP_MODE);
2313+
}
23032314
PRINT_DIRECTIVE(".amdhsa_memory_ordered", COMPUTE_PGM_RSRC1_GFX10_PLUS_MEM_ORDERED);
23042315
PRINT_DIRECTIVE(".amdhsa_forward_progress", COMPUTE_PGM_RSRC1_GFX10_PLUS_FWD_PROGRESS);
2316+
} else {
2317+
CHECK_RESERVED_BITS_DESC(COMPUTE_PGM_RSRC1_GFX6_GFX9_RESERVED3,
2318+
"COMPUTE_PGM_RSRC1");
23052319
}
23062320

23072321
if (isGFX12Plus())
@@ -2423,17 +2437,24 @@ Expected<bool> AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC3(
24232437
"must be zero on gfx10 or gfx11");
24242438
}
24252439

2426-
// Bits [14-16]
2440+
// Bits [14-21].
24272441
if (isGFX1250()) {
24282442
PRINT_DIRECTIVE(".amdhsa_named_barrier_count",
24292443
COMPUTE_PGM_RSRC3_GFX125_NAMED_BAR_CNT);
2444+
PRINT_PSEUDO_DIRECTIVE_COMMENT(
2445+
"ENABLE_DYNAMIC_VGPR", COMPUTE_PGM_RSRC3_GFX125_ENABLE_DYNAMIC_VGPR);
2446+
PRINT_PSEUDO_DIRECTIVE_COMMENT("TCP_SPLIT",
2447+
COMPUTE_PGM_RSRC3_GFX125_TCP_SPLIT);
2448+
PRINT_PSEUDO_DIRECTIVE_COMMENT(
2449+
"ENABLE_DIDT_THROTTLE",
2450+
COMPUTE_PGM_RSRC3_GFX125_ENABLE_DIDT_THROTTLE);
24302451
} else {
24312452
CHECK_RESERVED_BITS_DESC_MSG(COMPUTE_PGM_RSRC3_GFX10_GFX120_RESERVED4,
24322453
"COMPUTE_PGM_RSRC3",
24332454
"must be zero on gfx10+");
24342455
}
24352456

2436-
// Bits [17-30].
2457+
// Bits [22-30].
24372458
CHECK_RESERVED_BITS_DESC_MSG(COMPUTE_PGM_RSRC3_GFX10_PLUS_RESERVED5,
24382459
"COMPUTE_PGM_RSRC3", "must be zero on gfx10+");
24392460

@@ -2442,7 +2463,7 @@ Expected<bool> AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC3(
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PRINT_PSEUDO_DIRECTIVE_COMMENT("IMAGE_OP",
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COMPUTE_PGM_RSRC3_GFX11_PLUS_IMAGE_OP);
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} else {
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CHECK_RESERVED_BITS_DESC_MSG(COMPUTE_PGM_RSRC3_GFX10_RESERVED5,
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CHECK_RESERVED_BITS_DESC_MSG(COMPUTE_PGM_RSRC3_GFX10_RESERVED6,
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"COMPUTE_PGM_RSRC3",
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"must be zero on gfx10");
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}

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