Skip to content

Commit 469eb30

Browse files
danielhbdanielhb
committed
Adding load/store clustering as subtarget features
Added 4 subtarget features that disables the default cluster settings: - TuneDisableMISched(Load|Store)Clustering - TuneDisablePostMISched(Load|Store)Clustering The 4 command line options added previously were removed. Use the new subtarget features in Ventana veyron-v1 to allow only misched store clustering. Test changes: - add a store clustering test: misched-store-clustering.ll - add subtarget features tests in misched-load-clustering.ll and misched-store-clustering.ll - misched-mem-clustering.mir: use the subtarget features
1 parent 63e9d80 commit 469eb30

File tree

8 files changed

+133
-38
lines changed

8 files changed

+133
-38
lines changed

‎llvm/lib/Target/RISCV/RISCVFeatures.td

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1700,6 +1700,18 @@ def TuneNLogNVRGather
17001700
def TunePostRAScheduler : SubtargetFeature<"use-postra-scheduler",
17011701
"UsePostRAScheduler", "true", "Schedule again after register allocation">;
17021702

1703+
def TuneDisableMISchedLoadClustering : SubtargetFeature<"disable-misched-load-clustering",
1704+
"NoMISchedLoadClustering", "true", "Disable load clustering in the machine scheduler">;
1705+
1706+
def TuneDisableMISchedStoreClustering : SubtargetFeature<"disable-misched-store-clustering",
1707+
"NoMISchedStoreClustering", "true", "Disable store clustering in the machine scheduler">;
1708+
1709+
def TuneDisablePostMISchedLoadClustering : SubtargetFeature<"disable-postmisched-load-clustering",
1710+
"NoPostMISchedLoadClustering", "true", "Disable PostRA load clustering in the machine scheduler">;
1711+
1712+
def TuneDisablePostMISchedStoreClustering : SubtargetFeature<"disable-postmisched-store-clustering",
1713+
"NoPostMISchedStoreClustering", "true", "Disable PostRA store clustering in the machine scheduler">;
1714+
17031715
def TuneDisableLatencySchedHeuristic
17041716
: SubtargetFeature<"disable-latency-sched-heuristic", "DisableLatencySchedHeuristic", "true",
17051717
"Disable latency scheduling heuristic">;

‎llvm/lib/Target/RISCV/RISCVProcessors.td

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -590,6 +590,9 @@ def VENTANA_VEYRON_V1 : RISCVProcessorModel<"veyron-v1",
590590
FeatureStdExtZicboz,
591591
FeatureVendorXVentanaCondOps],
592592
[TuneVentanaVeyron,
593+
TuneDisableMISchedLoadClustering,
594+
TuneDisablePostMISchedLoadClustering,
595+
TuneDisablePostMISchedStoreClustering,
593596
TuneLUIADDIFusion,
594597
TuneAUIPCADDIFusion,
595598
TuneZExtHFusion,

‎llvm/lib/Target/RISCV/RISCVSubtarget.h

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -150,6 +150,14 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
150150

151151
bool enablePostRAScheduler() const override { return UsePostRAScheduler; }
152152

153+
bool disableMISchedLoadClustering() const { return NoMISchedLoadClustering; }
154+
155+
bool disableMISchedStoreClustering() const { return NoMISchedStoreClustering; }
156+
157+
bool disablePostMISchedLoadClustering() const { return NoPostMISchedLoadClustering; }
158+
159+
bool disablePostMISchedStoreClustering() const { return NoPostMISchedStoreClustering; }
160+
153161
Align getPrefFunctionAlignment() const {
154162
return Align(TuneInfo->PrefFunctionAlignment);
155163
}

‎llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

Lines changed: 6 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -94,26 +94,6 @@ static cl::opt<bool>
9494
cl::desc("Enable the loop data prefetch pass"),
9595
cl::init(true));
9696

97-
static cl::opt<bool> EnableMISchedLoadClustering(
98-
"riscv-misched-load-clustering", cl::Hidden,
99-
cl::desc("Enable load clustering in the machine scheduler"),
100-
cl::init(true));
101-
102-
static cl::opt<bool> EnableMISchedStoreClustering(
103-
"riscv-misched-store-clustering", cl::Hidden,
104-
cl::desc("Enable store clustering in the machine scheduler"),
105-
cl::init(true));
106-
107-
static cl::opt<bool> EnablePostMISchedLoadClustering(
108-
"riscv-postmisched-load-clustering", cl::Hidden,
109-
cl::desc("Enable PostRA load clustering in the machine scheduler"),
110-
cl::init(true));
111-
112-
static cl::opt<bool> EnablePostMISchedStoreClustering(
113-
"riscv-postmisched-store-clustering", cl::Hidden,
114-
cl::desc("Enable PostRA store clustering in the machine scheduler"),
115-
cl::init(true));
116-
11797
static cl::opt<bool> DisableVectorMaskMutation(
11898
"riscv-disable-vector-mask-mutation",
11999
cl::desc("Disable the vector mask scheduling mutation"), cl::init(false),
@@ -304,17 +284,17 @@ bool RISCVTargetMachine::isNoopAddrSpaceCast(unsigned SrcAS,
304284

305285
ScheduleDAGInstrs *
306286
RISCVTargetMachine::createMachineScheduler(MachineSchedContext *C) const {
287+
const RISCVSubtarget &ST = C->MF->getSubtarget<RISCVSubtarget>();
307288
ScheduleDAGMILive *DAG = createSchedLive(C);
308289

309-
if (EnableMISchedLoadClustering)
290+
if (!ST.disableMISchedLoadClustering())
310291
DAG->addMutation(createLoadClusterDAGMutation(
311292
DAG->TII, DAG->TRI, /*ReorderWhileClustering=*/true));
312293

313-
if (EnableMISchedStoreClustering)
294+
if (!ST.disableMISchedStoreClustering())
314295
DAG->addMutation(createStoreClusterDAGMutation(
315296
DAG->TII, DAG->TRI, /*ReorderWhileClustering=*/true));
316297

317-
const RISCVSubtarget &ST = C->MF->getSubtarget<RISCVSubtarget>();
318298
if (!DisableVectorMaskMutation && ST.hasVInstructions())
319299
DAG->addMutation(createRISCVVectorMaskDAGMutation(DAG->TRI));
320300

@@ -323,13 +303,14 @@ RISCVTargetMachine::createMachineScheduler(MachineSchedContext *C) const {
323303

324304
ScheduleDAGInstrs *
325305
RISCVTargetMachine::createPostMachineScheduler(MachineSchedContext *C) const {
306+
const RISCVSubtarget &ST = C->MF->getSubtarget<RISCVSubtarget>();
326307
ScheduleDAGMI *DAG = createSchedPostRA(C);
327308

328-
if (EnablePostMISchedLoadClustering)
309+
if (!ST.disablePostMISchedLoadClustering())
329310
DAG->addMutation(createLoadClusterDAGMutation(
330311
DAG->TII, DAG->TRI, /*ReorderWhileClustering=*/true));
331312

332-
if (EnablePostMISchedStoreClustering)
313+
if (!ST.disablePostMISchedStoreClustering())
333314
DAG->addMutation(createStoreClusterDAGMutation(
334315
DAG->TII, DAG->TRI, /*ReorderWhileClustering=*/true));
335316

‎llvm/test/CodeGen/RISCV/features-info.ll

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,10 @@
1313
; CHECK-NEXT: conditional-cmv-fusion - Enable branch+c.mv fusion.
1414
; CHECK-NEXT: d - 'D' (Double-Precision Floating-Point).
1515
; CHECK-NEXT: disable-latency-sched-heuristic - Disable latency scheduling heuristic.
16+
; CHECK-NEXT: disable-misched-load-clustering - Disable load clustering in the machine scheduler.
17+
; CHECK-NEXT: disable-misched-store-clustering - Disable store clustering in the machine scheduler.
18+
; CHECK-NEXT: disable-postmisched-load-clustering - Disable PostRA load clustering in the machine scheduler.
19+
; CHECK-NEXT: disable-postmisched-store-clustering - Disable PostRA store clustering in the machine scheduler.
1620
; CHECK-NEXT: dlen-factor-2 - Vector unit DLEN(data path width) is half of VLEN.
1721
; CHECK-NEXT: e - 'E' (Embedded Instruction Set with 16 GPRs).
1822
; CHECK-NEXT: exact-asm - Enable Exact Assembly (Disables Compression and Relaxation).

‎llvm/test/CodeGen/RISCV/misched-load-clustering.ll

Lines changed: 13 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1,39 +1,43 @@
11
; REQUIRES: asserts
2-
; RUN: llc -mtriple=riscv32 -verify-misched -riscv-misched-load-clustering=false \
3-
; RUN: -riscv-misched-store-clustering=false \
2+
;
3+
; Disable all misched clustering
4+
; RUN: llc -mtriple=riscv32 -verify-misched \
5+
; RUN: -mattr=+disable-misched-load-clustering,+disable-misched-store-clustering \
46
; RUN: -debug-only=machine-scheduler -o - 2>&1 < %s \
57
; RUN: | FileCheck -check-prefix=NOCLUSTER %s
6-
; RUN: llc -mtriple=riscv64 -verify-misched -riscv-misched-load-clustering=false \
7-
; RUN: -riscv-misched-store-clustering=false \
8+
; RUN: llc -mtriple=riscv64 -verify-misched \
9+
; RUN: -mattr=+disable-misched-load-clustering,+disable-misched-store-clustering \
810
; RUN: -debug-only=machine-scheduler -o - 2>&1 < %s \
911
; RUN: | FileCheck -check-prefix=NOCLUSTER %s
1012
;
13+
; ST misched clustering only
1114
; RUN: llc -mtriple=riscv32 -verify-misched \
12-
; RUN: -riscv-misched-load-clustering=false \
15+
; RUN: -mattr=+disable-misched-load-clustering \
1316
; RUN: -debug-only=machine-scheduler -o - 2>&1 < %s \
1417
; RUN: | FileCheck -check-prefix=STCLUSTER %s
1518
; RUN: llc -mtriple=riscv64 -verify-misched \
16-
; RUN: -riscv-misched-load-clustering=false \
19+
; RUN: -mattr=+disable-misched-load-clustering \
1720
; RUN: -debug-only=machine-scheduler -o - 2>&1 < %s \
1821
; RUN: | FileCheck -check-prefix=STCLUSTER %s
1922
;
23+
; LD misched clustering only
2024
; RUN: llc -mtriple=riscv32 -verify-misched \
21-
; RUN: -riscv-misched-store-clustering=false \
25+
; RUN: -mattr=+disable-misched-store-clustering \
2226
; RUN: -debug-only=machine-scheduler -o - 2>&1 < %s \
2327
; RUN: | FileCheck -check-prefix=LDCLUSTER %s
2428
; RUN: llc -mtriple=riscv64 -verify-misched \
25-
; RUN: -riscv-misched-store-clustering=false \
29+
; RUN: -mattr=+disable-misched-store-clustering \
2630
; RUN: -debug-only=machine-scheduler -o - 2>&1 < %s \
2731
; RUN: | FileCheck -check-prefix=LDCLUSTER %s
2832
;
33+
; Default misched cluster settings (i.e. both LD and ST clustering)
2934
; RUN: llc -mtriple=riscv32 -verify-misched \
3035
; RUN: -debug-only=machine-scheduler -o - 2>&1 < %s \
3136
; RUN: | FileCheck -check-prefix=DEFAULTCLUSTER %s
3237
; RUN: llc -mtriple=riscv64 -verify-misched \
3338
; RUN: -debug-only=machine-scheduler -o - 2>&1 < %s \
3439
; RUN: | FileCheck -check-prefix=DEFAULTCLUSTER %s
3540

36-
3741
define i32 @load_clustering_1(ptr nocapture %p) {
3842
; NOCLUSTER: ********** MI Scheduling **********
3943
; NOCLUSTER-LABEL: load_clustering_1:%bb.0

‎llvm/test/CodeGen/RISCV/misched-mem-clustering.mir

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,12 +1,12 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
22
# RUN: llc -mtriple=riscv64 -x mir -mcpu=sifive-p470 -verify-misched -enable-post-misched=false \
3-
# RUN: -riscv-postmisched-load-clustering=false \
4-
# RUN: -riscv-postmisched-store-clustering=false -debug-only=machine-scheduler \
3+
# RUN: -mattr=+disable-postmisched-load-clustering \
4+
# RUN: -mattr=+disable-postmisched-store-clustering -debug-only=machine-scheduler \
55
# RUN: -start-before=machine-scheduler -stop-after=postmisched -misched-regpressure=false -o - 2>&1 < %s \
66
# RUN: | FileCheck -check-prefix=NOPOSTMISCHED %s
77
# RUN: llc -mtriple=riscv64 -x mir -mcpu=sifive-p470 -mattr=+use-postra-scheduler -verify-misched -enable-post-misched=true \
8-
# RUN: -riscv-postmisched-load-clustering=false \
9-
# RUN: -riscv-postmisched-store-clustering=false -debug-only=machine-scheduler \
8+
# RUN: -mattr=+disable-postmisched-load-clustering \
9+
# RUN: -mattr=+disable-postmisched-store-clustering -debug-only=machine-scheduler \
1010
# RUN: -start-before=machine-scheduler -stop-after=postmisched -misched-regpressure=false -o - 2>&1 < %s \
1111
# RUN: | FileCheck -check-prefix=NOCLUSTER %s
1212
# RUN: llc -mtriple=riscv64 -x mir -mcpu=sifive-p470 -mattr=+use-postra-scheduler -verify-misched -enable-post-misched=true \

‎llvm/test/CodeGen/RISCV/misched-store-clustering.ll

Lines changed: 83 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,83 @@
1+
; REQUIRES: asserts
2+
;
3+
; Disable all misched clustering
4+
; RUN: llc -mtriple=riscv32 -verify-misched \
5+
; RUN: -mattr=+disable-misched-load-clustering,+disable-misched-store-clustering \
6+
; RUN: -debug-only=machine-scheduler -o - 2>&1 < %s \
7+
; RUN: | FileCheck -check-prefix=NOCLUSTER %s
8+
; RUN: llc -mtriple=riscv64 -verify-misched \
9+
; RUN: -mattr=+disable-misched-load-clustering,+disable-misched-store-clustering \
10+
; RUN: -debug-only=machine-scheduler -o - 2>&1 < %s \
11+
; RUN: | FileCheck -check-prefix=NOCLUSTER %s
12+
;
13+
; ST misched clustering only
14+
; RUN: llc -mtriple=riscv32 -verify-misched \
15+
; RUN: -mattr=+disable-misched-load-clustering \
16+
; RUN: -debug-only=machine-scheduler -o - 2>&1 < %s \
17+
; RUN: | FileCheck -check-prefix=STCLUSTER %s
18+
; RUN: llc -mtriple=riscv64 -verify-misched \
19+
; RUN: -mattr=+disable-misched-load-clustering \
20+
; RUN: -debug-only=machine-scheduler -o - 2>&1 < %s \
21+
; RUN: | FileCheck -check-prefix=STCLUSTER %s
22+
;
23+
; LD misched clustering only
24+
; RUN: llc -mtriple=riscv32 -verify-misched \
25+
; RUN: -mattr=+disable-misched-store-clustering \
26+
; RUN: -debug-only=machine-scheduler -o - 2>&1 < %s \
27+
; RUN: | FileCheck -check-prefix=LDCLUSTER %s
28+
; RUN: llc -mtriple=riscv64 -verify-misched \
29+
; RUN: -mattr=+disable-misched-store-clustering \
30+
; RUN: -debug-only=machine-scheduler -o - 2>&1 < %s \
31+
; RUN: | FileCheck -check-prefix=LDCLUSTER %s
32+
;
33+
; Default misched cluster settings (i.e. both LD and ST clustering)
34+
; RUN: llc -mtriple=riscv32 -verify-misched \
35+
; RUN: -debug-only=machine-scheduler -o - 2>&1 < %s \
36+
; RUN: | FileCheck -check-prefix=DEFAULTCLUSTER %s
37+
; RUN: llc -mtriple=riscv64 -verify-misched \
38+
; RUN: -debug-only=machine-scheduler -o - 2>&1 < %s \
39+
; RUN: | FileCheck -check-prefix=DEFAULTCLUSTER %s
40+
41+
define i32 @store_clustering_1(ptr nocapture %p, i32 %v) {
42+
; NOCLUSTER: ********** MI Scheduling **********
43+
; NOCLUSTER-LABEL: store_clustering_1:%bb.0
44+
; NOCLUSTER: *** Final schedule for %bb.0 ***
45+
; NOCLUSTER: SU(2): SW %1:gpr, %0:gpr, 12 :: (store (s32) into %ir.arrayidx0)
46+
; NOCLUSTER: SU(3): SW %1:gpr, %0:gpr, 8 :: (store (s32) into %ir.arrayidx1)
47+
; NOCLUSTER: SU(4): SW %1:gpr, %0:gpr, 4 :: (store (s32) into %ir.arrayidx2)
48+
; NOCLUSTER: SU(5): SW %1:gpr, %0:gpr, 16 :: (store (s32) into %ir.arrayidx3)
49+
;
50+
; STCLUSTER: ********** MI Scheduling **********
51+
; STCLUSTER-LABEL: store_clustering_1:%bb.0
52+
; STCLUSTER: *** Final schedule for %bb.0 ***
53+
; STCLUSTER: SU(4): SW %1:gpr, %0:gpr, 4 :: (store (s32) into %ir.arrayidx2)
54+
; STCLUSTER: SU(3): SW %1:gpr, %0:gpr, 8 :: (store (s32) into %ir.arrayidx1)
55+
; STCLUSTER: SU(2): SW %1:gpr, %0:gpr, 12 :: (store (s32) into %ir.arrayidx0)
56+
; STCLUSTER: SU(5): SW %1:gpr, %0:gpr, 16 :: (store (s32) into %ir.arrayidx3)
57+
;
58+
; LDCLUSTER: ********** MI Scheduling **********
59+
; LDCLUSTER-LABEL: store_clustering_1:%bb.0
60+
; LDCLUSTER: *** Final schedule for %bb.0 ***
61+
; LDCLUSTER: SU(2): SW %1:gpr, %0:gpr, 12 :: (store (s32) into %ir.arrayidx0)
62+
; LDCLUSTER: SU(3): SW %1:gpr, %0:gpr, 8 :: (store (s32) into %ir.arrayidx1)
63+
; LDCLUSTER: SU(4): SW %1:gpr, %0:gpr, 4 :: (store (s32) into %ir.arrayidx2)
64+
; LDCLUSTER: SU(5): SW %1:gpr, %0:gpr, 16 :: (store (s32) into %ir.arrayidx3)
65+
;
66+
; DEFAULTCLUSTER: ********** MI Scheduling **********
67+
; DEFAULTCLUSTER-LABEL: store_clustering_1:%bb.0
68+
; DEFAULTCLUSTER: *** Final schedule for %bb.0 ***
69+
; DEFAULTCLUSTER: SU(4): SW %1:gpr, %0:gpr, 4 :: (store (s32) into %ir.arrayidx2)
70+
; DEFAULTCLUSTER: SU(3): SW %1:gpr, %0:gpr, 8 :: (store (s32) into %ir.arrayidx1)
71+
; DEFAULTCLUSTER: SU(2): SW %1:gpr, %0:gpr, 12 :: (store (s32) into %ir.arrayidx0)
72+
; DEFAULTCLUSTER: SU(5): SW %1:gpr, %0:gpr, 16 :: (store (s32) into %ir.arrayidx3)
73+
entry:
74+
%arrayidx0 = getelementptr inbounds i32, ptr %p, i32 3
75+
store i32 %v, ptr %arrayidx0
76+
%arrayidx1 = getelementptr inbounds i32, ptr %p, i32 2
77+
store i32 %v, ptr %arrayidx1
78+
%arrayidx2 = getelementptr inbounds i32, ptr %p, i32 1
79+
store i32 %v, ptr %arrayidx2
80+
%arrayidx3 = getelementptr inbounds i32, ptr %p, i32 4
81+
store i32 %v, ptr %arrayidx3
82+
ret i32 %v
83+
}

0 commit comments

Comments
 (0)