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Implement reviewer suggestions
1 parent bb8a8d7 commit 49fb4c4

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2 files changed

+17
-20
lines changed

2 files changed

+17
-20
lines changed

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2686,7 +2686,7 @@ SDValue DAGCombiner::visitPTRADD(SDNode *N) {
26862686
return N0;
26872687

26882688
// fold (ptradd 0, x) -> x
2689-
if (isNullConstant(N0) && PtrVT == IntVT)
2689+
if (PtrVT == IntVT && isNullConstant(N0))
26902690
return N1;
26912691

26922692
if (N0.getOpcode() != ISD::PTRADD ||
@@ -2704,10 +2704,9 @@ SDValue DAGCombiner::visitPTRADD(SDNode *N) {
27042704
// * y is a constant and (ptradd x, y) has one use; or
27052705
// * y and z are both constants.
27062706
if ((YIsConstant && N0OneUse) || (YIsConstant && ZIsConstant)) {
2707-
SDNodeFlags Flags;
27082707
// If both additions in the original were NUW, the new ones are as well.
2709-
if (N->getFlags().hasNoUnsignedWrap() && N0->getFlags().hasNoUnsignedWrap())
2710-
Flags |= SDNodeFlags::NoUnsignedWrap;
2708+
SDNodeFlags Flags =
2709+
(N->getFlags() & N0->getFlags()) & SDNodeFlags::NoUnsignedWrap;
27112710
SDValue Add = DAG.getNode(ISD::ADD, DL, IntVT, {Y, Z}, Flags);
27122711
AddToWorklist(Add.getNode());
27132712
return DAG.getMemBasePlusOffset(X, Add, DL, Flags);

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

Lines changed: 14 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -15108,22 +15108,20 @@ SDValue SITargetLowering::performPtrAddCombine(SDNode *N,
1510815108
SDValue X = N0;
1510915109
SDValue Y = N1.getOperand(0);
1511015110
SDValue Z = N1.getOperand(1);
15111-
bool N1OneUse = N1.hasOneUse();
15112-
bool YIsConstant = DAG.isConstantIntBuildVectorOrConstantInt(Y);
15113-
bool ZIsConstant = DAG.isConstantIntBuildVectorOrConstantInt(Z);
15114-
if ((ZIsConstant != YIsConstant) && N1OneUse) {
15115-
SDNodeFlags Flags;
15116-
// If both additions in the original were NUW, the new ones are as well.
15117-
if (N->getFlags().hasNoUnsignedWrap() &&
15118-
N1->getFlags().hasNoUnsignedWrap())
15119-
Flags |= SDNodeFlags::NoUnsignedWrap;
15120-
15121-
if (YIsConstant)
15122-
std::swap(Y, Z);
15123-
15124-
SDValue Inner = DAG.getMemBasePlusOffset(X, Y, DL, Flags);
15125-
DCI.AddToWorklist(Inner.getNode());
15126-
return DAG.getMemBasePlusOffset(Inner, Z, DL, Flags);
15111+
if (N1.hasOneUse()) {
15112+
bool YIsConstant = DAG.isConstantIntBuildVectorOrConstantInt(Y);
15113+
bool ZIsConstant = DAG.isConstantIntBuildVectorOrConstantInt(Z);
15114+
if (ZIsConstant != YIsConstant) {
15115+
// If both additions in the original were NUW, the new ones are as well.
15116+
SDNodeFlags Flags =
15117+
(N->getFlags() & N1->getFlags()) & SDNodeFlags::NoUnsignedWrap;
15118+
if (YIsConstant)
15119+
std::swap(Y, Z);
15120+
15121+
SDValue Inner = DAG.getMemBasePlusOffset(X, Y, DL, Flags);
15122+
DCI.AddToWorklist(Inner.getNode());
15123+
return DAG.getMemBasePlusOffset(Inner, Z, DL, Flags);
15124+
}
1512715125
}
1512815126
}
1512915127

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