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[PowerPC] Exploit Prefixed Load/Stores using the refactored Load/Store Implementation
This patch exploits the prefixed load and store instructions utilizing the refactored load/store implementation introduced in D93370. Prefixed load and store instructions are emitted whenever we are loading or storing a value with an offset that fits into a 34-bit signed immediate. Patterns for the prefixed load and stores are added in this patch, as well as the implementation that detects when we are loading and storing a value with an offset that fits in 34-bits. Differential Revision: https://reviews.llvm.org/D96075
1 parent a1ae56d commit 5041a48

26 files changed

+1127
-1122
lines changed

‎llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -270,6 +270,13 @@ namespace {
270270
None) == PPC::AM_PCRel;
271271
}
272272

273+
/// SelectPDForm - Returns true if address N can be represented by Prefixed
274+
/// DForm addressing mode (a base register, plus a signed 34-bit immediate.
275+
bool SelectPDForm(SDNode *Parent, SDValue N, SDValue &Disp, SDValue &Base) {
276+
return PPCLowering->SelectOptimalAddrMode(Parent, N, Disp, Base, *CurDAG,
277+
None) == PPC::AM_PrefixDForm;
278+
}
279+
273280
/// SelectXForm - Returns true if address N can be represented by the
274281
/// addressing mode of XForm instructions (an indexed [r+r] operation).
275282
bool SelectXForm(SDNode *Parent, SDValue N, SDValue &Disp, SDValue &Base) {

‎llvm/lib/Target/PowerPC/PPCISelLowering.cpp

Lines changed: 45 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1518,10 +1518,9 @@ void PPCTargetLowering::initializeAddrModeMap() {
15181518
PPC::MOF_RPlusSImm16Mult16 | PPC::MOF_Vector | PPC::MOF_SubtargetP9,
15191519
PPC::MOF_NotAddNorCst | PPC::MOF_Vector | PPC::MOF_SubtargetP9,
15201520
PPC::MOF_AddrIsSImm32 | PPC::MOF_Vector | PPC::MOF_SubtargetP9,
1521-
PPC::MOF_RPlusSImm16Mult16 | PPC::MOF_Vector256 | PPC::MOF_SubtargetP10,
1522-
PPC::MOF_NotAddNorCst | PPC::MOF_Vector256 | PPC::MOF_SubtargetP10,
1523-
PPC::MOF_AddrIsSImm32 | PPC::MOF_Vector256 | PPC::MOF_SubtargetP10,
15241521
};
1522+
AddrModesMap[PPC::AM_PrefixDForm] = {PPC::MOF_RPlusSImm34 |
1523+
PPC::MOF_SubtargetP10};
15251524
// TODO: Add mapping for quadword load/store.
15261525
}
15271526

@@ -17267,6 +17266,9 @@ PPC::AddrMode PPCTargetLowering::getAddrModeForFlags(unsigned Flags) const {
1726717266
for (auto FlagSet : AddrModesMap.at(PPC::AM_DQForm))
1726817267
if ((Flags & FlagSet) == FlagSet)
1726917268
return PPC::AM_DQForm;
17269+
for (auto FlagSet : AddrModesMap.at(PPC::AM_PrefixDForm))
17270+
if ((Flags & FlagSet) == FlagSet)
17271+
return PPC::AM_PrefixDForm;
1727017272
// If no other forms are selected, return an X-Form as it is the most
1727117273
// general addressing mode.
1727217274
return PPC::AM_XForm;
@@ -17386,6 +17388,22 @@ unsigned PPCTargetLowering::computeMOFlags(const SDNode *Parent, SDValue N,
1738617388
if ((FlagSet & PPC::MOF_SubtargetP10) && isPCRelNode(N))
1738717389
return FlagSet;
1738817390

17391+
// If the node is the paired load/store intrinsics, compute flags for
17392+
// address computation and return early.
17393+
unsigned ParentOp = Parent->getOpcode();
17394+
if (Subtarget.isISA3_1() && ((ParentOp == ISD::INTRINSIC_W_CHAIN) ||
17395+
(ParentOp == ISD::INTRINSIC_VOID))) {
17396+
unsigned ID = cast<ConstantSDNode>(Parent->getOperand(1))->getZExtValue();
17397+
assert(
17398+
((ID == Intrinsic::ppc_vsx_lxvp) || (ID == Intrinsic::ppc_vsx_stxvp)) &&
17399+
"Only the paired load and store (lxvp/stxvp) intrinsics are valid.");
17400+
SDValue IntrinOp = (ID == Intrinsic::ppc_vsx_lxvp) ? Parent->getOperand(2)
17401+
: Parent->getOperand(3);
17402+
computeFlagsForAddressComputation(IntrinOp, FlagSet, DAG);
17403+
FlagSet |= PPC::MOF_Vector;
17404+
return FlagSet;
17405+
}
17406+
1738917407
// Mark this as something we don't want to handle here if it is atomic
1739017408
// or pre-increment instruction.
1739117409
if (const LSBaseSDNode *LSB = dyn_cast<LSBaseSDNode>(Parent))
@@ -17410,9 +17428,12 @@ unsigned PPCTargetLowering::computeMOFlags(const SDNode *Parent, SDValue N,
1741017428
} else if (MemVT.isVector() && !MemVT.isFloatingPoint()) { // Integer vectors.
1741117429
if (Size == 128)
1741217430
FlagSet |= PPC::MOF_Vector;
17413-
else if (Size == 256)
17414-
FlagSet |= PPC::MOF_Vector256;
17415-
else
17431+
else if (Size == 256) {
17432+
assert(Subtarget.pairedVectorMemops() &&
17433+
"256-bit vectors are only available when paired vector memops is "
17434+
"enabled!");
17435+
FlagSet |= PPC::MOF_Vector;
17436+
} else
1741617437
llvm_unreachable("Not expecting illegal vectors!");
1741717438
} else { // Floating point type: can be scalar, f128 or vector types.
1741817439
if (Size == 32 || Size == 64)
@@ -17609,6 +17630,24 @@ PPC::AddrMode PPCTargetLowering::SelectOptimalAddrMode(const SDNode *Parent,
1760917630
Base = N;
1761017631
break;
1761117632
}
17633+
case PPC::AM_PrefixDForm: {
17634+
int64_t Imm34 = 0;
17635+
unsigned Opcode = N.getOpcode();
17636+
if (((Opcode == ISD::ADD) || (Opcode == ISD::OR)) &&
17637+
(isIntS34Immediate(N.getOperand(1), Imm34))) {
17638+
// N is an Add/OR Node, and it's operand is a 34-bit signed immediate.
17639+
Disp = DAG.getTargetConstant(Imm34, DL, N.getValueType());
17640+
if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0)))
17641+
Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
17642+
else
17643+
Base = N.getOperand(0);
17644+
} else if (isIntS34Immediate(N, Imm34)) {
17645+
// The address is a 34-bit signed immediate.
17646+
Disp = DAG.getTargetConstant(Imm34, DL, N.getValueType());
17647+
Base = DAG.getRegister(PPC::ZERO8, N.getValueType());
17648+
}
17649+
break;
17650+
}
1761217651
case PPC::AM_PCRel: {
1761317652
// When selecting PC-Relative instructions, "Base" is not utilized as
1761417653
// we select the address as [PC+imm].

‎llvm/lib/Target/PowerPC/PPCISelLowering.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -717,6 +717,7 @@ namespace llvm {
717717
AM_DForm,
718718
AM_DSForm,
719719
AM_DQForm,
720+
AM_PrefixDForm,
720721
AM_XForm,
721722
AM_PCRel
722723
};

‎llvm/lib/Target/PowerPC/PPCInstrInfo.td

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1159,6 +1159,7 @@ def DQForm : ComplexPattern<iPTR, 2, "SelectDQForm", [], [SDNPWantParent]>;
11591159
def XForm : ComplexPattern<iPTR, 2, "SelectXForm", [], [SDNPWantParent]>;
11601160
def ForceXForm : ComplexPattern<iPTR, 2, "SelectForceXForm", [], [SDNPWantParent]>;
11611161
def PCRelForm : ComplexPattern<iPTR, 2, "SelectPCRelForm", [], [SDNPWantParent]>;
1162+
def PDForm : ComplexPattern<iPTR, 2, "SelectPDForm", [], [SDNPWantParent]>;
11621163

11631164
//===----------------------------------------------------------------------===//
11641165
// PowerPC Instruction Predicate Definitions.

‎llvm/lib/Target/PowerPC/PPCInstrPrefix.td

Lines changed: 103 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1666,18 +1666,18 @@ let mayLoad = 0, mayStore = 1, Predicates = [PairedVectorMemops, PrefixInstrs] i
16661666

16671667
let Predicates = [PairedVectorMemops] in {
16681668
// Intrinsics for Paired Vector Loads.
1669-
def : Pat<(v256i1 (int_ppc_vsx_lxvp iaddrX16:$src)), (LXVP memrix16:$src)>;
1670-
def : Pat<(v256i1 (int_ppc_vsx_lxvp xaddrX16:$src)), (LXVPX xaddrX16:$src)>;
1669+
def : Pat<(v256i1 (int_ppc_vsx_lxvp DQForm:$src)), (LXVP memrix16:$src)>;
1670+
def : Pat<(v256i1 (int_ppc_vsx_lxvp XForm:$src)), (LXVPX XForm:$src)>;
16711671
let Predicates = [PairedVectorMemops, PrefixInstrs] in {
1672-
def : Pat<(v256i1 (int_ppc_vsx_lxvp iaddrX34:$src)), (PLXVP memri34:$src)>;
1672+
def : Pat<(v256i1 (int_ppc_vsx_lxvp PDForm:$src)), (PLXVP memri34:$src)>;
16731673
}
16741674
// Intrinsics for Paired Vector Stores.
1675-
def : Pat<(int_ppc_vsx_stxvp v256i1:$XSp, iaddrX16:$dst),
1675+
def : Pat<(int_ppc_vsx_stxvp v256i1:$XSp, DQForm:$dst),
16761676
(STXVP $XSp, memrix16:$dst)>;
1677-
def : Pat<(int_ppc_vsx_stxvp v256i1:$XSp, xaddrX16:$dst),
1678-
(STXVPX $XSp, xaddrX16:$dst)>;
1677+
def : Pat<(int_ppc_vsx_stxvp v256i1:$XSp, XForm:$dst),
1678+
(STXVPX $XSp, XForm:$dst)>;
16791679
let Predicates = [PairedVectorMemops, PrefixInstrs] in {
1680-
def : Pat<(int_ppc_vsx_stxvp v256i1:$XSp, iaddrX34:$dst),
1680+
def : Pat<(int_ppc_vsx_stxvp v256i1:$XSp, PDForm:$dst),
16811681
(PSTXVP $XSp, memri34:$dst)>;
16821682
}
16831683
}
@@ -2671,6 +2671,45 @@ def : Pat<(f64 nzFPImmAsi64:$A),
26712671
// nand(A, nand(B, C))
26722672
def : xxevalPattern<(or (vnot v4i32:$vA), (and v4i32:$vB, v4i32:$vC)),
26732673
!sub(255, 14)>;
2674+
2675+
// Anonymous patterns to select prefixed VSX loads and stores.
2676+
// Load / Store f128
2677+
def : Pat<(f128 (load PDForm:$src)),
2678+
(COPY_TO_REGCLASS (PLXV memri34:$src), VRRC)>;
2679+
def : Pat<(store f128:$XS, PDForm:$dst),
2680+
(PSTXV (COPY_TO_REGCLASS $XS, VSRC), memri34:$dst)>;
2681+
2682+
// Load / Store v4i32
2683+
def : Pat<(v4i32 (load PDForm:$src)), (PLXV memri34:$src)>;
2684+
def : Pat<(store v4i32:$XS, PDForm:$dst), (PSTXV $XS, memri34:$dst)>;
2685+
2686+
// Load / Store v2i64
2687+
def : Pat<(v2i64 (load PDForm:$src)), (PLXV memri34:$src)>;
2688+
def : Pat<(store v2i64:$XS, PDForm:$dst), (PSTXV $XS, memri34:$dst)>;
2689+
2690+
// Load / Store v4f32
2691+
def : Pat<(v4f32 (load PDForm:$src)), (PLXV memri34:$src)>;
2692+
def : Pat<(store v4f32:$XS, PDForm:$dst), (PSTXV $XS, memri34:$dst)>;
2693+
2694+
// Load / Store v2f64
2695+
def : Pat<(v2f64 (load PDForm:$src)), (PLXV memri34:$src)>;
2696+
def : Pat<(store v2f64:$XS, PDForm:$dst), (PSTXV $XS, memri34:$dst)>;
2697+
2698+
// Cases For PPCstore_scal_int_from_vsr
2699+
def : Pat<(PPCstore_scal_int_from_vsr
2700+
(f64 (PPCcv_fp_to_uint_in_vsr f64:$src)), PDForm:$dst, 8),
2701+
(PSTXSD (XSCVDPUXDS f64:$src), PDForm:$dst)>;
2702+
def : Pat<(PPCstore_scal_int_from_vsr
2703+
(f64 (PPCcv_fp_to_sint_in_vsr f64:$src)), PDForm:$dst, 8),
2704+
(PSTXSD (XSCVDPSXDS f64:$src), PDForm:$dst)>;
2705+
def : Pat<(PPCstore_scal_int_from_vsr
2706+
(f64 (PPCcv_fp_to_uint_in_vsr f128:$src)), PDForm:$dst, 8),
2707+
(PSTXSD (COPY_TO_REGCLASS (XSCVQPUDZ f128:$src), VFRC),
2708+
PDForm:$dst)>;
2709+
def : Pat<(PPCstore_scal_int_from_vsr
2710+
(f64 (PPCcv_fp_to_sint_in_vsr f128:$src)), PDForm:$dst, 8),
2711+
(PSTXSD (COPY_TO_REGCLASS (XSCVQPSDZ f128:$src), VFRC),
2712+
PDForm:$dst)>;
26742713
}
26752714

26762715
let Predicates = [PrefixInstrs] in {
@@ -2694,6 +2733,63 @@ let Predicates = [PrefixInstrs] in {
26942733
(XXBLENDVW $A, $B, $C)>;
26952734
def : Pat<(int_ppc_vsx_xxblendvd v2i64:$A, v2i64:$B, v2i64:$C),
26962735
(XXBLENDVD $A, $B, $C)>;
2736+
2737+
// Anonymous patterns to select prefixed loads and stores.
2738+
// Load i32
2739+
def : Pat<(i32 (extloadi1 PDForm:$src)), (PLBZ memri34:$src)>;
2740+
def : Pat<(i32 (zextloadi1 PDForm:$src)), (PLBZ memri34:$src)>;
2741+
def : Pat<(i32 (extloadi8 PDForm:$src)), (PLBZ memri34:$src)>;
2742+
def : Pat<(i32 (zextloadi8 PDForm:$src)), (PLBZ memri34:$src)>;
2743+
def : Pat<(i32 (extloadi16 PDForm:$src)), (PLHZ memri34:$src)>;
2744+
def : Pat<(i32 (zextloadi16 PDForm:$src)), (PLHZ memri34:$src)>;
2745+
def : Pat<(i32 (sextloadi16 PDForm:$src)), (PLHA memri34:$src)>;
2746+
def : Pat<(i32 (load PDForm:$src)), (PLWZ memri34:$src)>;
2747+
2748+
// Store i32
2749+
def : Pat<(truncstorei8 i32:$rS, PDForm:$dst), (PSTB gprc:$rS, memri34:$dst)>;
2750+
def : Pat<(truncstorei16 i32:$rS, PDForm:$dst), (PSTH gprc:$rS, memri34:$dst)>;
2751+
def : Pat<(store i32:$rS, PDForm:$dst), (PSTW gprc:$rS, memri34:$dst)>;
2752+
2753+
// Load i64
2754+
def : Pat<(i64 (extloadi1 PDForm:$src)), (PLBZ8 memri34:$src)>;
2755+
def : Pat<(i64 (zextloadi1 PDForm:$src)), (PLBZ8 memri34:$src)>;
2756+
def : Pat<(i64 (extloadi8 PDForm:$src)), (PLBZ8 memri34:$src)>;
2757+
def : Pat<(i64 (zextloadi8 PDForm:$src)), (PLBZ8 memri34:$src)>;
2758+
def : Pat<(i64 (extloadi16 PDForm:$src)), (PLHZ8 memri34:$src)>;
2759+
def : Pat<(i64 (zextloadi16 PDForm:$src)), (PLHZ8 memri34:$src)>;
2760+
def : Pat<(i64 (sextloadi16 PDForm:$src)), (PLHA8 memri34:$src)>;
2761+
def : Pat<(i64 (extloadi32 PDForm:$src)), (PLWZ8 memri34:$src)>;
2762+
def : Pat<(i64 (zextloadi32 PDForm:$src)), (PLWZ8 memri34:$src)>;
2763+
def : Pat<(i64 (sextloadi32 PDForm:$src)), (PLWA8 memri34:$src)>;
2764+
def : Pat<(i64 (load PDForm:$src)), (PLD memri34:$src)>;
2765+
2766+
// Store i64
2767+
def : Pat<(truncstorei8 i64:$rS, PDForm:$dst), (PSTB8 g8rc:$rS, memri34:$dst)>;
2768+
def : Pat<(truncstorei16 i64:$rS, PDForm:$dst), (PSTH8 g8rc:$rS, memri34:$dst)>;
2769+
def : Pat<(truncstorei32 i64:$rS, PDForm:$dst), (PSTW8 g8rc:$rS, memri34:$dst)>;
2770+
def : Pat<(store i64:$rS, PDForm:$dst), (PSTD g8rc:$rS, memri34:$dst)>;
2771+
2772+
// Load / Store f32
2773+
def : Pat<(f32 (load PDForm:$src)), (PLFS memri34:$src)>;
2774+
def : Pat<(store f32:$FRS, PDForm:$dst), (PSTFS $FRS, memri34:$dst)>;
2775+
2776+
// Load / Store f64
2777+
def : Pat<(f64 (extloadf32 PDForm:$src)),
2778+
(COPY_TO_REGCLASS (PLFS memri34:$src), VSFRC)>;
2779+
def : Pat<(f64 (load PDForm:$src)), (PLFD memri34:$src)>;
2780+
def : Pat<(store f64:$FRS, PDForm:$dst), (PSTFD $FRS, memri34:$dst)>;
2781+
2782+
// Atomic Load
2783+
def : Pat<(atomic_load_8 PDForm:$src), (PLBZ memri34:$src)>;
2784+
def : Pat<(atomic_load_16 PDForm:$src), (PLHZ memri34:$src)>;
2785+
def : Pat<(atomic_load_32 PDForm:$src), (PLWZ memri34:$src)>;
2786+
def : Pat<(atomic_load_64 PDForm:$src), (PLD memri34:$src)>;
2787+
2788+
// Atomic Store
2789+
def : Pat<(atomic_store_8 PDForm:$dst, i32:$RS), (PSTB $RS, memri34:$dst)>;
2790+
def : Pat<(atomic_store_16 PDForm:$dst, i32:$RS), (PSTH $RS, memri34:$dst)>;
2791+
def : Pat<(atomic_store_32 PDForm:$dst, i32:$RS), (PSTW $RS, memri34:$dst)>;
2792+
def : Pat<(atomic_store_64 PDForm:$dst, i64:$RS), (PSTD $RS, memri34:$dst)>;
26972793
}
26982794

26992795
def InsertEltShift {

‎llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp

Lines changed: 19 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -135,6 +135,23 @@ PPCRegisterInfo::PPCRegisterInfo(const PPCTargetMachine &TM)
135135
ImmToIdxMap[PPC::SPELWZ] = PPC::SPELWZX;
136136

137137
// Power10
138+
ImmToIdxMap[PPC::PLBZ] = PPC::LBZX; ImmToIdxMap[PPC::PLBZ8] = PPC::LBZX8;
139+
ImmToIdxMap[PPC::PLHZ] = PPC::LHZX; ImmToIdxMap[PPC::PLHZ8] = PPC::LHZX8;
140+
ImmToIdxMap[PPC::PLHA] = PPC::LHAX; ImmToIdxMap[PPC::PLHA8] = PPC::LHAX8;
141+
ImmToIdxMap[PPC::PLWZ] = PPC::LWZX; ImmToIdxMap[PPC::PLWZ8] = PPC::LWZX8;
142+
ImmToIdxMap[PPC::PLWA] = PPC::LWAX; ImmToIdxMap[PPC::PLWA8] = PPC::LWAX;
143+
ImmToIdxMap[PPC::PLD] = PPC::LDX; ImmToIdxMap[PPC::PSTD] = PPC::STDX;
144+
145+
ImmToIdxMap[PPC::PSTB] = PPC::STBX; ImmToIdxMap[PPC::PSTB8] = PPC::STBX8;
146+
ImmToIdxMap[PPC::PSTH] = PPC::STHX; ImmToIdxMap[PPC::PSTH8] = PPC::STHX8;
147+
ImmToIdxMap[PPC::PSTW] = PPC::STWX; ImmToIdxMap[PPC::PSTW8] = PPC::STWX8;
148+
149+
ImmToIdxMap[PPC::PLFS] = PPC::LFSX; ImmToIdxMap[PPC::PSTFS] = PPC::STFSX;
150+
ImmToIdxMap[PPC::PLFD] = PPC::LFDX; ImmToIdxMap[PPC::PSTFD] = PPC::STFDX;
151+
ImmToIdxMap[PPC::PLXSSP] = PPC::LXSSPX; ImmToIdxMap[PPC::PSTXSSP] = PPC::STXSSPX;
152+
ImmToIdxMap[PPC::PLXSD] = PPC::LXSDX; ImmToIdxMap[PPC::PSTXSD] = PPC::STXSDX;
153+
ImmToIdxMap[PPC::PLXV] = PPC::LXVX; ImmToIdxMap[PPC::PSTXV] = PPC::STXVX;
154+
138155
ImmToIdxMap[PPC::LXVP] = PPC::LXVPX;
139156
ImmToIdxMap[PPC::STXVP] = PPC::STXVPX;
140157
ImmToIdxMap[PPC::PLXVP] = PPC::LXVPX;
@@ -1347,7 +1364,7 @@ PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
13471364
MachineFunction &MF = *MBB.getParent();
13481365
const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
13491366
// Get the instruction info.
1350-
const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1367+
const PPCInstrInfo &TII = *Subtarget.getInstrInfo();
13511368
// Get the frame info.
13521369
MachineFrameInfo &MFI = MF.getFrameInfo();
13531370
DebugLoc dl = MI.getDebugLoc();
@@ -1459,7 +1476,7 @@ PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
14591476
bool OffsetFitsMnemonic = (OpC == PPC::EVSTDD || OpC == PPC::EVLDD) ?
14601477
isUInt<8>(Offset) :
14611478
isInt<16>(Offset);
1462-
if (OpC == PPC::PLXVP || OpC == PPC::PSTXVP)
1479+
if (TII.isPrefixed(MI.getOpcode()))
14631480
OffsetFitsMnemonic = isInt<34>(Offset);
14641481
if (!noImmForm && ((OffsetFitsMnemonic &&
14651482
((Offset % offsetMinAlign(MI)) == 0)) ||

‎llvm/test/CodeGen/PowerPC/aix-vec_insert_elt.ll

Lines changed: 7 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -667,7 +667,7 @@ define <2 x double> @testDouble2(<2 x double> %a, i8* %b, i32 zeroext %idx1, i32
667667
; CHECK-32-P10-NEXT: rlwinm 5, 5, 3, 28, 28
668668
; CHECK-32-P10-NEXT: stfdx 0, 6, 4
669669
; CHECK-32-P10-NEXT: lxv 0, -32(1)
670-
; CHECK-32-P10-NEXT: lfd 1, 1(3)
670+
; CHECK-32-P10-NEXT: plfd 1, 1(3), 0
671671
; CHECK-32-P10-NEXT: addi 3, 1, -16
672672
; CHECK-32-P10-NEXT: stxv 0, -16(1)
673673
; CHECK-32-P10-NEXT: stfdx 1, 3, 5
@@ -737,12 +737,11 @@ define <2 x double> @testDouble3(<2 x double> %a, i8* %b, i32 zeroext %idx1, i32
737737
;
738738
; CHECK-32-P10-LABEL: testDouble3:
739739
; CHECK-32-P10: # %bb.0: # %entry
740-
; CHECK-32-P10-NEXT: lis 6, 1
741-
; CHECK-32-P10-NEXT: rlwinm 4, 4, 3, 28, 28
742-
; CHECK-32-P10-NEXT: rlwinm 5, 5, 3, 28, 28
743-
; CHECK-32-P10-NEXT: lfdx 0, 3, 6
744-
; CHECK-32-P10-NEXT: addi 6, 1, -32
740+
; CHECK-32-P10-NEXT: plfd 0, 65536(3), 0
741+
; CHECK-32-P10-DAG: addi 6, 1, -32
742+
; CHECK-32-P10-DAG: rlwinm 4, 4, 3, 28, 28
745743
; CHECK-32-P10-NEXT: stxv 34, -32(1)
744+
; CHECK-32-P10-NEXT: rlwinm 5, 5, 3, 28, 28
746745
; CHECK-32-P10-NEXT: stfdx 0, 6, 4
747746
; CHECK-32-P10-NEXT: lxv 0, -32(1)
748747
; CHECK-32-P10-NEXT: lfd 1, 0(3)
@@ -874,15 +873,13 @@ define <2 x double> @testDoubleImm4(<2 x double> %a, i32* %b) {
874873
;
875874
; CHECK-64-P10-LABEL: testDoubleImm4:
876875
; CHECK-64-P10: # %bb.0: # %entry
877-
; CHECK-64-P10-NEXT: lis 4, 4
878-
; CHECK-64-P10-NEXT: lfdx 0, 3, 4
876+
; CHECK-64-P10-NEXT: plfd 0, 262144(3), 0
879877
; CHECK-64-P10-NEXT: xxpermdi 34, 0, 34, 1
880878
; CHECK-64-P10-NEXT: blr
881879
;
882880
; CHECK-32-P10-LABEL: testDoubleImm4:
883881
; CHECK-32-P10: # %bb.0: # %entry
884-
; CHECK-32-P10-NEXT: lis 4, 4
885-
; CHECK-32-P10-NEXT: lfdx 0, 3, 4
882+
; CHECK-32-P10-NEXT: plfd 0, 262144(3), 0
886883
; CHECK-32-P10-NEXT: xxpermdi 34, 0, 34, 1
887884
; CHECK-32-P10-NEXT: blr
888885
entry:

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