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Address reviewer comments.
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‎mlir/lib/Target/LLVMIR/Dialect/XeVM/XeVMToLLVMIRTranslation.cpp

Lines changed: 2 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -63,11 +63,6 @@ class XeVMDialectLLVMIRTranslationInterface
6363
}
6464

6565
private:
66-
template <typename IntTy>
67-
static llvm::Metadata *getConstantIntMD(llvm::Type *type, IntTy val) {
68-
return llvm::ConstantAsMetadata::get(llvm::ConstantInt::get(type, val));
69-
}
70-
7166
static LogicalResult handleDecorationCacheControl(llvm::Instruction *inst,
7267
ArrayRef<Attribute> attrs) {
7368
SmallVector<llvm::Metadata *> decorations;
@@ -94,14 +89,14 @@ class XeVMDialectLLVMIRTranslationInterface
9489
};
9590
} // namespace
9691

97-
void ::mlir::registerXeVMDialectTranslation(::mlir::DialectRegistry &registry) {
92+
void mlir::registerXeVMDialectTranslation(::mlir::DialectRegistry &registry) {
9893
registry.insert<xevm::XeVMDialect>();
9994
registry.addExtension(+[](MLIRContext *ctx, xevm::XeVMDialect *dialect) {
10095
dialect->addInterfaces<XeVMDialectLLVMIRTranslationInterface>();
10196
});
10297
}
10398

104-
void ::mlir::registerXeVMDialectTranslation(::mlir::MLIRContext &context) {
99+
void mlir::registerXeVMDialectTranslation(::mlir::MLIRContext &context) {
105100
DialectRegistry registry;
106101
registerXeVMDialectTranslation(registry);
107102
context.appendDialectRegistry(registry);

‎mlir/test/Target/LLVMIR/xevm.mlir

Lines changed: 1 addition & 81 deletions
Original file line numberDiff line numberDiff line change
@@ -1,93 +1,13 @@
11
// RUN: mlir-translate --split-input-file -mlir-to-llvmir %s | FileCheck %s
22

33
module {
4-
llvm.func spir_funccc @_Z41intel_sub_group_2d_block_read_16b_8r16x1cPU3AS1viiiDv2_iPt(!llvm.ptr<1> {llvm.nonnull, llvm.readonly}, i32, i32, i32, vector<2xi32>, !llvm.ptr {llvm.nonnull, llvm.writeonly}) attributes {no_unwind, will_return}
5-
llvm.func @blockload2d_cache_control(%arg0: !llvm.ptr<1>, %arg1: i32, %arg2: i32, %arg3: i32, %arg4: i32, %arg5: i32) -> vector<8xi16> {
6-
%0 = llvm.mlir.undef : vector<2xi32>
7-
%1 = llvm.mlir.constant(0 : i32) : i32
8-
%2 = llvm.mlir.constant(1 : i32) : i32
9-
%3 = llvm.insertelement %arg4, %0[%1 : i32] : vector<2xi32>
10-
%4 = llvm.insertelement %arg5, %3[%2 : i32] : vector<2xi32>
11-
%5 = llvm.mlir.constant(8 : i32) : i32
12-
%6 = llvm.alloca %5 x i16 : (i32) -> !llvm.ptr
13-
// CHECK-LABEL: call spir_func void @_Z41intel_sub_group_2d_block_read_16b_8r16x1cPU3AS1viiiDv2_iPt
14-
// CHECK-SAME: !spirv.DecorationCacheControlINTEL ![[DECO1:.*]]
15-
llvm.call spir_funccc @_Z41intel_sub_group_2d_block_read_16b_8r16x1cPU3AS1viiiDv2_iPt(%arg0, %arg1, %arg2, %arg3, %4, %6)
16-
{function_type = !llvm.func<void (ptr<1>, i32, i32, i32, vector<2xi32>, ptr)>, linkage = #llvm.linkage<external>, no_unwind,
17-
sym_name = "_Z41intel_sub_group_2d_block_read_16b_8r16x1cPU3AS1viiiDv2_iPt", visibility_ = 0 : i64, will_return,
18-
xevm.DecorationCacheControl = [[6442 : i32, 0 : i32, 1 : i32, 0 : i32], [6442 : i32, 1 : i32, 1 : i32, 0 : i32]]}
19-
: (!llvm.ptr<1> {llvm.nonnull, llvm.readonly}, i32, i32, i32, vector<2xi32>, !llvm.ptr {llvm.nonnull, llvm.writeonly}) -> ()
20-
%7 = llvm.load %6 : !llvm.ptr -> vector<8xi16>
21-
llvm.return %7 : vector<8xi16>
22-
}
23-
}
24-
25-
// CHECK: ![[DECO1]] = !{![[DECO2:.*]], ![[DECO3:.*]]}
26-
// CHECK: ![[DECO2]] = !{i32 6442, i32 0, i32 1, i32 0}
27-
// CHECK: ![[DECO3]] = !{i32 6442, i32 1, i32 1, i32 0}
28-
29-
// -----
30-
module {
31-
llvm.func spir_funccc @_Z42intel_sub_group_2d_block_write_32b_8r16x1cPU3AS1viiiDv2_iPj(!llvm.ptr<1> {llvm.nonnull, llvm.writeonly}, i32, i32, i32, vector<2xi32>, !llvm.ptr {llvm.nonnull, llvm.readonly}) attributes {no_unwind, will_return}
32-
llvm.func @blockstore2d_cache_control(%arg0: !llvm.ptr<1>, %arg1: i32, %arg2: i32, %arg3: i32, %arg4: i32, %arg5: i32, %arg6: vector<8xi32>) {
33-
%0 = llvm.mlir.undef : vector<2xi32>
34-
%1 = llvm.mlir.constant(0 : i32) : i32
35-
%2 = llvm.mlir.constant(1 : i32) : i32
36-
%3 = llvm.insertelement %arg4, %0[%1 : i32] : vector<2xi32>
37-
%4 = llvm.insertelement %arg5, %3[%2 : i32] : vector<2xi32>
38-
%5 = llvm.mlir.constant(8 : i32) : i32
39-
%6 = llvm.alloca %5 x i32 : (i32) -> !llvm.ptr
40-
llvm.store %arg6, %6 : vector<8xi32>, !llvm.ptr
41-
// CHECK-LABEL: call spir_func void @_Z42intel_sub_group_2d_block_write_32b_8r16x1cPU3AS1viiiDv2_iPj
42-
// CHECK-SAME: !spirv.DecorationCacheControlINTEL ![[DECO1:.*]]
43-
llvm.call spir_funccc @_Z42intel_sub_group_2d_block_write_32b_8r16x1cPU3AS1viiiDv2_iPj(%arg0, %arg1, %arg2, %arg3, %4, %6)
44-
{function_type = !llvm.func<void (ptr<1>, i32, i32, i32, vector<2xi32>, ptr)>, linkage = #llvm.linkage<external>, no_unwind,
45-
sym_name = "_Z42intel_sub_group_2d_block_write_32b_8r16x1cPU3AS1viiiDv2_iPj", visibility_ = 0 : i64, will_return,
46-
xevm.DecorationCacheControl = [[6443 : i32, 0 : i32, 2 : i32, 0 : i32], [6443 : i32, 1 : i32, 2 : i32, 0 : i32]]}
47-
: (!llvm.ptr<1> {llvm.nonnull, llvm.writeonly}, i32, i32, i32, vector<2xi32>, !llvm.ptr {llvm.nonnull, llvm.readonly}) -> ()
48-
llvm.return
49-
}
50-
}
51-
52-
// CHECK: ![[DECO1]] = !{![[DECO2:.*]], ![[DECO3:.*]]}
53-
// CHECK: ![[DECO2]] = !{i32 6443, i32 0, i32 2, i32 0}
54-
// CHECK: ![[DECO3]] = !{i32 6443, i32 1, i32 2, i32 0}
55-
56-
// -----
57-
module {
58-
llvm.func spir_funccc @_Z44intel_sub_group_2d_block_prefetch_8b_8r32x1cPU3AS1viiiDv2_i(!llvm.ptr<1> {llvm.nonnull}, i32, i32, i32, vector<2xi32>) attributes {memory_effects = #llvm.memory_effects<other = none, argMem = read, inaccessibleMem = none>, no_unwind}
59-
llvm.func @blockprefetch2d(%arg0: !llvm.ptr<1>, %arg1: i32, %arg2: i32, %arg3: i32, %arg4: i32, %arg5: i32) {
60-
%0 = llvm.mlir.undef : vector<2xi32>
61-
%1 = llvm.mlir.constant(0 : i32) : i32
62-
%2 = llvm.mlir.constant(1 : i32) : i32
63-
%3 = llvm.insertelement %arg4, %0[%1 : i32] : vector<2xi32>
64-
%4 = llvm.insertelement %arg5, %3[%2 : i32] : vector<2xi32>
65-
// CHECK-LABEL: call spir_func void @_Z44intel_sub_group_2d_block_prefetch_8b_8r32x1cPU3AS1viiiDv2_i
66-
// CHECK-SAME: !spirv.DecorationCacheControlINTEL ![[DECO1:.*]]
67-
llvm.call spir_funccc @_Z44intel_sub_group_2d_block_prefetch_8b_8r32x1cPU3AS1viiiDv2_i(%arg0, %arg1, %arg2, %arg3, %4)
68-
{function_type = !llvm.func<void (ptr<1>, i32, i32, i32, vector<2xi32>)>, linkage = #llvm.linkage<external>,
69-
memory_effects = #llvm.memory_effects<other = none, argMem = read, inaccessibleMem = none>, no_unwind,
70-
sym_name = "_Z44intel_sub_group_2d_block_prefetch_8b_8r32x1cPU3AS1viiiDv2_i", visibility_ = 0 : i64,
71-
xevm.DecorationCacheControl = [[6442 : i32, 0 : i32, 1 : i32, 0 : i32], [6442 : i32, 1 : i32, 1 : i32, 0 : i32]]}
72-
: (!llvm.ptr<1> {llvm.nonnull}, i32, i32, i32, vector<2xi32>) -> ()
73-
llvm.return
74-
}
75-
}
76-
77-
// CHECK: ![[DECO1]] = !{![[DECO2:.*]], ![[DECO3:.*]]}
78-
// CHECK: ![[DECO2]] = !{i32 6442, i32 0, i32 1, i32 0}
79-
// CHECK: ![[DECO3]] = !{i32 6442, i32 1, i32 1, i32 0}
80-
81-
// -----
82-
module {
83-
llvm.func spir_funccc @_Z8prefetchPU3AS1Kcm(!llvm.ptr<1>, i64) attributes {memory_effects = #llvm.memory_effects<other = none, argMem = read, inaccessibleMem = none>, no_unwind}
4+
llvm.func spir_funccc @_Z8prefetchPU3AS1Kcm(!llvm.ptr<1>, i64)
845
llvm.func @prefetch(%arg0: !llvm.ptr<1>) {
856
%0 = llvm.mlir.constant(1 : i64) : i64
867
// CHECK-LABEL: call spir_func void @_Z8prefetchPU3AS1Kcm
878
// CHECK-SAME: !spirv.DecorationCacheControlINTEL ![[DECO1:.*]]
889
llvm.call spir_funccc @_Z8prefetchPU3AS1Kcm(%arg0, %0)
8910
{function_type = !llvm.func<void (ptr<1>, i64)>, linkage = #llvm.linkage<external>,
90-
memory_effects = #llvm.memory_effects<other = none, argMem = read, inaccessibleMem = none>,
9111
no_unwind, sym_name = "_Z8prefetchPU3AS1Kcm", visibility_ = 0 : i64,
9212
xevm.DecorationCacheControl = [[6442 : i32, 0 : i32, 1 : i32, 0 : i32], [6442 : i32, 1 : i32, 1 : i32, 0 : i32]]}
9313
: (!llvm.ptr<1>, i64) -> ()

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