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[AMDGPU] Add scheduling stage to rewrite MFMA from VGPR to AGPR
Change-Id: I47b2a4274a35f3cf0a6d064674d1d29526e4dfd2
1 parent 83dfdd8 commit 758593b

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6 files changed

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6 files changed

+6868
-9
lines changed

llvm/include/llvm/CodeGen/MachineInstrBuilder.h

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@@ -454,6 +454,21 @@ inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
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.setMMRAMetadata(MIMD.getMMRAMetadata());
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}
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/// This version of the builder inserts the newly-built instruction after the
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/// given position in the given MachineBasicBlock, and does NOT take a
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/// destination register.
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inline MachineInstrBuilder BuildMIAfter(MachineBasicBlock &BB,
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MachineBasicBlock::iterator I,
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const MIMetadata &MIMD,
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const MCInstrDesc &MCID) {
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MachineFunction &MF = *BB.getParent();
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MachineInstr *MI = MF.CreateMachineInstr(MCID, MIMD.getDL());
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BB.insertAfter(I, MI);
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return MachineInstrBuilder(MF, MI)
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.setPCSections(MIMD.getPCSections())
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.setMMRAMetadata(MIMD.getMMRAMetadata());
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}
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inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
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MachineBasicBlock::instr_iterator I,
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const MIMetadata &MIMD,

llvm/lib/Target/AMDGPU/GCNRegPressure.h

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@@ -90,6 +90,36 @@ struct GCNRegPressure {
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DynamicVGPRBlockSize));
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}
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unsigned getVGPRSpills(const GCNSubtarget &ST, MachineFunction &MF) {
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if (!ST.hasGFX90AInsts())
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return 0;
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auto MaxVectorRegs = ST.getMaxNumVectorRegs(MF.getFunction());
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unsigned ArchVGPRThreshold = MaxVectorRegs.first;
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unsigned AGPRThreshold = MaxVectorRegs.second;
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unsigned ArchPressure = getArchVGPRNum();
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unsigned AGPRPressure = getAGPRNum();
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unsigned ArchSpill = ArchPressure > ArchVGPRThreshold
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? (ArchPressure - ArchVGPRThreshold)
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: 0;
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unsigned AGPRSpill =
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AGPRPressure > AGPRThreshold ? (AGPRPressure - AGPRThreshold) : 0;
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unsigned UnifiedSpill = 0;
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if (ST.hasGFX90AInsts()) {
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unsigned CombinedThreshold = ST.getMaxNumVGPRs(MF);
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unsigned UnifiedPressure = getVGPRNum(true);
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UnifiedSpill = UnifiedPressure > CombinedThreshold
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? (UnifiedPressure - CombinedThreshold)
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: 0;
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}
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return std::max(UnifiedSpill, (ArchSpill + AGPRSpill));
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}
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void inc(unsigned Reg,
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LaneBitmask PrevMask,
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LaneBitmask NewMask,

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