|
1 |
| -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 |
| 1 | +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 5 |
2 | 2 | ; RUN: opt %s -passes=loop-vectorize -S | FileCheck %s
|
3 | 3 |
|
4 | 4 | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
|
5 | 5 | target triple = "x86_64-unknown-linux-gnu"
|
6 | 6 |
|
7 |
| -define i32 @bitcast-cse(i16 %0) { |
| 7 | +define i32 @bitcast-cse(i16 %val, half %fval, ptr %p, i64 %n) { |
8 | 8 | ; CHECK-LABEL: define i32 @bitcast-cse(
|
9 |
| -; CHECK-SAME: i16 [[TMP0:%.*]]) { |
| 9 | +; CHECK-SAME: i16 [[VAL:%.*]], half [[FVAL:%.*]], ptr [[P:%.*]], i64 [[N:%.*]]) { |
10 | 10 | ; CHECK-NEXT: [[ENTRY:.*]]:
|
11 |
| -; CHECK-NEXT: br i1 false, label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] |
| 11 | +; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 60 |
| 12 | +; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]] |
| 13 | +; CHECK: [[VECTOR_SCEVCHECK]]: |
| 14 | +; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[N]], -1 |
| 15 | +; CHECK-NEXT: [[MUL:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 4, i64 [[TMP8]]) |
| 16 | +; CHECK-NEXT: [[MUL_RESULT:%.*]] = extractvalue { i64, i1 } [[MUL]], 0 |
| 17 | +; CHECK-NEXT: [[MUL_OVERFLOW:%.*]] = extractvalue { i64, i1 } [[MUL]], 1 |
| 18 | +; CHECK-NEXT: [[TMP9:%.*]] = sub i64 0, [[MUL_RESULT]] |
| 19 | +; CHECK-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr [[P]], i64 [[MUL_RESULT]] |
| 20 | +; CHECK-NEXT: [[TMP11:%.*]] = icmp ult ptr [[TMP10]], [[P]] |
| 21 | +; CHECK-NEXT: [[TMP12:%.*]] = or i1 [[TMP11]], [[MUL_OVERFLOW]] |
| 22 | +; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[P]], i64 2 |
| 23 | +; CHECK-NEXT: [[MUL1:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 4, i64 [[TMP8]]) |
| 24 | +; CHECK-NEXT: [[MUL_RESULT2:%.*]] = extractvalue { i64, i1 } [[MUL1]], 0 |
| 25 | +; CHECK-NEXT: [[MUL_OVERFLOW3:%.*]] = extractvalue { i64, i1 } [[MUL1]], 1 |
| 26 | +; CHECK-NEXT: [[TMP13:%.*]] = sub i64 0, [[MUL_RESULT2]] |
| 27 | +; CHECK-NEXT: [[TMP14:%.*]] = getelementptr i8, ptr [[SCEVGEP]], i64 [[MUL_RESULT2]] |
| 28 | +; CHECK-NEXT: [[TMP15:%.*]] = icmp ult ptr [[TMP14]], [[SCEVGEP]] |
| 29 | +; CHECK-NEXT: [[TMP16:%.*]] = or i1 [[TMP15]], [[MUL_OVERFLOW3]] |
| 30 | +; CHECK-NEXT: [[TMP17:%.*]] = or i1 [[TMP12]], [[TMP16]] |
| 31 | +; CHECK-NEXT: br i1 [[TMP17]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]] |
12 | 32 | ; CHECK: [[VECTOR_PH]]:
|
13 |
| -; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i16> poison, i16 [[TMP0]], i64 0 |
| 33 | +; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 8 |
| 34 | +; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]] |
| 35 | +; CHECK-NEXT: [[TMP19:%.*]] = mul i64 [[N_VEC]], 4 |
| 36 | +; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[P]], i64 [[TMP19]] |
| 37 | +; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i16> poison, i16 [[VAL]], i64 0 |
14 | 38 | ; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i16> [[BROADCAST_SPLATINSERT]], <4 x i16> poison, <4 x i32> zeroinitializer
|
| 39 | +; CHECK-NEXT: [[BROADCAST_SPLATINSERT4:%.*]] = insertelement <4 x half> poison, half [[FVAL]], i64 0 |
| 40 | +; CHECK-NEXT: [[BROADCAST_SPLAT5:%.*]] = shufflevector <4 x half> [[BROADCAST_SPLATINSERT4]], <4 x half> poison, <4 x i32> zeroinitializer |
15 | 41 | ; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
|
16 | 42 | ; CHECK: [[VECTOR_BODY]]:
|
17 | 43 | ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
|
18 | 44 | ; CHECK-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 4
|
19 | 45 | ; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[OFFSET_IDX]], 16
|
20 |
| -; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr null, i64 [[OFFSET_IDX]] |
21 |
| -; CHECK-NEXT: [[NEXT_GEP1:%.*]] = getelementptr i8, ptr null, i64 [[TMP1]] |
| 46 | +; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[P]], i64 [[OFFSET_IDX]] |
| 47 | +; CHECK-NEXT: [[NEXT_GEP1:%.*]] = getelementptr i8, ptr [[P]], i64 [[TMP1]] |
22 | 48 | ; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[BROADCAST_SPLAT]] to <4 x half>
|
23 |
| -; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x half> [[TMP2]], <4 x half> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> |
| 49 | +; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x half> [[TMP2]], <4 x half> [[BROADCAST_SPLAT5]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> |
24 | 50 | ; CHECK-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <8 x half> [[TMP3]], <8 x half> poison, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
|
25 |
| -; CHECK-NEXT: store <8 x half> [[INTERLEAVED_VEC]], ptr [[NEXT_GEP]], align 1 |
26 |
| -; CHECK-NEXT: store <8 x half> [[INTERLEAVED_VEC]], ptr [[NEXT_GEP1]], align 1 |
| 51 | +; CHECK-NEXT: store <8 x half> [[INTERLEAVED_VEC]], ptr [[NEXT_GEP]], align 2 |
| 52 | +; CHECK-NEXT: store <8 x half> [[INTERLEAVED_VEC]], ptr [[NEXT_GEP1]], align 2 |
27 | 53 | ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8
|
28 |
| -; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], -9223372036854775808 |
29 |
| -; CHECK-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] |
| 54 | +; CHECK-NEXT: [[TMP25:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] |
| 55 | +; CHECK-NEXT: br i1 [[TMP25]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] |
30 | 56 | ; CHECK: [[MIDDLE_BLOCK]]:
|
31 |
| -; CHECK-NEXT: br i1 true, label %[[FOR_END_LOOPEXIT909:.*]], label %[[SCALAR_PH]] |
| 57 | +; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] |
| 58 | +; CHECK-NEXT: br i1 [[CMP_N]], label %[[END:.*]], label %[[SCALAR_PH]] |
32 | 59 | ; CHECK: [[SCALAR_PH]]:
|
33 |
| -; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi ptr [ null, %[[MIDDLE_BLOCK]] ], [ null, %[[ENTRY]] ] |
34 |
| -; CHECK-NEXT: [[BC_RESUME_VAL3:%.*]] = phi i64 [ 0, %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] |
35 |
| -; CHECK-NEXT: br label %[[DO_BODY93_I705:.*]] |
36 |
| -; CHECK: [[DO_BODY93_I705]]: |
37 |
| -; CHECK-NEXT: [[DEST_10_I706:%.*]] = phi ptr [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[ADD_PTR97_I709:%.*]], %[[DO_BODY93_I705]] ] |
38 |
| -; CHECK-NEXT: [[LEN_ADDR_8_I707:%.*]] = phi i64 [ [[BC_RESUME_VAL3]], %[[SCALAR_PH]] ], [ [[SUB99_I710:%.*]], %[[DO_BODY93_I705]] ] |
39 |
| -; CHECK-NEXT: store i16 [[TMP0]], ptr [[DEST_10_I706]], align 1 |
40 |
| -; CHECK-NEXT: [[ARRAYIDX96_I708:%.*]] = getelementptr i16, ptr [[DEST_10_I706]], i64 1 |
41 |
| -; CHECK-NEXT: store half 0xH0000, ptr [[ARRAYIDX96_I708]], align 1 |
42 |
| -; CHECK-NEXT: [[ADD_PTR97_I709]] = getelementptr i16, ptr [[DEST_10_I706]], i64 2 |
43 |
| -; CHECK-NEXT: [[SUB99_I710]] = add i64 [[LEN_ADDR_8_I707]], -2 |
44 |
| -; CHECK-NEXT: [[TOBOOL100_NOT_I711:%.*]] = icmp eq i64 [[SUB99_I710]], 0 |
45 |
| -; CHECK-NEXT: br i1 [[TOBOOL100_NOT_I711]], label %[[FOR_END_LOOPEXIT909]], label %[[DO_BODY93_I705]], !llvm.loop [[LOOP3:![0-9]+]] |
46 |
| -; CHECK: [[FOR_END_LOOPEXIT909]]: |
| 60 | +; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi ptr [ [[TMP20]], %[[MIDDLE_BLOCK]] ], [ [[P]], %[[ENTRY]] ], [ [[P]], %[[VECTOR_SCEVCHECK]] ] |
| 61 | +; CHECK-NEXT: [[BC_RESUME_VAL8:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_SCEVCHECK]] ] |
| 62 | +; CHECK-NEXT: br label %[[LOOP:.*]] |
| 63 | +; CHECK: [[LOOP]]: |
| 64 | +; CHECK-NEXT: [[RES:%.*]] = phi ptr [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[RES_NEXT:%.*]], %[[LOOP]] ] |
| 65 | +; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL8]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ] |
| 66 | +; CHECK-NEXT: store i16 [[VAL]], ptr [[RES]], align 2 |
| 67 | +; CHECK-NEXT: [[RES_OFFSET:%.*]] = getelementptr i16, ptr [[RES]], i64 1 |
| 68 | +; CHECK-NEXT: store half [[FVAL]], ptr [[RES_OFFSET]], align 2 |
| 69 | +; CHECK-NEXT: [[RES_NEXT]] = getelementptr i16, ptr [[RES]], i64 2 |
| 70 | +; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 |
| 71 | +; CHECK-NEXT: [[EXIT_COND:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]] |
| 72 | +; CHECK-NEXT: br i1 [[EXIT_COND]], label %[[END]], label %[[LOOP]], !llvm.loop [[LOOP3:![0-9]+]] |
| 73 | +; CHECK: [[END]]: |
47 | 74 | ; CHECK-NEXT: ret i32 0
|
48 | 75 | ;
|
49 | 76 | entry:
|
50 |
| - br label %do.body93.i705 |
| 77 | + br label %loop |
51 | 78 |
|
52 |
| -do.body93.i705: |
53 |
| - %dest.10.i706 = phi ptr [ null, %entry ], [ %add.ptr97.i709, %do.body93.i705 ] |
54 |
| - %len.addr.8.i707 = phi i64 [ 0, %entry ], [ %sub99.i710, %do.body93.i705 ] |
55 |
| - store i16 %0, ptr %dest.10.i706, align 1 |
56 |
| - %arrayidx96.i708 = getelementptr i16, ptr %dest.10.i706, i64 1 |
57 |
| - store half 0.0, ptr %arrayidx96.i708, align 1 |
58 |
| - %add.ptr97.i709 = getelementptr i16, ptr %dest.10.i706, i64 2 |
59 |
| - %sub99.i710 = add i64 %len.addr.8.i707, -2 |
60 |
| - %tobool100.not.i711 = icmp eq i64 %sub99.i710, 0 |
61 |
| - br i1 %tobool100.not.i711, label %for.end.loopexit909, label %do.body93.i705 |
| 79 | +loop: |
| 80 | + %res = phi ptr [ %p, %entry ], [ %res.next, %loop ] |
| 81 | + %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] |
| 82 | + store i16 %val, ptr %res |
| 83 | + %res.offset = getelementptr i16, ptr %res, i64 1 |
| 84 | + store half %fval, ptr %res.offset |
| 85 | + %res.next = getelementptr i16, ptr %res, i64 2 |
| 86 | + %iv.next = add i64 %iv, 1 |
| 87 | + %exit.cond = icmp eq i64 %iv.next, %n |
| 88 | + br i1 %exit.cond, label %end, label %loop |
62 | 89 |
|
63 |
| -for.end.loopexit909: |
| 90 | +end: |
64 | 91 | ret i32 0
|
65 | 92 | }
|
66 |
| -;. |
67 |
| -; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]} |
68 |
| -; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1} |
69 |
| -; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"} |
70 |
| -; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]} |
71 |
| -;. |
|
0 commit comments