nounwind for vector tests since cfi directives are causing CI failures

Author: tgross35

llvm/test/CodeGen/AArch64/sve-fixed-vector-llrint.ll

@@ -1,7 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=aarch64 -mattr=+sve -aarch64-sve-vector-bits-min=256 | FileCheck %s
 
-define <1 x i64> @llrint_v1i64_v1f16(<1 x half> %x) {
+define <1 x i64> @llrint_v1i64_v1f16(<1 x half> %x) nounwind {
 ; CHECK-LABEL: llrint_v1i64_v1f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    frintx h0, h0
@@ -13,7 +13,7 @@ define <1 x i64> @llrint_v1i64_v1f16(<1 x half> %x) {
 }
 declare <1 x i64> @llvm.llrint.v1i64.v1f16(<1 x half>)
 
-define <2 x i64> @llrint_v1i64_v2f16(<2 x half> %x) {
+define <2 x i64> @llrint_v1i64_v2f16(<2 x half> %x) nounwind {
 ; CHECK-LABEL: llrint_v1i64_v2f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
@@ -30,7 +30,7 @@ define <2 x i64> @llrint_v1i64_v2f16(<2 x half> %x) {
 }
 declare <2 x i64> @llvm.llrint.v2i64.v2f16(<2 x half>)
 
-define <4 x i64> @llrint_v4i64_v4f16(<4 x half> %x) {
+define <4 x i64> @llrint_v4i64_v4f16(<4 x half> %x) nounwind {
 ; CHECK-LABEL: llrint_v4i64_v4f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    frintx v0.4h, v0.4h
@@ -51,7 +51,7 @@ define <4 x i64> @llrint_v4i64_v4f16(<4 x half> %x) {
 }
 declare <4 x i64> @llvm.llrint.v4i64.v4f16(<4 x half>)
 
-define <8 x i64> @llrint_v8i64_v8f16(<8 x half> %x) {
+define <8 x i64> @llrint_v8i64_v8f16(<8 x half> %x) nounwind {
 ; CHECK-LABEL: llrint_v8i64_v8f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
@@ -85,7 +85,7 @@ define <8 x i64> @llrint_v8i64_v8f16(<8 x half> %x) {
 }
 declare <8 x i64> @llvm.llrint.v8i64.v8f16(<8 x half>)
 
-define <16 x i64> @llrint_v16i64_v16f16(<16 x half> %x) {
+define <16 x i64> @llrint_v16i64_v16f16(<16 x half> %x) nounwind {
 ; CHECK-LABEL: llrint_v16i64_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ext v2.16b, v1.16b, v1.16b, #8
@@ -144,16 +144,13 @@ define <16 x i64> @llrint_v16i64_v16f16(<16 x half> %x) {
 }
 declare <16 x i64> @llvm.llrint.v16i64.v16f16(<16 x half>)
 
-define <32 x i64> @llrint_v32i64_v32f16(<32 x half> %x) {
+define <32 x i64> @llrint_v32i64_v32f16(<32 x half> %x) nounwind {
 ; CHECK-LABEL: llrint_v32i64_v32f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
 ; CHECK-NEXT:    sub x9, sp, #272
 ; CHECK-NEXT:    mov x29, sp
 ; CHECK-NEXT:    and sp, x9, #0xffffffffffffffe0
-; CHECK-NEXT:    .cfi_def_cfa w29, 16
-; CHECK-NEXT:    .cfi_offset w30, -8
-; CHECK-NEXT:    .cfi_offset w29, -16
 ; CHECK-NEXT:    frintx v5.4h, v0.4h
 ; CHECK-NEXT:    ext v0.16b, v0.16b, v0.16b, #8
 ; CHECK-NEXT:    ext v4.16b, v1.16b, v1.16b, #8
@@ -278,7 +275,7 @@ define <32 x i64> @llrint_v32i64_v32f16(<32 x half> %x) {
 }
 declare <32 x i64> @llvm.llrint.v32i64.v32f16(<32 x half>)
 
-define <1 x i64> @llrint_v1i64_v1f32(<1 x float> %x) {
+define <1 x i64> @llrint_v1i64_v1f32(<1 x float> %x) nounwind {
 ; CHECK-LABEL: llrint_v1i64_v1f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
@@ -291,7 +288,7 @@ define <1 x i64> @llrint_v1i64_v1f32(<1 x float> %x) {
 }
 declare <1 x i64> @llvm.llrint.v1i64.v1f32(<1 x float>)
 
-define <2 x i64> @llrint_v2i64_v2f32(<2 x float> %x) {
+define <2 x i64> @llrint_v2i64_v2f32(<2 x float> %x) nounwind {
 ; CHECK-LABEL: llrint_v2i64_v2f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    frintx v0.2s, v0.2s
@@ -303,7 +300,7 @@ define <2 x i64> @llrint_v2i64_v2f32(<2 x float> %x) {
 }
 declare <2 x i64> @llvm.llrint.v2i64.v2f32(<2 x float>)
 
-define <4 x i64> @llrint_v4i64_v4f32(<4 x float> %x) {
+define <4 x i64> @llrint_v4i64_v4f32(<4 x float> %x) nounwind {
 ; CHECK-LABEL: llrint_v4i64_v4f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    frintx v0.4s, v0.4s
@@ -324,7 +321,7 @@ define <4 x i64> @llrint_v4i64_v4f32(<4 x float> %x) {
 }
 declare <4 x i64> @llvm.llrint.v4i64.v4f32(<4 x float>)
 
-define <8 x i64> @llrint_v8i64_v8f32(<8 x float> %x) {
+define <8 x i64> @llrint_v8i64_v8f32(<8 x float> %x) nounwind {
 ; CHECK-LABEL: llrint_v8i64_v8f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    frintx v0.4s, v0.4s
@@ -357,7 +354,7 @@ define <8 x i64> @llrint_v8i64_v8f32(<8 x float> %x) {
 }
 declare <8 x i64> @llvm.llrint.v8i64.v8f32(<8 x float>)
 
-define <16 x i64> @llrint_v16i64_v16f32(<16 x float> %x) {
+define <16 x i64> @llrint_v16i64_v16f32(<16 x float> %x) nounwind {
 ; CHECK-LABEL: llrint_v16i64_v16f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    frintx v3.4s, v3.4s
@@ -414,16 +411,13 @@ define <16 x i64> @llrint_v16i64_v16f32(<16 x float> %x) {
 }
 declare <16 x i64> @llvm.llrint.v16i64.v16f32(<16 x float>)
 
-define <32 x i64> @llrint_v32i64_v32f32(<32 x float> %x) {
+define <32 x i64> @llrint_v32i64_v32f32(<32 x float> %x) nounwind {
 ; CHECK-LABEL: llrint_v32i64_v32f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
 ; CHECK-NEXT:    sub x9, sp, #272
 ; CHECK-NEXT:    mov x29, sp
 ; CHECK-NEXT:    and sp, x9, #0xffffffffffffffe0
-; CHECK-NEXT:    .cfi_def_cfa w29, 16
-; CHECK-NEXT:    .cfi_offset w30, -8
-; CHECK-NEXT:    .cfi_offset w29, -16
 ; CHECK-NEXT:    frintx v0.4s, v0.4s
 ; CHECK-NEXT:    frintx v1.4s, v1.4s
 ; CHECK-NEXT:    frintx v2.4s, v2.4s
@@ -544,7 +538,7 @@ define <32 x i64> @llrint_v32i64_v32f32(<32 x float> %x) {
 }
 declare <32 x i64> @llvm.llrint.v32i64.v32f32(<32 x float>)
 
-define <1 x i64> @llrint_v1i64_v1f64(<1 x double> %x) {
+define <1 x i64> @llrint_v1i64_v1f64(<1 x double> %x) nounwind {
 ; CHECK-LABEL: llrint_v1i64_v1f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    frintx d0, d0
@@ -556,7 +550,7 @@ define <1 x i64> @llrint_v1i64_v1f64(<1 x double> %x) {
 }
 declare <1 x i64> @llvm.llrint.v1i64.v1f64(<1 x double>)
 
-define <2 x i64> @llrint_v2i64_v2f64(<2 x double> %x) {
+define <2 x i64> @llrint_v2i64_v2f64(<2 x double> %x) nounwind {
 ; CHECK-LABEL: llrint_v2i64_v2f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    frintx v0.2d, v0.2d
@@ -567,7 +561,7 @@ define <2 x i64> @llrint_v2i64_v2f64(<2 x double> %x) {
 }
 declare <2 x i64> @llvm.llrint.v2i64.v2f64(<2 x double>)
 
-define <4 x i64> @llrint_v4i64_v4f64(<4 x double> %x) {
+define <4 x i64> @llrint_v4i64_v4f64(<4 x double> %x) nounwind {
 ; CHECK-LABEL: llrint_v4i64_v4f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p0.d, vl2
@@ -593,7 +587,7 @@ define <4 x i64> @llrint_v4i64_v4f64(<4 x double> %x) {
 }
 declare <4 x i64> @llvm.llrint.v4i64.v4f64(<4 x double>)
 
-define <8 x i64> @llrint_v8i64_v8f64(<8 x double> %x) {
+define <8 x i64> @llrint_v8i64_v8f64(<8 x double> %x) nounwind {
 ; CHECK-LABEL: llrint_v8i64_v8f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p0.d, vl2
@@ -635,7 +629,7 @@ define <8 x i64> @llrint_v8i64_v8f64(<8 x double> %x) {
 }
 declare <8 x i64> @llvm.llrint.v8i64.v8f64(<8 x double>)
 
-define <16 x i64> @llrint_v16f64(<16 x double> %x) {
+define <16 x i64> @llrint_v16f64(<16 x double> %x) nounwind {
 ; CHECK-LABEL: llrint_v16f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p1.d, vl2
@@ -708,16 +702,13 @@ define <16 x i64> @llrint_v16f64(<16 x double> %x) {
 }
 declare <16 x i64> @llvm.llrint.v16i64.v16f64(<16 x double>)
 
-define <32 x i64> @llrint_v32f64(<32 x double> %x) {
+define <32 x i64> @llrint_v32f64(<32 x double> %x) nounwind {
 ; CHECK-LABEL: llrint_v32f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
 ; CHECK-NEXT:    sub x9, sp, #272
 ; CHECK-NEXT:    mov x29, sp
 ; CHECK-NEXT:    and sp, x9, #0xffffffffffffffe0
-; CHECK-NEXT:    .cfi_def_cfa w29, 16
-; CHECK-NEXT:    .cfi_offset w30, -8
-; CHECK-NEXT:    .cfi_offset w29, -16
 ; CHECK-NEXT:    ptrue p1.d, vl2
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
 ; CHECK-NEXT:    // kill: def $q1 killed $q1 def $z1
@@ -862,12 +853,10 @@ define <32 x i64> @llrint_v32f64(<32 x double> %x) {
 }
 declare <32 x i64> @llvm.llrint.v32i64.v32f64(<32 x double>)
 
-define <1 x i64> @llrint_v1i64_v1fp128(<1 x fp128> %x) {
+define <1 x i64> @llrint_v1i64_v1fp128(<1 x fp128> %x) nounwind {
 ; CHECK-LABEL: llrint_v1i64_v1fp128:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-NEXT:    .cfi_offset w30, -16
 ; CHECK-NEXT:    bl llrintl
 ; CHECK-NEXT:    fmov d0, x0
 ; CHECK-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
@@ -877,15 +866,13 @@ define <1 x i64> @llrint_v1i64_v1fp128(<1 x fp128> %x) {
 }
 declare <1 x i64> @llvm.llrint.v1i64.v1fp128(<1 x fp128>)
 
-define <2 x i64> @llrint_v2i64_v2fp128(<2 x fp128> %x) {
+define <2 x i64> @llrint_v2i64_v2fp128(<2 x fp128> %x) nounwind {
 ; CHECK-LABEL: llrint_v2i64_v2fp128:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    sub sp, sp, #48
-; CHECK-NEXT:    str x30, [sp, #32] // 8-byte Folded Spill
-; CHECK-NEXT:    .cfi_def_cfa_offset 48
-; CHECK-NEXT:    .cfi_offset w30, -16
 ; CHECK-NEXT:    str q0, [sp] // 16-byte Folded Spill
 ; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    str x30, [sp, #32] // 8-byte Folded Spill
 ; CHECK-NEXT:    bl llrintl
 ; CHECK-NEXT:    fmov d0, x0
 ; CHECK-NEXT:    str q0, [sp, #16] // 16-byte Folded Spill
@@ -902,15 +889,12 @@ define <2 x i64> @llrint_v2i64_v2fp128(<2 x fp128> %x) {
 }
 declare <2 x i64> @llvm.llrint.v2i64.v2fp128(<2 x fp128>)
 
-define <4 x i64> @llrint_v4i64_v4fp128(<4 x fp128> %x) {
+define <4 x i64> @llrint_v4i64_v4fp128(<4 x fp128> %x) nounwind {
 ; CHECK-LABEL: llrint_v4i64_v4fp128:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
 ; CHECK-NEXT:    sub sp, sp, #64
 ; CHECK-NEXT:    addvl sp, sp, #-1
-; CHECK-NEXT:    .cfi_escape 0x0f, 0x0d, 0x8f, 0x00, 0x11, 0xd0, 0x00, 0x22, 0x11, 0x08, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 80 + 8 * VG
-; CHECK-NEXT:    .cfi_offset w30, -8
-; CHECK-NEXT:    .cfi_offset w29, -16
 ; CHECK-NEXT:    str q0, [sp, #48] // 16-byte Folded Spill
 ; CHECK-NEXT:    mov v0.16b, v3.16b
 ; CHECK-NEXT:    stp q2, q1, [sp, #16] // 32-byte Folded Spill
@@ -950,15 +934,12 @@ define <4 x i64> @llrint_v4i64_v4fp128(<4 x fp128> %x) {
 }
 declare <4 x i64> @llvm.llrint.v4i64.v4fp128(<4 x fp128>)
 
-define <8 x i64> @llrint_v8i64_v8fp128(<8 x fp128> %x) {
+define <8 x i64> @llrint_v8i64_v8fp128(<8 x fp128> %x) nounwind {
 ; CHECK-LABEL: llrint_v8i64_v8fp128:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
 ; CHECK-NEXT:    sub sp, sp, #128
 ; CHECK-NEXT:    addvl sp, sp, #-2
-; CHECK-NEXT:    .cfi_escape 0x0f, 0x0d, 0x8f, 0x00, 0x11, 0x90, 0x01, 0x22, 0x11, 0x10, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 144 + 16 * VG
-; CHECK-NEXT:    .cfi_offset w30, -8
-; CHECK-NEXT:    .cfi_offset w29, -16
 ; CHECK-NEXT:    str q0, [sp, #112] // 16-byte Folded Spill
 ; CHECK-NEXT:    mov v0.16b, v7.16b
 ; CHECK-NEXT:    stp q6, q5, [sp, #16] // 32-byte Folded Spill
@@ -1030,15 +1011,12 @@ define <8 x i64> @llrint_v8i64_v8fp128(<8 x fp128> %x) {
 }
 declare <8 x i64> @llvm.llrint.v8i64.v8fp128(<8 x fp128>)
 
-define <16 x i64> @llrint_v16fp128(<16 x fp128> %x) {
+define <16 x i64> @llrint_v16fp128(<16 x fp128> %x) nounwind {
 ; CHECK-LABEL: llrint_v16fp128:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
 ; CHECK-NEXT:    sub sp, sp, #256
 ; CHECK-NEXT:    addvl sp, sp, #-4
-; CHECK-NEXT:    .cfi_escape 0x0f, 0x0d, 0x8f, 0x00, 0x11, 0x90, 0x02, 0x22, 0x11, 0x20, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 272 + 32 * VG
-; CHECK-NEXT:    .cfi_offset w30, -8
-; CHECK-NEXT:    .cfi_offset w29, -16
 ; CHECK-NEXT:    addvl x8, sp, #4
 ; CHECK-NEXT:    str q1, [sp, #240] // 16-byte Folded Spill
 ; CHECK-NEXT:    ldr q1, [x8, #272]
@@ -1194,17 +1172,13 @@ define <16 x i64> @llrint_v16fp128(<16 x fp128> %x) {
 }
 declare <16 x i64> @llvm.llrint.v16i64.v16fp128(<16 x fp128>)
 
-define <32 x i64> @llrint_v32fp128(<32 x fp128> %x) {
+define <32 x i64> @llrint_v32fp128(<32 x fp128> %x) nounwind {
 ; CHECK-LABEL: llrint_v32fp128:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str x29, [sp, #-32]! // 8-byte Folded Spill
 ; CHECK-NEXT:    stp x30, x19, [sp, #16] // 16-byte Folded Spill
 ; CHECK-NEXT:    sub sp, sp, #512
 ; CHECK-NEXT:    addvl sp, sp, #-8
-; CHECK-NEXT:    .cfi_escape 0x0f, 0x0e, 0x8f, 0x00, 0x11, 0xa0, 0x04, 0x22, 0x11, 0xc0, 0x00, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 544 + 64 * VG
-; CHECK-NEXT:    .cfi_offset w19, -8
-; CHECK-NEXT:    .cfi_offset w30, -16
-; CHECK-NEXT:    .cfi_offset w29, -32
 ; CHECK-NEXT:    addvl x9, sp, #8
 ; CHECK-NEXT:    stp q2, q1, [sp, #16] // 32-byte Folded Spill
 ; CHECK-NEXT:    mov x19, x8