Fix typo

Author: arsenm

llvm/lib/Target/AMDGPU/SIRegisterInfo.td

@@ -964,9 +964,9 @@ class VRegClassBase<int numRegs, list<ValueType> regTypes, dag regList> :
   // regsters with numRegs 17+ we give SizePriority of 15. In  practice, there is only one 
   // RegClass per Vector Register type in each of these groups (i.e. numRegs = 15,16 : {VReg_512}, 
   // and numRegs = 17+ : {VReg_1024}). Therefore, we have not lost any info by compressing. 
-  defvar SizePrioriity = !if(!le(numRegs, 14), !sub(numRegs, 1), !if(!le(numRegs, 16), 14, 15));
+  defvar SizePriority = !if(!le(numRegs, 14), !sub(numRegs, 1), !if(!le(numRegs, 16), 14, 15));
 
-  let AllocationPriority = !add(SizePrioriity, !mul(BaseClassPriority, BaseClassScaleFactor));
+  let AllocationPriority = !add(SizePriority, !mul(BaseClassPriority, BaseClassScaleFactor));
   let Weight = numRegs;
 }