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[PowerPC][CLANG] DMF VSX Vector float GER 2x (rank-2 update) (#147383)
Add clang builtins for DMF VSX Vector floats: ``` void __builtin_mma_dmxvf16gerx2 (__dmr1024 *, __vector_pair, vec_t); void __builtin_mma_dmxvf16gerx2nn (__dmr1024 *, __vector_pair, vec_t); void __builtin_mma_dmxvf16gerx2np (__dmr1024 *, __vector_pair, vec_t); void __builtin_mma_dmxvf16gerx2pn (__dmr1024 *, __vector_pair, vec_t); void __builtin_mma_dmxvf16gerx2pp (__dmr1024 *, __vector_pair, vec_t); void __builtin_mma_pmdmxvf16gerx2 (__dmr1024 *, __vector_pair, vec_t, uint8, uint4, uint2); void __builtin_mma_pmdmxvf16gerx2nn (__dmr1024 *, __vector_pair, vec_t, uint8, uint4, uint2); void __builtin_mma_pmdmxvf16gerx2np (__dmr1024 *, __vector_pair, vec_t, uint8, uint4, uint2); void __builtin_mma_pmdmxvf16gerx2pn (__dmr1024 *, __vector_pair, vec_t, uint8, uint4, uint2); void __builtin_mma_pmdmxvf16gerx2pp (__dmr1024 *, __vector_pair, vec_t, uint8, uint4, uint2); void __builtin_mma_dmxvbf16gerx2 (__dmr1024 *, __vector_pair, vec_t); void __builtin_mma_dmxvbf16gerx2nn (__dmr1024 *, __vector_pair, vec_t); void __builtin_mma_dmxvbf16gerx2np (__dmr1024 *, __vector_pair, vec_t); void __builtin_mma_dmxvbf16gerx2pn (__dmr1024 *, __vector_pair, vec_t); void __builtin_mma_dmxvbf16gerx2pp (__dmr1024 *, __vector_pair, vec_t); void __builtin_mma_pmdmxvbf16gerx2 (__dmr1024 *, __vector_pair, vec_t, uint8, uint4, uint2); void __builtin_mma_pmdmxvbf16gerx2nn (__dmr1024 *, __vector_pair, vec_t, uint8, uint4, uint2); void __builtin_mma_pmdmxvbf16gerx2np (__dmr1024 *, __vector_pair, vec_t, uint8, uint4, uint2); void __builtin_mma_pmdmxvbf16gerx2pn (__dmr1024 *, __vector_pair, vec_t, uint8, uint4, uint2); void __builtin_mma_pmdmxvbf16gerx2pp (__dmr1024 *, __vector_pair, vec_t, uint8, uint4, uint2); ```
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‎clang/include/clang/Basic/BuiltinsPPC.def‎

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Original file line numberDiff line numberDiff line change
@@ -1122,6 +1122,14 @@ UNALIASED_CUSTOM_MMA_BUILTIN(mma_xvbf16ger2, "vW512*VV",
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"mma,paired-vector-memops")
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UNALIASED_CUSTOM_MMA_BUILTIN(mma_pmxvbf16ger2, "vW512*VVi15i15i3",
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"mma,paired-vector-memops")
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UNALIASED_CUSTOM_MMA_BUILTIN(mma_dmxvbf16gerx2, "vW1024*W256V",
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"mma,isa-future-instructions")
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UNALIASED_CUSTOM_MMA_BUILTIN(mma_pmdmxvbf16gerx2, "vW1024*W256Vi255i15i3",
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"mma,isa-future-instructions")
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UNALIASED_CUSTOM_MMA_BUILTIN(mma_dmxvf16gerx2, "vW1024*W256V",
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"mma,isa-future-instructions")
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UNALIASED_CUSTOM_MMA_BUILTIN(mma_pmdmxvf16gerx2, "vW1024*W256Vi255i15i3",
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"mma,isa-future-instructions")
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// FIXME: Obviously incomplete.
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‎clang/test/CodeGen/PowerPC/builtins-dmf-vsx-vector-float.c‎

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@@ -0,0 +1,309 @@
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// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5
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// Update then manual applied to commonize the checks for AIX and LoP.
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// RUN: %clang_cc1 -O3 -triple powerpc64le-unknown-unknown -target-cpu future \
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// RUN: -emit-llvm %s -o - | FileCheck %s
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// RUN: %clang_cc1 -O3 -triple powerpc64-ibm-aix -target-cpu future \
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// RUN: -emit-llvm %s -o - | FileCheck %s
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// CHECK-LABEL: void @test_dmxvbf16gerx2(
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: [[TMP0:%.*]] = load <256 x i1>, ptr [[VPP:%.*]], align 32, !tbaa [[TBAA2:![0-9]+]]
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// CHECK-NEXT: [[TMP1:%.*]] = tail call <1024 x i1> @llvm.ppc.mma.dmxvbf16gerx2(<256 x i1> [[TMP0]], <16 x i8> [[VC:%.*]])
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// CHECK-NEXT: store <1024 x i1> [[TMP1]], ptr [[RESP:%.*]], align 128, !tbaa [[TBAA6:![0-9]+]]
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// CHECK-NEXT: ret void
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//
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void test_dmxvbf16gerx2(unsigned char *vdmrp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
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__dmr1024 vdmr = *((__dmr1024 *)vdmrp);
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__vector_pair vp = *((__vector_pair *)vpp);
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__builtin_mma_dmxvbf16gerx2(&vdmr, vp, vc);
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*((__dmr1024 *)resp) = vdmr;
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}
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// CHECK-LABEL: void @test_dmxvbf16gerx2nn(
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP:%.*]], align 128, !tbaa [[TBAA6]]
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// CHECK-NEXT: [[TMP1:%.*]] = load <256 x i1>, ptr [[VPP:%.*]], align 32, !tbaa [[TBAA2]]
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// CHECK-NEXT: [[TMP2:%.*]] = tail call <1024 x i1> @llvm.ppc.mma.dmxvbf16gerx2nn(<1024 x i1> [[TMP0]], <256 x i1> [[TMP1]], <16 x i8> [[VC:%.*]])
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// CHECK-NEXT: store <1024 x i1> [[TMP2]], ptr [[RESP:%.*]], align 128, !tbaa [[TBAA6]]
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// CHECK-NEXT: ret void
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//
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void test_dmxvbf16gerx2nn(unsigned char *vdmrp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
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__dmr1024 vdmr = *((__dmr1024 *)vdmrp);
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__vector_pair vp = *((__vector_pair *)vpp);
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__builtin_mma_dmxvbf16gerx2nn(&vdmr, vp, vc);
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*((__dmr1024 *)resp) = vdmr;
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}
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// CHECK-LABEL: void @test_dmxvbf16gerx2np(
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP:%.*]], align 128, !tbaa [[TBAA6]]
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// CHECK-NEXT: [[TMP1:%.*]] = load <256 x i1>, ptr [[VPP:%.*]], align 32, !tbaa [[TBAA2]]
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// CHECK-NEXT: [[TMP2:%.*]] = tail call <1024 x i1> @llvm.ppc.mma.dmxvbf16gerx2np(<1024 x i1> [[TMP0]], <256 x i1> [[TMP1]], <16 x i8> [[VC:%.*]])
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// CHECK-NEXT: store <1024 x i1> [[TMP2]], ptr [[RESP:%.*]], align 128, !tbaa [[TBAA6]]
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// CHECK-NEXT: ret void
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//
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void test_dmxvbf16gerx2np(unsigned char *vdmrp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
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__dmr1024 vdmr = *((__dmr1024 *)vdmrp);
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__vector_pair vp = *((__vector_pair *)vpp);
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__builtin_mma_dmxvbf16gerx2np(&vdmr, vp, vc);
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*((__dmr1024 *)resp) = vdmr;
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}
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// CHECK-LABEL: void @test_dmxvbf16gerx2pn(
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP:%.*]], align 128, !tbaa [[TBAA6]]
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// CHECK-NEXT: [[TMP1:%.*]] = load <256 x i1>, ptr [[VPP:%.*]], align 32, !tbaa [[TBAA2]]
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// CHECK-NEXT: [[TMP2:%.*]] = tail call <1024 x i1> @llvm.ppc.mma.dmxvbf16gerx2pn(<1024 x i1> [[TMP0]], <256 x i1> [[TMP1]], <16 x i8> [[VC:%.*]])
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// CHECK-NEXT: store <1024 x i1> [[TMP2]], ptr [[RESP:%.*]], align 128, !tbaa [[TBAA6]]
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// CHECK-NEXT: ret void
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//
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void test_dmxvbf16gerx2pn(unsigned char *vdmrp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
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__dmr1024 vdmr = *((__dmr1024 *)vdmrp);
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__vector_pair vp = *((__vector_pair *)vpp);
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__builtin_mma_dmxvbf16gerx2pn(&vdmr, vp, vc);
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*((__dmr1024 *)resp) = vdmr;
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}
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// CHECK-LABEL: void @test_dmxvbf16gerx2pp(
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP:%.*]], align 128, !tbaa [[TBAA6]]
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// CHECK-NEXT: [[TMP1:%.*]] = load <256 x i1>, ptr [[VPP:%.*]], align 32, !tbaa [[TBAA2]]
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// CHECK-NEXT: [[TMP2:%.*]] = tail call <1024 x i1> @llvm.ppc.mma.dmxvbf16gerx2pp(<1024 x i1> [[TMP0]], <256 x i1> [[TMP1]], <16 x i8> [[VC:%.*]])
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// CHECK-NEXT: store <1024 x i1> [[TMP2]], ptr [[RESP:%.*]], align 128, !tbaa [[TBAA6]]
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// CHECK-NEXT: ret void
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//
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void test_dmxvbf16gerx2pp(unsigned char *vdmrp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
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__dmr1024 vdmr = *((__dmr1024 *)vdmrp);
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__vector_pair vp = *((__vector_pair *)vpp);
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__builtin_mma_dmxvbf16gerx2pp(&vdmr, vp, vc);
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*((__dmr1024 *)resp) = vdmr;
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}
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// CHECK-LABEL: void @test_pmdmxvbf16gerx2(
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: [[TMP0:%.*]] = load <256 x i1>, ptr [[VPP:%.*]], align 32, !tbaa [[TBAA2]]
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// CHECK-NEXT: [[TMP1:%.*]] = tail call <1024 x i1> @llvm.ppc.mma.pmdmxvbf16gerx2(<256 x i1> [[TMP0]], <16 x i8> [[VC:%.*]], i32 0, i32 0, i32 0)
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// CHECK-NEXT: store <1024 x i1> [[TMP1]], ptr [[RESP:%.*]], align 128, !tbaa [[TBAA6]]
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// CHECK-NEXT: ret void
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//
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void test_pmdmxvbf16gerx2(unsigned char *vdmrp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
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__dmr1024 vdmr = *((__dmr1024 *)vdmrp);
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__vector_pair vp = *((__vector_pair *)vpp);
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__builtin_mma_pmdmxvbf16gerx2(&vdmr, vp, vc, 0, 0, 0);
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*((__dmr1024 *)resp) = vdmr;
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}
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// CHECK-LABEL: void @test_pmdmxvbf16gerx2nn(
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP:%.*]], align 128, !tbaa [[TBAA6]]
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// CHECK-NEXT: [[TMP1:%.*]] = load <256 x i1>, ptr [[VPP:%.*]], align 32, !tbaa [[TBAA2]]
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// CHECK-NEXT: [[TMP2:%.*]] = tail call <1024 x i1> @llvm.ppc.mma.pmdmxvbf16gerx2nn(<1024 x i1> [[TMP0]], <256 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], i32 0, i32 0, i32 0)
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// CHECK-NEXT: store <1024 x i1> [[TMP2]], ptr [[RESP:%.*]], align 128, !tbaa [[TBAA6]]
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// CHECK-NEXT: ret void
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//
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void test_pmdmxvbf16gerx2nn(unsigned char *vdmrp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
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__dmr1024 vdmr = *((__dmr1024 *)vdmrp);
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__vector_pair vp = *((__vector_pair *)vpp);
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__builtin_mma_pmdmxvbf16gerx2nn(&vdmr, vp, vc, 0, 0, 0);
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*((__dmr1024 *)resp) = vdmr;
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}
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// CHECK-LABEL: void @test_pmdmxvbf16gerx2np(
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP:%.*]], align 128, !tbaa [[TBAA6]]
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// CHECK-NEXT: [[TMP1:%.*]] = load <256 x i1>, ptr [[VPP:%.*]], align 32, !tbaa [[TBAA2]]
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// CHECK-NEXT: [[TMP2:%.*]] = tail call <1024 x i1> @llvm.ppc.mma.pmdmxvbf16gerx2np(<1024 x i1> [[TMP0]], <256 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], i32 0, i32 0, i32 0)
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// CHECK-NEXT: store <1024 x i1> [[TMP2]], ptr [[RESP:%.*]], align 128, !tbaa [[TBAA6]]
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// CHECK-NEXT: ret void
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//
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void test_pmdmxvbf16gerx2np(unsigned char *vdmrp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
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__dmr1024 vdmr = *((__dmr1024 *)vdmrp);
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__vector_pair vp = *((__vector_pair *)vpp);
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__builtin_mma_pmdmxvbf16gerx2np(&vdmr, vp, vc, 0, 0, 0);
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*((__dmr1024 *)resp) = vdmr;
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}
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// CHECK-LABEL: void @test_pmdmxvbf16gerx2pn(
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP:%.*]], align 128, !tbaa [[TBAA6]]
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// CHECK-NEXT: [[TMP1:%.*]] = load <256 x i1>, ptr [[VPP:%.*]], align 32, !tbaa [[TBAA2]]
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// CHECK-NEXT: [[TMP2:%.*]] = tail call <1024 x i1> @llvm.ppc.mma.pmdmxvbf16gerx2pn(<1024 x i1> [[TMP0]], <256 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], i32 0, i32 0, i32 0)
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// CHECK-NEXT: store <1024 x i1> [[TMP2]], ptr [[RESP:%.*]], align 128, !tbaa [[TBAA6]]
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// CHECK-NEXT: ret void
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//
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void test_pmdmxvbf16gerx2pn(unsigned char *vdmrp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
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__dmr1024 vdmr = *((__dmr1024 *)vdmrp);
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__vector_pair vp = *((__vector_pair *)vpp);
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__builtin_mma_pmdmxvbf16gerx2pn(&vdmr, vp, vc, 0, 0, 0);
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*((__dmr1024 *)resp) = vdmr;
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}
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// CHECK-LABEL: void @test_pmdmxvbf16gerx2pp(
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP:%.*]], align 128, !tbaa [[TBAA6]]
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// CHECK-NEXT: [[TMP1:%.*]] = load <256 x i1>, ptr [[VPP:%.*]], align 32, !tbaa [[TBAA2]]
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// CHECK-NEXT: [[TMP2:%.*]] = tail call <1024 x i1> @llvm.ppc.mma.pmdmxvbf16gerx2pp(<1024 x i1> [[TMP0]], <256 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], i32 0, i32 0, i32 0)
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// CHECK-NEXT: store <1024 x i1> [[TMP2]], ptr [[RESP:%.*]], align 128, !tbaa [[TBAA6]]
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// CHECK-NEXT: ret void
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//
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void test_pmdmxvbf16gerx2pp(unsigned char *vdmrp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
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__dmr1024 vdmr = *((__dmr1024 *)vdmrp);
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__vector_pair vp = *((__vector_pair *)vpp);
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__builtin_mma_pmdmxvbf16gerx2pp(&vdmr, vp, vc, 0, 0, 0);
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*((__dmr1024 *)resp) = vdmr;
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}
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// CHECK-LABEL: void @test_dmxvf16gerx2(
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: [[TMP0:%.*]] = load <256 x i1>, ptr [[VPP:%.*]], align 32, !tbaa [[TBAA2:![0-9]+]]
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// CHECK-NEXT: [[TMP1:%.*]] = tail call <1024 x i1> @llvm.ppc.mma.dmxvf16gerx2(<256 x i1> [[TMP0]], <16 x i8> [[VC:%.*]])
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// CHECK-NEXT: store <1024 x i1> [[TMP1]], ptr [[RESP:%.*]], align 128, !tbaa [[TBAA6:![0-9]+]]
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// CHECK-NEXT: ret void
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//
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void test_dmxvf16gerx2(unsigned char *vdmrp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
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__dmr1024 vdmr = *((__dmr1024 *)vdmrp);
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__vector_pair vp = *((__vector_pair *)vpp);
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__builtin_mma_dmxvf16gerx2(&vdmr, vp, vc);
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*((__dmr1024 *)resp) = vdmr;
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}
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// CHECK-LABEL: void @test_dmxvf16gerx2nn(
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP:%.*]], align 128, !tbaa [[TBAA6]]
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// CHECK-NEXT: [[TMP1:%.*]] = load <256 x i1>, ptr [[VPP:%.*]], align 32, !tbaa [[TBAA2]]
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// CHECK-NEXT: [[TMP2:%.*]] = tail call <1024 x i1> @llvm.ppc.mma.dmxvf16gerx2nn(<1024 x i1> [[TMP0]], <256 x i1> [[TMP1]], <16 x i8> [[VC:%.*]])
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// CHECK-NEXT: store <1024 x i1> [[TMP2]], ptr [[RESP:%.*]], align 128, !tbaa [[TBAA6]]
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// CHECK-NEXT: ret void
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//
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void test_dmxvf16gerx2nn(unsigned char *vdmrp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
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__dmr1024 vdmr = *((__dmr1024 *)vdmrp);
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__vector_pair vp = *((__vector_pair *)vpp);
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__builtin_mma_dmxvf16gerx2nn(&vdmr, vp, vc);
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*((__dmr1024 *)resp) = vdmr;
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}
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// CHECK-LABEL: void @test_dmxvf16gerx2np(
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP:%.*]], align 128, !tbaa [[TBAA6]]
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// CHECK-NEXT: [[TMP1:%.*]] = load <256 x i1>, ptr [[VPP:%.*]], align 32, !tbaa [[TBAA2]]
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// CHECK-NEXT: [[TMP2:%.*]] = tail call <1024 x i1> @llvm.ppc.mma.dmxvf16gerx2np(<1024 x i1> [[TMP0]], <256 x i1> [[TMP1]], <16 x i8> [[VC:%.*]])
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// CHECK-NEXT: store <1024 x i1> [[TMP2]], ptr [[RESP:%.*]], align 128, !tbaa [[TBAA6]]
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// CHECK-NEXT: ret void
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//
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void test_dmxvf16gerx2np(unsigned char *vdmrp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
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__dmr1024 vdmr = *((__dmr1024 *)vdmrp);
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__vector_pair vp = *((__vector_pair *)vpp);
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__builtin_mma_dmxvf16gerx2np(&vdmr, vp, vc);
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*((__dmr1024 *)resp) = vdmr;
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}
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// CHECK-LABEL: void @test_dmxvf16gerx2pn(
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP:%.*]], align 128, !tbaa [[TBAA6]]
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// CHECK-NEXT: [[TMP1:%.*]] = load <256 x i1>, ptr [[VPP:%.*]], align 32, !tbaa [[TBAA2]]
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// CHECK-NEXT: [[TMP2:%.*]] = tail call <1024 x i1> @llvm.ppc.mma.dmxvf16gerx2pn(<1024 x i1> [[TMP0]], <256 x i1> [[TMP1]], <16 x i8> [[VC:%.*]])
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// CHECK-NEXT: store <1024 x i1> [[TMP2]], ptr [[RESP:%.*]], align 128, !tbaa [[TBAA6]]
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// CHECK-NEXT: ret void
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//
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void test_dmxvf16gerx2pn(unsigned char *vdmrp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
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__dmr1024 vdmr = *((__dmr1024 *)vdmrp);
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__vector_pair vp = *((__vector_pair *)vpp);
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__builtin_mma_dmxvf16gerx2pn(&vdmr, vp, vc);
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*((__dmr1024 *)resp) = vdmr;
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}
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// CHECK-LABEL: void @test_dmxvf16gerx2pp(
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP:%.*]], align 128, !tbaa [[TBAA6]]
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// CHECK-NEXT: [[TMP1:%.*]] = load <256 x i1>, ptr [[VPP:%.*]], align 32, !tbaa [[TBAA2]]
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// CHECK-NEXT: [[TMP2:%.*]] = tail call <1024 x i1> @llvm.ppc.mma.dmxvf16gerx2pp(<1024 x i1> [[TMP0]], <256 x i1> [[TMP1]], <16 x i8> [[VC:%.*]])
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// CHECK-NEXT: store <1024 x i1> [[TMP2]], ptr [[RESP:%.*]], align 128, !tbaa [[TBAA6]]
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// CHECK-NEXT: ret void
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//
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void test_dmxvf16gerx2pp(unsigned char *vdmrp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
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__dmr1024 vdmr = *((__dmr1024 *)vdmrp);
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__vector_pair vp = *((__vector_pair *)vpp);
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__builtin_mma_dmxvf16gerx2pp(&vdmr, vp, vc);
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*((__dmr1024 *)resp) = vdmr;
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}
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// CHECK-LABEL: void @test_pmdmxvf16gerx2(
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: [[TMP0:%.*]] = load <256 x i1>, ptr [[VPP:%.*]], align 32, !tbaa [[TBAA2]]
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// CHECK-NEXT: [[TMP1:%.*]] = tail call <1024 x i1> @llvm.ppc.mma.pmdmxvf16gerx2(<256 x i1> [[TMP0]], <16 x i8> [[VC:%.*]], i32 0, i32 0, i32 0)
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// CHECK-NEXT: store <1024 x i1> [[TMP1]], ptr [[RESP:%.*]], align 128, !tbaa [[TBAA6]]
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// CHECK-NEXT: ret void
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//
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void test_pmdmxvf16gerx2(unsigned char *vdmrp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
238+
__dmr1024 vdmr = *((__dmr1024 *)vdmrp);
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__vector_pair vp = *((__vector_pair *)vpp);
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__builtin_mma_pmdmxvf16gerx2(&vdmr, vp, vc, 0, 0, 0);
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*((__dmr1024 *)resp) = vdmr;
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}
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// CHECK-LABEL: void @test_pmdmxvf16gerx2nn(
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP:%.*]], align 128, !tbaa [[TBAA6]]
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// CHECK-NEXT: [[TMP1:%.*]] = load <256 x i1>, ptr [[VPP:%.*]], align 32, !tbaa [[TBAA2]]
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// CHECK-NEXT: [[TMP2:%.*]] = tail call <1024 x i1> @llvm.ppc.mma.pmdmxvf16gerx2nn(<1024 x i1> [[TMP0]], <256 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], i32 0, i32 0, i32 0)
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// CHECK-NEXT: store <1024 x i1> [[TMP2]], ptr [[RESP:%.*]], align 128, !tbaa [[TBAA6]]
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// CHECK-NEXT: ret void
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//
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void test_pmdmxvf16gerx2nn(unsigned char *vdmrp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
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__dmr1024 vdmr = *((__dmr1024 *)vdmrp);
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__vector_pair vp = *((__vector_pair *)vpp);
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__builtin_mma_pmdmxvf16gerx2nn(&vdmr, vp, vc, 0, 0, 0);
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*((__dmr1024 *)resp) = vdmr;
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}
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// CHECK-LABEL: void @test_pmdmxvf16gerx2np(
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP:%.*]], align 128, !tbaa [[TBAA6]]
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// CHECK-NEXT: [[TMP1:%.*]] = load <256 x i1>, ptr [[VPP:%.*]], align 32, !tbaa [[TBAA2]]
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// CHECK-NEXT: [[TMP2:%.*]] = tail call <1024 x i1> @llvm.ppc.mma.pmdmxvf16gerx2np(<1024 x i1> [[TMP0]], <256 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], i32 0, i32 0, i32 0)
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// CHECK-NEXT: store <1024 x i1> [[TMP2]], ptr [[RESP:%.*]], align 128, !tbaa [[TBAA6]]
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// CHECK-NEXT: ret void
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//
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void test_pmdmxvf16gerx2np(unsigned char *vdmrp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
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__dmr1024 vdmr = *((__dmr1024 *)vdmrp);
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__vector_pair vp = *((__vector_pair *)vpp);
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__builtin_mma_pmdmxvf16gerx2np(&vdmr, vp, vc, 0, 0, 0);
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*((__dmr1024 *)resp) = vdmr;
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}
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// CHECK-LABEL: void @test_pmdmxvf16gerx2pn(
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP:%.*]], align 128, !tbaa [[TBAA6]]
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// CHECK-NEXT: [[TMP1:%.*]] = load <256 x i1>, ptr [[VPP:%.*]], align 32, !tbaa [[TBAA2]]
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// CHECK-NEXT: [[TMP2:%.*]] = tail call <1024 x i1> @llvm.ppc.mma.pmdmxvf16gerx2pn(<1024 x i1> [[TMP0]], <256 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], i32 0, i32 0, i32 0)
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// CHECK-NEXT: store <1024 x i1> [[TMP2]], ptr [[RESP:%.*]], align 128, !tbaa [[TBAA6]]
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// CHECK-NEXT: ret void
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//
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void test_pmdmxvf16gerx2pn(unsigned char *vdmrp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
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__dmr1024 vdmr = *((__dmr1024 *)vdmrp);
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__vector_pair vp = *((__vector_pair *)vpp);
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__builtin_mma_pmdmxvf16gerx2pn(&vdmr, vp, vc, 0, 0, 0);
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*((__dmr1024 *)resp) = vdmr;
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}
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// CHECK-LABEL: void @test_pmdmxvf16gerx2pp(
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP:%.*]], align 128, !tbaa [[TBAA6]]
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// CHECK-NEXT: [[TMP1:%.*]] = load <256 x i1>, ptr [[VPP:%.*]], align 32, !tbaa [[TBAA2]]
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// CHECK-NEXT: [[TMP2:%.*]] = tail call <1024 x i1> @llvm.ppc.mma.pmdmxvf16gerx2pp(<1024 x i1> [[TMP0]], <256 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], i32 0, i32 0, i32 0)
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// CHECK-NEXT: store <1024 x i1> [[TMP2]], ptr [[RESP:%.*]], align 128, !tbaa [[TBAA6]]
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// CHECK-NEXT: ret void
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//
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void test_pmdmxvf16gerx2pp(unsigned char *vdmrp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
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__dmr1024 vdmr = *((__dmr1024 *)vdmrp);
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__vector_pair vp = *((__vector_pair *)vpp);
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__builtin_mma_pmdmxvf16gerx2pp(&vdmr, vp, vc, 0, 0, 0);
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*((__dmr1024 *)resp) = vdmr;
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}
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// CHECK: [[TBAA2]] = !{[[META3:![0-9]+]], [[META3]], i64 0}
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// CHECK: [[META3]] = !{!"__vector_pair", [[META4:![0-9]+]], i64 0}
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// CHECK: [[META4]] = !{!"omnipotent char", [[META5:![0-9]+]], i64 0}
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// CHECK: [[META5]] = !{!"Simple C/C++ TBAA"}
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// CHECK: [[TBAA6]] = !{[[META7:![0-9]+]], [[META7]], i64 0}
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// CHECK: [[META7]] = !{!"__dmr1024", [[META4]], i64 0}

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