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Add XeVM to LLVMIR translation.
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‎mlir/include/mlir/Target/LLVMIR/Dialect/All.h

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@@ -28,6 +28,7 @@
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#include "mlir/Target/LLVMIR/Dialect/ROCDL/ROCDLToLLVMIRTranslation.h"
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#include "mlir/Target/LLVMIR/Dialect/SPIRV/SPIRVToLLVMIRTranslation.h"
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#include "mlir/Target/LLVMIR/Dialect/VCIX/VCIXToLLVMIRTranslation.h"
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#include "mlir/Target/LLVMIR/Dialect/XeVM/XeVMToLLVMIRTranslation.h"
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namespace mlir {
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class DialectRegistry;
@@ -47,6 +48,7 @@ static inline void registerAllToLLVMIRTranslations(DialectRegistry &registry) {
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registerROCDLDialectTranslation(registry);
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registerSPIRVDialectTranslation(registry);
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registerVCIXDialectTranslation(registry);
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registerXeVMDialectTranslation(registry);
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// Extension required for translating GPU offloading Ops.
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gpu::registerOffloadingLLVMTranslationInterfaceExternalModels(registry);
@@ -63,6 +65,7 @@ registerAllGPUToLLVMIRTranslations(DialectRegistry &registry) {
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registerNVVMDialectTranslation(registry);
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registerROCDLDialectTranslation(registry);
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registerSPIRVDialectTranslation(registry);
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registerXeVMDialectTranslation(registry);
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// Extension required for translating GPU offloading Ops.
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gpu::registerOffloadingLLVMTranslationInterfaceExternalModels(registry);

‎mlir/include/mlir/Target/LLVMIR/Dialect/XeVM/XeVMToLLVMIRTranslation.h

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//===-- XeVMToLLVMIRTranslation.h - XeVM to LLVM IR -------------*- C++ -*-===//
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//
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// This file is licensed under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This provides registration calls for XeVM dialect to LLVM IR translation.
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//
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//===----------------------------------------------------------------------===//
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#ifndef MLIR_TARGET_LLVMIR_DIALECT_XEVM_XEVMTOLLVMIRTRANSLATION_H
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#define MLIR_TARGET_LLVMIR_DIALECT_XEVM_XEVMTOLLVMIRTRANSLATION_H
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namespace mlir {
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class DialectRegistry;
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class MLIRContext;
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/// Register the XeVM dialect and the translation from it to the LLVM IR in the
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/// given registry;
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void registerXeVMDialectTranslation(mlir::DialectRegistry &registry);
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/// Register the XeVM dialect and the translation from it in the registry
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/// associated with the given context.
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void registerXeVMDialectTranslation(mlir::MLIRContext &context);
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} // namespace mlir
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#endif // MLIR_TARGET_LLVMIR_DIALECT_XEVM_XEVMTOLLVMIRTRANSLATION_H

‎mlir/lib/Target/LLVMIR/CMakeLists.txt

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@@ -60,6 +60,7 @@ add_mlir_translation_library(MLIRToLLVMIRTranslationRegistration
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MLIRROCDLToLLVMIRTranslation
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MLIRSPIRVToLLVMIRTranslation
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MLIRVCIXToLLVMIRTranslation
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MLIRXeVMToLLVMIRTranslation
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)
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add_mlir_translation_library(MLIRTargetLLVMIRImport

‎mlir/lib/Target/LLVMIR/Dialect/CMakeLists.txt

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@@ -10,3 +10,4 @@ add_subdirectory(OpenMP)
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add_subdirectory(ROCDL)
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add_subdirectory(SPIRV)
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add_subdirectory(VCIX)
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add_subdirectory(XeVM)

‎mlir/lib/Target/LLVMIR/Dialect/XeVM/CMakeLists.txt

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set(LLVM_OPTIONAL_SOURCES
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XeVMToLLVMIRTranslation.cpp
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)
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add_mlir_translation_library(MLIRXeVMToLLVMIRTranslation
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XeVMToLLVMIRTranslation.cpp
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DEPENDS
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MLIRXeVMConversionsIncGen
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LINK_COMPONENTS
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Core
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LINK_LIBS PUBLIC
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MLIRDialectUtils
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MLIRIR
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MLIRLLVMDialect
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MLIRXeVMDialect
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MLIRSupport
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MLIRTargetLLVMIRExport
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)

‎mlir/lib/Target/LLVMIR/Dialect/XeVM/XeVMToLLVMIRTranslation.cpp

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//===-- XeVMToLLVMIRTranslation.cpp - Translate XeVM to LLVM IR -*- C++ -*-===//
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//
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// This file is licensed under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements a translation between the MLIR XeVM dialect and
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// LLVM IR.
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//
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//===----------------------------------------------------------------------===//
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#include "mlir/Target/LLVMIR/Dialect/XeVM/XeVMToLLVMIRTranslation.h"
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#include "mlir/Dialect/LLVMIR/XeVMDialect.h"
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#include "mlir/IR/BuiltinAttributes.h"
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#include "mlir/IR/Operation.h"
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#include "mlir/Target/LLVMIR/ModuleTranslation.h"
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#include "llvm/ADT/TypeSwitch.h"
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#include "llvm/IR/Constants.h"
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#include "llvm/IR/LLVMContext.h"
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#include "llvm/IR/Metadata.h"
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#include "llvm/IR/ConstantRange.h"
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#include "llvm/IR/IRBuilder.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace mlir;
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using namespace mlir::LLVM;
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namespace {
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/// Implementation of the dialect interface that converts operations belonging
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/// to the XeVM dialect to LLVM IR.
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class XeVMDialectLLVMIRTranslationInterface
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: public LLVMTranslationDialectInterface {
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public:
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using LLVMTranslationDialectInterface::LLVMTranslationDialectInterface;
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/// Attaches module-level metadata for functions marked as kernels.
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LogicalResult
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amendOperation(Operation *op, ArrayRef<llvm::Instruction *> instructions,
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NamedAttribute attribute,
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LLVM::ModuleTranslation &moduleTranslation) const final {
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StringRef attrName = attribute.getName().getValue();
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if (attrName == mlir::xevm::XeVMDialect::getCacheControlsAttrName()) {
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auto cacheControlsArray = dyn_cast<ArrayAttr>(attribute.getValue());
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if (cacheControlsArray.size() != 2) {
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return op->emitOpError(
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"Expected both L1 and L3 cache control attributes!");
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}
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if (instructions.size() != 1) {
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return op->emitOpError("Expecting a single instruction");
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}
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return handleDecorationCacheControl(instructions.front(),
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cacheControlsArray.getValue());
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}
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auto func = dyn_cast<LLVM::LLVMFuncOp>(op);
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if (!func)
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return failure();
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return success();
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}
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private:
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template <typename IntTy>
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static llvm::Metadata *getConstantIntMD(llvm::Type *type, IntTy val) {
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return llvm::ConstantAsMetadata::get(llvm::ConstantInt::get(type, val));
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}
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static LogicalResult handleDecorationCacheControl(llvm::Instruction *inst,
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ArrayRef<Attribute> attrs) {
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SmallVector<llvm::Metadata *> decorations;
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llvm::LLVMContext &ctx = inst->getContext();
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llvm::Type *i32Ty = llvm::IntegerType::getInt32Ty(ctx);
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llvm::transform(
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attrs, std::back_inserter(decorations),
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[&ctx, i32Ty](Attribute attr) -> llvm::Metadata * {
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auto valuesArray = dyn_cast<ArrayAttr>(attr).getValue();
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std::array<llvm::Metadata *, 4> metadata;
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llvm::transform(
82+
valuesArray, metadata.begin(), [i32Ty](Attribute valueAttr) {
83+
return llvm::ConstantAsMetadata::get(llvm::ConstantInt::get(
84+
i32Ty, cast<IntegerAttr>(valueAttr).getValue()));
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});
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return llvm::MDNode::get(ctx, metadata);
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});
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constexpr llvm::StringLiteral decorationCacheControlMDName =
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"spirv.DecorationCacheControlINTEL";
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inst->setMetadata(decorationCacheControlMDName,
91+
llvm::MDNode::get(ctx, decorations));
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return success();
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}
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};
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} // namespace
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void ::mlir::registerXeVMDialectTranslation(::mlir::DialectRegistry &registry) {
98+
registry.insert<xevm::XeVMDialect>();
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registry.addExtension(+[](MLIRContext *ctx, xevm::XeVMDialect *dialect) {
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dialect->addInterfaces<XeVMDialectLLVMIRTranslationInterface>();
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});
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}
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void ::mlir::registerXeVMDialectTranslation(::mlir::MLIRContext &context) {
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DialectRegistry registry;
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registerXeVMDialectTranslation(registry);
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context.appendDialectRegistry(registry);
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}

‎mlir/test/Target/LLVMIR/xevm.mlir

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// RUN: mlir-translate --split-input-file -mlir-to-llvmir %s | FileCheck %s
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module {
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llvm.func spir_funccc @_Z41intel_sub_group_2d_block_read_16b_8r16x1cPU3AS1viiiDv2_iPt(!llvm.ptr<1> {llvm.nonnull, llvm.readonly}, i32, i32, i32, vector<2xi32>, !llvm.ptr {llvm.nonnull, llvm.writeonly}) attributes {no_unwind, will_return}
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llvm.func @blockload2d_cache_control(%arg0: !llvm.ptr<1>, %arg1: i32, %arg2: i32, %arg3: i32, %arg4: i32, %arg5: i32) -> vector<8xi16> {
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%0 = llvm.mlir.undef : vector<2xi32>
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%1 = llvm.mlir.constant(0 : i32) : i32
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%2 = llvm.mlir.constant(1 : i32) : i32
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%3 = llvm.insertelement %arg4, %0[%1 : i32] : vector<2xi32>
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%4 = llvm.insertelement %arg5, %3[%2 : i32] : vector<2xi32>
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%5 = llvm.mlir.constant(8 : i32) : i32
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%6 = llvm.alloca %5 x i16 : (i32) -> !llvm.ptr
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// CHECK-LABEL: call spir_func void @_Z41intel_sub_group_2d_block_read_16b_8r16x1cPU3AS1viiiDv2_iPt
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// CHECK-SAME: !spirv.DecorationCacheControlINTEL ![[DECO1:.*]]
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llvm.call spir_funccc @_Z41intel_sub_group_2d_block_read_16b_8r16x1cPU3AS1viiiDv2_iPt(%arg0, %arg1, %arg2, %arg3, %4, %6)
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{function_type = !llvm.func<void (ptr<1>, i32, i32, i32, vector<2xi32>, ptr)>, linkage = #llvm.linkage<external>, no_unwind,
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sym_name = "_Z41intel_sub_group_2d_block_read_16b_8r16x1cPU3AS1viiiDv2_iPt", visibility_ = 0 : i64, will_return,
18+
xevm.DecorationCacheControl = [[6442 : i32, 0 : i32, 1 : i32, 0 : i32], [6442 : i32, 1 : i32, 1 : i32, 0 : i32]]}
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: (!llvm.ptr<1> {llvm.nonnull, llvm.readonly}, i32, i32, i32, vector<2xi32>, !llvm.ptr {llvm.nonnull, llvm.writeonly}) -> ()
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%7 = llvm.load %6 : !llvm.ptr -> vector<8xi16>
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llvm.return %7 : vector<8xi16>
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}
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}
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// CHECK: ![[DECO1]] = !{![[DECO2:.*]], ![[DECO3:.*]]}
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// CHECK: ![[DECO2]] = !{i32 6442, i32 0, i32 1, i32 0}
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// CHECK: ![[DECO3]] = !{i32 6442, i32 1, i32 1, i32 0}
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// -----
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module {
31+
llvm.func spir_funccc @_Z42intel_sub_group_2d_block_write_32b_8r16x1cPU3AS1viiiDv2_iPj(!llvm.ptr<1> {llvm.nonnull, llvm.writeonly}, i32, i32, i32, vector<2xi32>, !llvm.ptr {llvm.nonnull, llvm.readonly}) attributes {no_unwind, will_return}
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llvm.func @blockstore2d_cache_control(%arg0: !llvm.ptr<1>, %arg1: i32, %arg2: i32, %arg3: i32, %arg4: i32, %arg5: i32, %arg6: vector<8xi32>) {
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%0 = llvm.mlir.undef : vector<2xi32>
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%1 = llvm.mlir.constant(0 : i32) : i32
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%2 = llvm.mlir.constant(1 : i32) : i32
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%3 = llvm.insertelement %arg4, %0[%1 : i32] : vector<2xi32>
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%4 = llvm.insertelement %arg5, %3[%2 : i32] : vector<2xi32>
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%5 = llvm.mlir.constant(8 : i32) : i32
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%6 = llvm.alloca %5 x i32 : (i32) -> !llvm.ptr
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llvm.store %arg6, %6 : vector<8xi32>, !llvm.ptr
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// CHECK-LABEL: call spir_func void @_Z42intel_sub_group_2d_block_write_32b_8r16x1cPU3AS1viiiDv2_iPj
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// CHECK-SAME: !spirv.DecorationCacheControlINTEL ![[DECO1:.*]]
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llvm.call spir_funccc @_Z42intel_sub_group_2d_block_write_32b_8r16x1cPU3AS1viiiDv2_iPj(%arg0, %arg1, %arg2, %arg3, %4, %6)
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{function_type = !llvm.func<void (ptr<1>, i32, i32, i32, vector<2xi32>, ptr)>, linkage = #llvm.linkage<external>, no_unwind,
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sym_name = "_Z42intel_sub_group_2d_block_write_32b_8r16x1cPU3AS1viiiDv2_iPj", visibility_ = 0 : i64, will_return,
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xevm.DecorationCacheControl = [[6443 : i32, 0 : i32, 2 : i32, 0 : i32], [6443 : i32, 1 : i32, 2 : i32, 0 : i32]]}
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: (!llvm.ptr<1> {llvm.nonnull, llvm.writeonly}, i32, i32, i32, vector<2xi32>, !llvm.ptr {llvm.nonnull, llvm.readonly}) -> ()
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llvm.return
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}
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}
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// CHECK: ![[DECO1]] = !{![[DECO2:.*]], ![[DECO3:.*]]}
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// CHECK: ![[DECO2]] = !{i32 6443, i32 0, i32 2, i32 0}
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// CHECK: ![[DECO3]] = !{i32 6443, i32 1, i32 2, i32 0}
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// -----
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module {
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llvm.func spir_funccc @_Z44intel_sub_group_2d_block_prefetch_8b_8r32x1cPU3AS1viiiDv2_i(!llvm.ptr<1> {llvm.nonnull}, i32, i32, i32, vector<2xi32>) attributes {memory_effects = #llvm.memory_effects<other = none, argMem = read, inaccessibleMem = none>, no_unwind}
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llvm.func @blockprefetch2d(%arg0: !llvm.ptr<1>, %arg1: i32, %arg2: i32, %arg3: i32, %arg4: i32, %arg5: i32) {
60+
%0 = llvm.mlir.undef : vector<2xi32>
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%1 = llvm.mlir.constant(0 : i32) : i32
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%2 = llvm.mlir.constant(1 : i32) : i32
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%3 = llvm.insertelement %arg4, %0[%1 : i32] : vector<2xi32>
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%4 = llvm.insertelement %arg5, %3[%2 : i32] : vector<2xi32>
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// CHECK-LABEL: call spir_func void @_Z44intel_sub_group_2d_block_prefetch_8b_8r32x1cPU3AS1viiiDv2_i
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// CHECK-SAME: !spirv.DecorationCacheControlINTEL ![[DECO1:.*]]
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llvm.call spir_funccc @_Z44intel_sub_group_2d_block_prefetch_8b_8r32x1cPU3AS1viiiDv2_i(%arg0, %arg1, %arg2, %arg3, %4)
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{function_type = !llvm.func<void (ptr<1>, i32, i32, i32, vector<2xi32>)>, linkage = #llvm.linkage<external>,
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memory_effects = #llvm.memory_effects<other = none, argMem = read, inaccessibleMem = none>, no_unwind,
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sym_name = "_Z44intel_sub_group_2d_block_prefetch_8b_8r32x1cPU3AS1viiiDv2_i", visibility_ = 0 : i64,
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xevm.DecorationCacheControl = [[6442 : i32, 0 : i32, 1 : i32, 0 : i32], [6442 : i32, 1 : i32, 1 : i32, 0 : i32]]}
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: (!llvm.ptr<1> {llvm.nonnull}, i32, i32, i32, vector<2xi32>) -> ()
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llvm.return
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}
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}
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// CHECK: ![[DECO1]] = !{![[DECO2:.*]], ![[DECO3:.*]]}
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// CHECK: ![[DECO2]] = !{i32 6442, i32 0, i32 1, i32 0}
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// CHECK: ![[DECO3]] = !{i32 6442, i32 1, i32 1, i32 0}
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// -----
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module {
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llvm.func spir_funccc @_Z8prefetchPU3AS1Kcm(!llvm.ptr<1>, i64) attributes {memory_effects = #llvm.memory_effects<other = none, argMem = read, inaccessibleMem = none>, no_unwind}
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llvm.func @prefetch(%arg0: !llvm.ptr<1>) {
85+
%0 = llvm.mlir.constant(1 : i64) : i64
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// CHECK-LABEL: call spir_func void @_Z8prefetchPU3AS1Kcm
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// CHECK-SAME: !spirv.DecorationCacheControlINTEL ![[DECO1:.*]]
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llvm.call spir_funccc @_Z8prefetchPU3AS1Kcm(%arg0, %0)
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{function_type = !llvm.func<void (ptr<1>, i64)>, linkage = #llvm.linkage<external>,
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memory_effects = #llvm.memory_effects<other = none, argMem = read, inaccessibleMem = none>,
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no_unwind, sym_name = "_Z8prefetchPU3AS1Kcm", visibility_ = 0 : i64,
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xevm.DecorationCacheControl = [[6442 : i32, 0 : i32, 1 : i32, 0 : i32], [6442 : i32, 1 : i32, 1 : i32, 0 : i32]]}
93+
: (!llvm.ptr<1>, i64) -> ()
94+
llvm.return
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}
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}
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// CHECK: ![[DECO1]] = !{![[DECO2:.*]], ![[DECO3:.*]]}
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// CHECK: ![[DECO2]] = !{i32 6442, i32 0, i32 1, i32 0}
100+
// CHECK: ![[DECO3]] = !{i32 6442, i32 1, i32 1, i32 0}
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