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[TableGen] Use ListSeparator to handle joining condition checks in CompressInstEmitter. NFC (#151089)
This avoids needing to remove the leading indentation and trailing ' &&\n' when we are done with all conditions. While there remove a few extra parentheses and fix a case where 6 spaces of indentation was used instead of 8.
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‎llvm/utils/TableGen/CompressInstEmitter.cpp

Lines changed: 47 additions & 57 deletions
Original file line numberDiff line numberDiff line change
@@ -566,8 +566,6 @@ static void printPredicates(ArrayRef<const Record *> Predicates, StringRef Name,
566566

567567
static void mergeCondAndCode(raw_ostream &CombinedStream, StringRef CondStr,
568568
StringRef CodeStr) {
569-
// Remove first indentation and last '&&'.
570-
CondStr = CondStr.drop_front(8).drop_back(4);
571569
CombinedStream.indent(4) << "if (" << CondStr << ") {\n";
572570
CombinedStream << CodeStr;
573571
CombinedStream.indent(4) << " return true;\n";
@@ -704,17 +702,18 @@ void CompressInstEmitter::emitCompressInstEmitter(raw_ostream &OS,
704702
});
705703
getReqFeatures(FeaturesSet, AnyOfFeatureSets, ReqFeatures);
706704

705+
ListSeparator CondSep(" &&\n ");
706+
707707
// Emit checks for all required features.
708708
for (auto &Op : FeaturesSet) {
709709
StringRef Not = Op.first ? "!" : "";
710-
CondStream.indent(8) << Not << "STI.getFeatureBits()[" << TargetName
711-
<< "::" << Op.second << "]"
712-
<< " &&\n";
710+
CondStream << CondSep << Not << "STI.getFeatureBits()[" << TargetName
711+
<< "::" << Op.second << "]";
713712
}
714713

715714
// Emit checks for all required feature groups.
716715
for (auto &Set : AnyOfFeatureSets) {
717-
CondStream.indent(8) << "(";
716+
CondStream << CondSep << "(";
718717
for (auto &Op : Set) {
719718
bool IsLast = &Op == &*Set.rbegin();
720719
StringRef Not = Op.first ? "!" : "";
@@ -723,7 +722,7 @@ void CompressInstEmitter::emitCompressInstEmitter(raw_ostream &OS,
723722
if (!IsLast)
724723
CondStream << " || ";
725724
}
726-
CondStream << ") &&\n";
725+
CondStream << ")";
727726
}
728727

729728
// Start Source Inst operands validation.
@@ -735,32 +734,31 @@ void CompressInstEmitter::emitCompressInstEmitter(raw_ostream &OS,
735734
case OpData::Operand:
736735
if (SourceOperandMap[OpNo].OpInfo.TiedOpIdx != -1) {
737736
if (Source.Operands[OpNo].Rec->isSubClassOf("RegisterClass"))
738-
CondStream.indent(8) << "(MI.getOperand(" << OpNo
739-
<< ").isReg()) && (MI.getOperand("
740-
<< SourceOperandMap[OpNo].OpInfo.TiedOpIdx
741-
<< ").isReg()) &&\n"
742-
<< indent(8) << "(MI.getOperand(" << OpNo
743-
<< ").getReg() == MI.getOperand("
744-
<< SourceOperandMap[OpNo].OpInfo.TiedOpIdx
745-
<< ").getReg()) &&\n";
737+
CondStream << CondSep << "MI.getOperand(" << OpNo
738+
<< ").isReg() && MI.getOperand("
739+
<< SourceOperandMap[OpNo].OpInfo.TiedOpIdx
740+
<< ").isReg()" << CondSep << "(MI.getOperand(" << OpNo
741+
<< ").getReg() == MI.getOperand("
742+
<< SourceOperandMap[OpNo].OpInfo.TiedOpIdx
743+
<< ").getReg())";
746744
else
747745
PrintFatalError("Unexpected tied operand types!");
748746
}
749747

750748
// We don't need to do anything for source instruction operand checks.
751749
break;
752750
case OpData::Imm:
753-
CondStream.indent(8)
754-
<< "(MI.getOperand(" << OpNo << ").isImm()) &&\n"
755-
<< " (MI.getOperand(" << OpNo
756-
<< ").getImm() == " << SourceOperandMap[OpNo].ImmVal << ") &&\n";
751+
CondStream << CondSep << "MI.getOperand(" << OpNo << ").isImm()"
752+
<< CondSep << "(MI.getOperand(" << OpNo
753+
<< ").getImm() == " << SourceOperandMap[OpNo].ImmVal
754+
<< ")";
757755
break;
758756
case OpData::Reg: {
759757
const Record *Reg = SourceOperandMap[OpNo].RegRec;
760-
CondStream.indent(8) << "(MI.getOperand(" << OpNo << ").isReg()) &&\n"
761-
<< indent(8) << "(MI.getOperand(" << OpNo
762-
<< ").getReg() == " << TargetName
763-
<< "::" << Reg->getName() << ") &&\n";
758+
CondStream << CondSep << "MI.getOperand(" << OpNo << ").isReg()"
759+
<< CondSep << "(MI.getOperand(" << OpNo
760+
<< ").getReg() == " << TargetName << "::" << Reg->getName()
761+
<< ")";
764762
break;
765763
}
766764
}
@@ -797,15 +795,14 @@ void CompressInstEmitter::emitCompressInstEmitter(raw_ostream &OS,
797795
// Don't check register class if this is a tied operand, it was done
798796
// for the operand it's tied to.
799797
if (DestOperand.getTiedRegister() == -1) {
800-
CondStream.indent(8) << "MI.getOperand(" << OpIdx << ").isReg()";
798+
CondStream << CondSep << "MI.getOperand(" << OpIdx << ").isReg()";
801799
if (EType == EmitterType::CheckCompress)
802800
CondStream << " && MI.getOperand(" << OpIdx
803801
<< ").getReg().isPhysical()";
804-
CondStream << " &&\n"
805-
<< indent(8) << TargetName << "MCRegisterClasses["
802+
CondStream << CondSep << TargetName << "MCRegisterClasses["
806803
<< TargetName << "::" << ClassRec->getName()
807804
<< "RegClassID].contains(MI.getOperand(" << OpIdx
808-
<< ").getReg()) &&\n";
805+
<< ").getReg())";
809806
}
810807

811808
if (CompressOrUncompress)
@@ -816,38 +813,33 @@ void CompressInstEmitter::emitCompressInstEmitter(raw_ostream &OS,
816813
if (CompressOrUncompress) {
817814
unsigned Entry = getPredicates(MCOpPredicateMap, MCOpPredicates,
818815
DagRec, "MCOperandPredicate");
819-
CondStream.indent(8)
820-
<< ValidatorName << "("
821-
<< "MI.getOperand(" << OpIdx << "), STI, " << Entry << " /* "
822-
<< DagRec->getName() << " */) &&\n";
816+
CondStream << CondSep << ValidatorName << "("
817+
<< "MI.getOperand(" << OpIdx << "), STI, " << Entry
818+
<< " /* " << DagRec->getName() << " */)";
823819
// Also check DestRec if different than DagRec.
824820
if (DagRec != DestRec) {
825821
Entry = getPredicates(MCOpPredicateMap, MCOpPredicates, DestRec,
826822
"MCOperandPredicate");
827-
CondStream.indent(8)
828-
<< ValidatorName << "("
829-
<< "MI.getOperand(" << OpIdx << "), STI, " << Entry
830-
<< " /* " << DestRec->getName() << " */) &&\n";
823+
CondStream << CondSep << ValidatorName << "("
824+
<< "MI.getOperand(" << OpIdx << "), STI, " << Entry
825+
<< " /* " << DestRec->getName() << " */)";
831826
}
832827
} else {
833828
unsigned Entry =
834829
getPredicates(ImmLeafPredicateMap, ImmLeafPredicates, DagRec,
835830
"ImmediateCode");
836-
CondStream.indent(8)
837-
<< "MI.getOperand(" << OpIdx << ").isImm() &&\n";
838-
CondStream.indent(8)
839-
<< TargetName << "ValidateMachineOperand("
840-
<< "MI.getOperand(" << OpIdx << "), &STI, " << Entry << " /* "
841-
<< DagRec->getName() << " */) &&\n";
831+
CondStream << CondSep << "MI.getOperand(" << OpIdx << ").isImm()";
832+
CondStream << CondSep << TargetName << "ValidateMachineOperand("
833+
<< "MI.getOperand(" << OpIdx << "), &STI, " << Entry
834+
<< " /* " << DagRec->getName() << " */)";
842835
if (DagRec != DestRec) {
843836
Entry = getPredicates(ImmLeafPredicateMap, ImmLeafPredicates,
844837
DestRec, "ImmediateCode");
845-
CondStream.indent(8)
846-
<< "MI.getOperand(" << OpIdx << ").isImm() &&\n";
847-
CondStream.indent(8)
848-
<< TargetName << "ValidateMachineOperand("
849-
<< "MI.getOperand(" << OpIdx << "), &STI, " << Entry
850-
<< " /* " << DestRec->getName() << " */) &&\n";
838+
CondStream << CondSep << "MI.getOperand(" << OpIdx
839+
<< ").isImm()";
840+
CondStream << CondSep << TargetName << "ValidateMachineOperand("
841+
<< "MI.getOperand(" << OpIdx << "), &STI, " << Entry
842+
<< " /* " << DestRec->getName() << " */)";
851843
}
852844
}
853845
if (CompressOrUncompress)
@@ -860,20 +852,18 @@ void CompressInstEmitter::emitCompressInstEmitter(raw_ostream &OS,
860852
if (CompressOrUncompress) {
861853
unsigned Entry = getPredicates(MCOpPredicateMap, MCOpPredicates,
862854
DestRec, "MCOperandPredicate");
863-
CondStream.indent(8)
864-
<< ValidatorName << "("
865-
<< "MCOperand::createImm(" << DestOperandMap[OpNo].ImmVal
866-
<< "), STI, " << Entry << " /* " << DestRec->getName()
867-
<< " */) &&\n";
855+
CondStream << CondSep << ValidatorName << "("
856+
<< "MCOperand::createImm(" << DestOperandMap[OpNo].ImmVal
857+
<< "), STI, " << Entry << " /* " << DestRec->getName()
858+
<< " */)";
868859
} else {
869860
unsigned Entry =
870861
getPredicates(ImmLeafPredicateMap, ImmLeafPredicates, DestRec,
871862
"ImmediateCode");
872-
CondStream.indent(8)
873-
<< TargetName
874-
<< "ValidateMachineOperand(MachineOperand::CreateImm("
875-
<< DestOperandMap[OpNo].ImmVal << "), &STI, " << Entry << " /* "
876-
<< DestRec->getName() << " */) &&\n";
863+
CondStream << CondSep << TargetName
864+
<< "ValidateMachineOperand(MachineOperand::CreateImm("
865+
<< DestOperandMap[OpNo].ImmVal << "), &STI, " << Entry
866+
<< " /* " << DestRec->getName() << " */)";
877867
}
878868
if (CompressOrUncompress)
879869
CodeStream.indent(6) << "OutInst.addOperand(MCOperand::createImm("

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