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Removing Redundant Instructions
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2 files changed

+150
-285
lines changed

2 files changed

+150
-285
lines changed

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

Lines changed: 1 addition & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -5211,10 +5211,6 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI,
52115211
MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
52125212
Register DestSub1 =
52135213
MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
5214-
Register Op1H_Op0L_Reg =
5215-
MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
5216-
Register CarryReg =
5217-
MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
52185214

52195215
const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
52205216
const TargetRegisterClass *SrcSubRC =
@@ -5229,19 +5225,10 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI,
52295225
.add(Op1L)
52305226
.addReg(ParityRegister);
52315227

5232-
BuildMI(BB, MI, DL, TII->get(AMDGPU::S_MUL_I32), Op1H_Op0L_Reg)
5228+
BuildMI(BB, MI, DL, TII->get(AMDGPU::S_MUL_I32), DestSub1)
52335229
.add(Op1H)
52345230
.addReg(ParityRegister);
52355231

5236-
BuildMI(BB, MI, DL, TII->get(AMDGPU::S_MUL_HI_U32), CarryReg)
5237-
.add(Op1L)
5238-
.addReg(ParityRegister);
5239-
5240-
BuildMI(BB, MI, DL, TII->get(AMDGPU::S_ADD_U32), DestSub1)
5241-
.addReg(CarryReg)
5242-
.addReg(Op1H_Op0L_Reg)
5243-
.setOperandDead(3); // Dead scc
5244-
52455232
BuildMI(BB, MI, DL, TII->get(TargetOpcode::REG_SEQUENCE), DstReg)
52465233
.addReg(DestSub0)
52475234
.addImm(AMDGPU::sub0)

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