@@ -5211,10 +5211,6 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI,
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MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
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Register DestSub1 =
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MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
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- Register Op1H_Op0L_Reg =
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- MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
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- Register CarryReg =
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- MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
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const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
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const TargetRegisterClass *SrcSubRC =
@@ -5229,19 +5225,10 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI,
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.add(Op1L)
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.addReg(ParityRegister);
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- BuildMI(BB, MI, DL, TII->get(AMDGPU::S_MUL_I32), Op1H_Op0L_Reg )
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+ BuildMI(BB, MI, DL, TII->get(AMDGPU::S_MUL_I32), DestSub1 )
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.add(Op1H)
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.addReg(ParityRegister);
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- BuildMI(BB, MI, DL, TII->get(AMDGPU::S_MUL_HI_U32), CarryReg)
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- .add(Op1L)
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- .addReg(ParityRegister);
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-
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- BuildMI(BB, MI, DL, TII->get(AMDGPU::S_ADD_U32), DestSub1)
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- .addReg(CarryReg)
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- .addReg(Op1H_Op0L_Reg)
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- .setOperandDead(3); // Dead scc
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-
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BuildMI(BB, MI, DL, TII->get(TargetOpcode::REG_SEQUENCE), DstReg)
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.addReg(DestSub0)
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.addImm(AMDGPU::sub0)
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