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[Test] Add and update tests for lrint
A number of backends are missing either all tests for lrint, or specifically those for f16 which currently crashes for `softPromoteHalf` targets. For a number of popular backends, do the following: * Ensure f16, f32, f64, and f128 are all covered * Ensure both a 32- and 64-bit target are tested, if relevant * Add `nounwind` to clean up CFI output * Add a test covering the above if one did not exist
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16 files changed

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‎llvm/test/CodeGen/ARM/llrint-conv.ll

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@@ -1,6 +1,16 @@
11
; RUN: llc < %s -mtriple=arm-eabi -float-abi=soft | FileCheck %s --check-prefix=SOFTFP
22
; RUN: llc < %s -mtriple=arm-eabi -float-abi=hard | FileCheck %s --check-prefix=HARDFP
33

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; SOFTFP-LABEL: testmsxh_builtin:
5+
; SOFTFP: bl llrintf
6+
; HARDFP-LABEL: testmsxh_builtin:
7+
; HARDFP: bl llrintf
8+
define i64 @testmsxh_builtin(half %x) {
9+
entry:
10+
%0 = tail call i64 @llvm.llrint.f16(half %x)
11+
ret i64 %0
12+
}
13+
414
; SOFTFP-LABEL: testmsxs_builtin:
515
; SOFTFP: bl llrintf
616
; HARDFP-LABEL: testmsxs_builtin:
@@ -21,5 +31,16 @@ entry:
2131
ret i64 %0
2232
}
2333

34+
; FIXME(#44744): incorrect libcall
35+
; SOFTFP-LABEL: testmsxq_builtin:
36+
; SOFTFP: bl llrintl
37+
; HARDFP-LABEL: testmsxq_builtin:
38+
; HARDFP: bl llrintl
39+
define i64 @testmsxq_builtin(fp128 %x) {
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entry:
41+
%0 = tail call i64 @llvm.llrint.f128(fp128 %x)
42+
ret i64 %0
43+
}
44+
2445
declare i64 @llvm.llrint.f32(float) nounwind readnone
2546
declare i64 @llvm.llrint.f64(double) nounwind readnone

‎llvm/test/CodeGen/ARM/lrint-conv.ll

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@@ -1,6 +1,13 @@
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; RUN: llc < %s -mtriple=arm-eabi -float-abi=soft | FileCheck %s --check-prefix=SOFTFP
22
; RUN: llc < %s -mtriple=arm-eabi -float-abi=hard | FileCheck %s --check-prefix=HARDFP
33

4+
; FIXME: crash
5+
; define i32 @testmswh_builtin(half %x) {
6+
; entry:
7+
; %0 = tail call i32 @llvm.lrint.i32.f16(half %x)
8+
; ret i32 %0
9+
; }
10+
411
; SOFTFP-LABEL: testmsws_builtin:
512
; SOFTFP: bl lrintf
613
; HARDFP-LABEL: testmsws_builtin:
@@ -21,5 +28,16 @@ entry:
2128
ret i32 %0
2229
}
2330

31+
; FIXME(#44744): incorrect libcall
32+
; SOFTFP-LABEL: testmswq_builtin:
33+
; SOFTFP: bl lrintl
34+
; HARDFP-LABEL: testmswq_builtin:
35+
; HARDFP: bl lrintl
36+
define i32 @testmswq_builtin(fp128 %x) {
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entry:
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%0 = tail call i32 @llvm.lrint.i32.f128(fp128 %x)
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ret i32 %0
40+
}
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2442
declare i32 @llvm.lrint.i32.f32(float) nounwind readnone
2543
declare i32 @llvm.lrint.i32.f64(double) nounwind readnone

‎llvm/test/CodeGen/AVR/llrint.ll

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@@ -1,6 +1,13 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc < %s -mtriple=avr -mcpu=atmega328p | FileCheck %s
33

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; FIXME: crash
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; define i64 @testmsxh_builtin(half %x) {
6+
; entry:
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; %0 = tail call i64 @llvm.llrint.f16(half %x)
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; ret i64 %0
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; }
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411
define i64 @testmsxs_builtin(float %x) {
512
; CHECK-LABEL: testmsxs_builtin:
613
; CHECK: ; %bb.0: ; %entry
@@ -21,5 +28,16 @@ entry:
2128
ret i64 %0
2229
}
2330

31+
; FIXME(#44744): incorrect libcall
32+
define i64 @testmsxq_builtin(fp128 %x) {
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; CHECK-LABEL: testmsxq_builtin:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: call llrintl
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; CHECK-NEXT: ret
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entry:
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%0 = tail call i64 @llvm.llrint.fp128(fp128 %x)
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ret i64 %0
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}
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2442
declare i64 @llvm.llrint.f32(float) nounwind readnone
2543
declare i64 @llvm.llrint.f64(double) nounwind readnone

‎llvm/test/CodeGen/AVR/lrint.ll

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@@ -1,6 +1,13 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc < %s -mtriple=avr -mcpu=atmega328p | FileCheck %s
33

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; FIXME: crash
5+
; define i32 @testmswh_builtin(half %x) {
6+
; entry:
7+
; %0 = tail call i32 @llvm.lrint.i32.f16(half %x)
8+
; ret i32 %0
9+
; }
10+
411
define i32 @testmsws_builtin(float %x) {
512
; CHECK-LABEL: testmsws_builtin:
613
; CHECK: ; %bb.0: ; %entry
@@ -21,5 +28,16 @@ entry:
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ret i32 %0
2229
}
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; FIXME(#44744): incorrect libcall
32+
define i32 @testmswq_builtin(fp128 %x) {
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; CHECK-LABEL: testmswq_builtin:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: call lrint
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; CHECK-NEXT: ret
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entry:
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%0 = tail call i32 @llvm.lrint.i32.fp128(fp128 %x)
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ret i32 %0
40+
}
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2442
declare i32 @llvm.lrint.i32.f32(float) nounwind readnone
2543
declare i32 @llvm.lrint.i32.f64(double) nounwind readnone

‎llvm/test/CodeGen/LoongArch/lrint-conv.ll

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; Tests for lrint and llrint, with both i32 and i64 checked.
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; RUN: sed 's/ITy/i32/g' %s | llc -mtriple=loongarch32 | FileCheck %s --check-prefixes=LA32
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; RUN: sed 's/ITy/i64/g' %s | llc -mtriple=loongarch32 | FileCheck %s --check-prefixes=LA32
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; RUN: sed 's/ITy/i32/g' %s | llc -mtriple=loongarch64 | FileCheck %s --check-prefixes=LA64-I32
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; RUN: sed 's/ITy/i64/g' %s | llc -mtriple=loongarch64 | FileCheck %s --check-prefixes=LA64-I64
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; FIXME: crash
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; define ITy @test_lrint_ixx_f16(half %x) nounwind {
10+
; %res = tail call ITy @llvm.lrint.ITy.f16(half %x)
11+
; ret ITy %res
12+
; }
13+
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; define ITy @test_llrint_ixx_f16(half %x) nounwind {
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; %res = tail call ITy @llvm.llrint.ITy.f16(half %x)
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; ret ITy %res
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; }
18+
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define ITy @test_lrint_ixx_f32(float %x) nounwind {
20+
; LA32-LABEL: test_lrint_ixx_f32:
21+
; LA32: bl lrintf
22+
;
23+
; LA64-I32-LABEL: test_lrint_ixx_f32:
24+
; LA64-I32: pcaddu18i $ra, %call36(lrintf)
25+
;
26+
; LA64-I64-LABEL: test_lrint_ixx_f32:
27+
; LA64-I64: pcaddu18i $t8, %call36(lrintf)
28+
%res = tail call ITy @llvm.lrint.ITy.f32(float %x)
29+
ret ITy %res
30+
}
31+
32+
define ITy @test_llrint_ixx_f32(float %x) nounwind {
33+
; LA32-LABEL: test_llrint_ixx_f32:
34+
; LA32: bl llrintf
35+
;
36+
; LA64-I32-LABEL: test_llrint_ixx_f32:
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; LA64-I32: pcaddu18i $ra, %call36(llrintf)
38+
;
39+
; LA64-I64-LABEL: test_llrint_ixx_f32:
40+
; LA64-I64: pcaddu18i $t8, %call36(llrintf)
41+
%res = tail call ITy @llvm.llrint.ITy.f32(float %x)
42+
ret ITy %res
43+
}
44+
45+
define ITy @test_lrint_ixx_f64(double %x) nounwind {
46+
; LA32-LABEL: test_lrint_ixx_f64:
47+
; LA32: bl lrint
48+
;
49+
; LA64-I32-LABEL: test_lrint_ixx_f64:
50+
; LA64-I32: pcaddu18i $ra, %call36(lrint)
51+
;
52+
; LA64-I64-LABEL: test_lrint_ixx_f64:
53+
; LA64-I64: pcaddu18i $t8, %call36(lrint)
54+
%res = tail call ITy @llvm.lrint.ITy.f64(double %x)
55+
ret ITy %res
56+
}
57+
58+
define ITy @test_llrint_ixx_f64(double %x) nounwind {
59+
; LA32-LABEL: test_llrint_ixx_f64:
60+
; LA32: bl llrint
61+
;
62+
; LA64-I32-LABEL: test_llrint_ixx_f64:
63+
; LA64-I32: pcaddu18i $ra, %call36(llrint)
64+
;
65+
; LA64-I64-LABEL: test_llrint_ixx_f64:
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; LA64-I64: pcaddu18i $t8, %call36(llrint)
67+
%res = tail call ITy @llvm.llrint.ITy.f64(double %x)
68+
ret ITy %res
69+
}
70+
71+
define ITy @test_lrint_ixx_f128(fp128 %x) nounwind {
72+
; LA32-LABEL: test_lrint_ixx_f128:
73+
; LA32: bl lrintl
74+
;
75+
; LA64-I32-LABEL: test_lrint_ixx_f128:
76+
; LA64-I32: pcaddu18i $ra, %call36(lrintl)
77+
;
78+
; LA64-I64-LABEL: test_lrint_ixx_f128:
79+
; LA64-I64: pcaddu18i $ra, %call36(lrintl)
80+
%res = tail call ITy @llvm.lrint.ITy.f128(fp128 %x)
81+
ret ITy %res
82+
}
83+
84+
define ITy @test_llrint_ixx_f128(fp128 %x) nounwind {
85+
; LA32-LABEL: test_llrint_ixx_f128:
86+
; LA32: bl llrintl
87+
;
88+
; LA64-I32-LABEL: test_llrint_ixx_f128:
89+
; LA64-I32: pcaddu18i $ra, %call36(llrintl)
90+
;
91+
; LA64-I64-LABEL: test_llrint_ixx_f128:
92+
; LA64-I64: pcaddu18i $ra, %call36(llrintl)
93+
%res = tail call ITy @llvm.llrint.ITy.f128(fp128 %x)
94+
ret ITy %res
95+
}

‎llvm/test/CodeGen/MSP430/lrint-conv.ll

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@@ -0,0 +1,60 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2+
3+
; Tests for lrint and llrint, with both i32 and i64 checked.
4+
5+
; RUN: sed 's/ITy/i32/g' %s | llc -mtriple=msp430-unknown-unknown | FileCheck %s --check-prefixes=CHECK
6+
; RUN: sed 's/ITy/i64/g' %s | llc -mtriple=msp430-unknown-unknown | FileCheck %s --check-prefixes=CHECK
7+
8+
; FIXME: crash
9+
; define ITy @test_lrint_ixx_f16(half %x) nounwind {
10+
; %res = tail call ITy @llvm.lrint.ITy.f16(half %x)
11+
; ret ITy %res
12+
; }
13+
14+
; define ITy @test_llrint_ixx_f16(half %x) nounwind {
15+
; %res = tail call ITy @llvm.llrint.ITy.f16(half %x)
16+
; ret ITy %res
17+
; }
18+
19+
define ITy @test_lrint_ixx_f32(float %x) nounwind {
20+
; CHECK-LABEL: test_lrint_ixx_f32:
21+
; CHECK: call #lrintf
22+
%res = tail call ITy @llvm.lrint.ITy.f32(float %x)
23+
ret ITy %res
24+
}
25+
26+
define ITy @test_llrint_ixx_f32(float %x) nounwind {
27+
; CHECK-LABEL: test_llrint_ixx_f32:
28+
; CHECK: call #llrintf
29+
%res = tail call ITy @llvm.llrint.ITy.f32(float %x)
30+
ret ITy %res
31+
}
32+
33+
define ITy @test_lrint_ixx_f64(double %x) nounwind {
34+
; CHECK-LABEL: test_lrint_ixx_f64:
35+
; CHECK: call #lrint
36+
%res = tail call ITy @llvm.lrint.ITy.f64(double %x)
37+
ret ITy %res
38+
}
39+
40+
define ITy @test_llrint_ixx_f64(double %x) nounwind {
41+
; CHECK-LABEL: test_llrint_ixx_f64:
42+
; CHECK: call #llrint
43+
%res = tail call ITy @llvm.llrint.ITy.f64(double %x)
44+
ret ITy %res
45+
}
46+
47+
define ITy @test_lrint_ixx_f128(fp128 %x) nounwind {
48+
; CHECK-LABEL: test_lrint_ixx_f128:
49+
; CHECK: call #lrintl
50+
%res = tail call ITy @llvm.lrint.ITy.f128(fp128 %x)
51+
ret ITy %res
52+
}
53+
54+
; FIXME(#44744): incorrect libcall
55+
define ITy @test_llrint_ixx_f128(fp128 %x) nounwind {
56+
; CHECK-LABEL: test_llrint_ixx_f128:
57+
; CHECK: call #llrintl
58+
%res = tail call ITy @llvm.llrint.ITy.f128(fp128 %x)
59+
ret ITy %res
60+
}

‎llvm/test/CodeGen/Mips/llrint-conv.ll

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Original file line numberDiff line numberDiff line change
@@ -1,4 +1,19 @@
11
; RUN: llc < %s -mtriple=mips64el -mattr=+soft-float | FileCheck %s
2+
; RUN: llc < %s -mtriple=mips -mattr=+soft-float | FileCheck %s
3+
4+
; FIXME: crash
5+
; define signext i32 @testmswh(half %x) {
6+
; entry:
7+
; %0 = tail call i64 @llvm.llrint.f16(half %x)
8+
; %conv = trunc i64 %0 to i32
9+
; ret i32 %conv
10+
; }
11+
12+
; define i64 @testmsxh(half %x) {
13+
; entry:
14+
; %0 = tail call i64 @llvm.llrint.f16(half %x)
15+
; ret i64 %0
16+
; }
217

318
define signext i32 @testmsws(float %x) {
419
; CHECK-LABEL: testmsws:

‎llvm/test/CodeGen/Mips/lrint-conv.ll

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,19 @@
11
; RUN: llc < %s -mtriple=mips64el -mattr=+soft-float | FileCheck %s
2+
; RUN: llc < %s -mtriple=mips -mattr=+soft-float | FileCheck %s
3+
4+
; FIXME: crash
5+
; define signext i32 @testmswh(half %x) {
6+
; entry:
7+
; %0 = tail call i64 @llvm.lrint.i64.f16(half %x)
8+
; %conv = trunc i64 %0 to i32
9+
; ret i32 %conv
10+
; }
11+
12+
; define i64 @testmsxh(half %x) {
13+
; entry:
14+
; %0 = tail call i64 @llvm.lrint.i64.f16(half %x)
15+
; ret i64 %0
16+
; }
217

318
define signext i32 @testmsws(float %x) {
419
; CHECK-LABEL: testmsws:

‎llvm/test/CodeGen/PowerPC/llrint-conv.ll

Lines changed: 32 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,19 @@
11
; RUN: llc < %s -mtriple=powerpc64le | FileCheck %s
2+
; RUN: llc < %s -mtriple=powerpc | FileCheck %s
3+
4+
; FIXME: crash
5+
; define signext i32 @testmswh(half %x) {
6+
; entry:
7+
; %0 = tail call i64 @llvm.llrint.f16(half %x)
8+
; %conv = trunc i64 %0 to i32
9+
; ret i32 %conv
10+
; }
11+
12+
; define i64 @testmsxh(half %x) {
13+
; entry:
14+
; %0 = tail call i64 @llvm.llrint.f16(half %x)
15+
; ret i64 %0
16+
; }
217

318
; CHECK-LABEL: testmsws:
419
; CHECK: bl llrintf
@@ -51,6 +66,23 @@ entry:
5166
ret i64 %0
5267
}
5368

69+
; CHECK-LABEL: testmswq:
70+
; CHECK: bl llrintf128
71+
define signext i32 @testmswq(fp128 %x) {
72+
entry:
73+
%0 = tail call i64 @llvm.llrint.f128(fp128 %x)
74+
%conv = trunc i64 %0 to i32
75+
ret i32 %conv
76+
}
77+
78+
; CHECK-LABEL: testmslq:
79+
; CHECK: bl llrintf128
80+
define i64 @testmslq(fp128 %x) {
81+
entry:
82+
%0 = tail call i64 @llvm.llrint.f128(fp128 %x)
83+
ret i64 %0
84+
}
85+
5486
declare i64 @llvm.llrint.f32(float) nounwind readnone
5587
declare i64 @llvm.llrint.f64(double) nounwind readnone
5688
declare i64 @llvm.llrint.ppcf128(ppc_fp128) nounwind readnone

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