fix comment

mjulian31 · mjulian31 · commit f4c6d311dabd · 2025-07-18T17:06:44.000-07:00
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
@@ -953,7 +953,7 @@ NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM,
        {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FTANH}) {
     setOperationAction(Op, MVT::f16, Promote);
     setOperationAction(Op, MVT::f32, Legal);
-    // fsin, fcos, and ftanh are not supported on f64
+    // only div/rem/sqrt are legal for f64
     if (Op == ISD::FDIV || Op == ISD::FREM || Op == ISD::FSQRT) {
       setOperationAction(Op, MVT::f64, Legal);
     }

Original file line number	Diff line number	Diff line change
`@@ -953,7 +953,7 @@ NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM,`
`953`	`953`	`{ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FTANH}) {`
`954`	`954`	`setOperationAction(Op, MVT::f16, Promote);`
`955`	`955`	`setOperationAction(Op, MVT::f32, Legal);`
`956`		`- // fsin, fcos, and ftanh are not supported on f64`
	`956`	`+ // only div/rem/sqrt are legal for f64`
`957`	`957`	`if (Op == ISD::FDIV \|\| Op == ISD::FREM \|\| Op == ISD::FSQRT) {`
`958`	`958`	`setOperationAction(Op, MVT::f64, Legal);`
`959`	`959`	`}`