fixes moved from #91854

Author: klensy

llvm/test/Analysis/CostModel/AArch64/sve-shuffle-broadcast.ll

@@ -31,7 +31,7 @@ define void  @broadcast() #0{
 ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction:   %22 = shufflevector <vscale x 8 x i1> undef, <vscale x 8 x i1> undef, <vscale x 8 x i32> zeroinitializer
 ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction:   %23 = shufflevector <vscale x 4 x i1> undef, <vscale x 4 x i1> undef, <vscale x 4 x i32> zeroinitializer
 ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction:   %24 = shufflevector <vscale x 2 x i1> undef, <vscale x 2 x i1> undef, <vscale x 2 x i32> zeroinitializer
-; CHECK-NETX: Cost Model: Found an estimated cost of 0 for instruction:   ret void
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction:   ret void
 
   %zero = shufflevector <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
   %1 = shufflevector <vscale x 32 x i8> undef, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer

llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/diverged-entry-headers.ll

@@ -90,7 +90,7 @@ S:
   br i1 %cond.uni, label %exit, label %T
 
 T:
-; CHECK-NIT:   DIVERGENT:   %tt.phi = phi i32
+; CHECK-NOT:   DIVERGENT:   %tt.phi = phi i32
   %tt.phi = phi i32 [ %ss, %S ], [ %a, %entry ]
   %tt = add i32 %b, 1
   br label %P

llvm/test/Assembler/bfloat.ll

@@ -37,25 +37,25 @@ define float @check_bfloat_convert() {
   ret float %tmp
 }
 
-; ASSEM-DISASS-LABEL @snan_bfloat
+; ASSEM-DISASS-LABEL: @snan_bfloat
 define bfloat @snan_bfloat() {
 ; ASSEM-DISASS: ret bfloat 0xR7F81
     ret bfloat 0xR7F81
 }
 
-; ASSEM-DISASS-LABEL @qnan_bfloat
+; ASSEM-DISASS-LABEL: @qnan_bfloat
 define bfloat @qnan_bfloat() {
 ; ASSEM-DISASS: ret bfloat 0xR7FC0
     ret bfloat 0xR7FC0
 }
 
-; ASSEM-DISASS-LABEL @pos_inf_bfloat
+; ASSEM-DISASS-LABEL: @pos_inf_bfloat
 define bfloat @pos_inf_bfloat() {
 ; ASSEM-DISASS: ret bfloat 0xR7F80
     ret bfloat 0xR7F80
 }
 
-; ASSEM-DISASS-LABEL @neg_inf_bfloat
+; ASSEM-DISASS-LABEL: @neg_inf_bfloat
 define bfloat @neg_inf_bfloat() {
 ; ASSEM-DISASS: ret bfloat 0xRFF80
     ret bfloat 0xRFF80

llvm/test/CodeGen/AArch64/arm64_32-atomics.ll

@@ -2,70 +2,70 @@
 ; RUN: llc -mtriple=arm64_32-apple-ios7.0 -mattr=+outline-atomics -o - %s | FileCheck %s -check-prefix=OUTLINE-ATOMICS
 
 define i8 @test_load_8(ptr %addr) {
-; CHECK-LABAL: test_load_8:
+; CHECK-LABEL: test_load_8:
 ; CHECK: ldarb w0, [x0]
   %val = load atomic i8, ptr %addr seq_cst, align 1
   ret i8 %val
 }
 
 define i16 @test_load_16(ptr %addr) {
-; CHECK-LABAL: test_load_16:
+; CHECK-LABEL: test_load_16:
 ; CHECK: ldarh w0, [x0]
   %val = load atomic i16, ptr %addr acquire, align 2
   ret i16 %val
 }
 
 define i32 @test_load_32(ptr %addr) {
-; CHECK-LABAL: test_load_32:
+; CHECK-LABEL: test_load_32:
 ; CHECK: ldar w0, [x0]
   %val = load atomic i32, ptr %addr seq_cst, align 4
   ret i32 %val
 }
 
 define i64 @test_load_64(ptr %addr) {
-; CHECK-LABAL: test_load_64:
+; CHECK-LABEL: test_load_64:
 ; CHECK: ldar x0, [x0]
   %val = load atomic i64, ptr %addr seq_cst, align 8
   ret i64 %val
 }
 
 define ptr @test_load_ptr(ptr %addr) {
-; CHECK-LABAL: test_load_ptr:
+; CHECK-LABEL: test_load_ptr:
 ; CHECK: ldar w0, [x0]
   %val = load atomic ptr, ptr %addr seq_cst, align 8
   ret ptr %val
 }
 
 define void @test_store_8(ptr %addr) {
-; CHECK-LABAL: test_store_8:
+; CHECK-LABEL: test_store_8:
 ; CHECK: stlrb wzr, [x0]
   store atomic i8 0, ptr %addr seq_cst, align 1
   ret void
 }
 
 define void @test_store_16(ptr %addr) {
-; CHECK-LABAL: test_store_16:
+; CHECK-LABEL: test_store_16:
 ; CHECK: stlrh wzr, [x0]
   store atomic i16 0, ptr %addr seq_cst, align 2
   ret void
 }
 
 define void @test_store_32(ptr %addr) {
-; CHECK-LABAL: test_store_32:
+; CHECK-LABEL: test_store_32:
 ; CHECK: stlr wzr, [x0]
   store atomic i32 0, ptr %addr seq_cst, align 4
   ret void
 }
 
 define void @test_store_64(ptr %addr) {
-; CHECK-LABAL: test_store_64:
+; CHECK-LABEL: test_store_64:
 ; CHECK: stlr xzr, [x0]
   store atomic i64 0, ptr %addr seq_cst, align 8
   ret void
 }
 
 define void @test_store_ptr(ptr %addr) {
-; CHECK-LABAL: test_store_ptr:
+; CHECK-LABEL: test_store_ptr:
 ; CHECK: stlr wzr, [x0]
   store atomic ptr null, ptr %addr seq_cst, align 8
   ret void

llvm/test/CodeGen/AArch64/arm64ec-entry-thunks.ll

@@ -1,7 +1,7 @@
 ; RUN: llc -mtriple=arm64ec-pc-windows-msvc < %s | FileCheck %s
 
 define void @no_op() nounwind {
-; CHECK-LABEL     .def    $ientry_thunk$cdecl$v$v;
+; CHECK-LABEL:     .def    $ientry_thunk$cdecl$v$v;
 ; CHECK:          .section        .wowthk$aa,"xr",discard,$ientry_thunk$cdecl$v$v
 ; CHECK:          // %bb.0:
 ; CHECK-NEXT:     stp     q6, q7, [sp, #-176]!            // 32-byte Folded Spill

llvm/test/CodeGen/AArch64/fpimm.ll

@@ -38,7 +38,7 @@ define void @check_double() {
 ; 64-bit ORR followed by MOVK.
 ; CHECK-DAG: mov  [[XFP0:x[0-9]+]], #1082331758844
 ; CHECK-DAG: movk [[XFP0]], #64764, lsl #16
-; CHECk-DAG: fmov {{d[0-9]+}}, [[XFP0]]
+; CHECK-DAG: fmov {{d[0-9]+}}, [[XFP0]]
   %newval3 = fadd double %val, 0xFCFCFC00FC
   store volatile double %newval3, ptr @varf64
 

llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-diff-scope-same-key.ll

@@ -28,7 +28,7 @@ define void @a() "sign-return-address"="all" {
 }
 
 define void @b() "sign-return-address"="non-leaf" {
-; CHECK-LABE:      b:                                     // @b
+; CHECK-LABEL:     b:                                     // @b
 ; V8A-NOT:         hint #25
 ; V83A-NOT:        paciasp
 ; CHECK-NOT:       .cfi_negate_ra_state

llvm/test/CodeGen/AArch64/speculation-hardening-sls.ll

@@ -192,7 +192,7 @@ entry:
 ; CHECK: .Lfunc_end
 }
 
-; HARDEN-label: __llvm_slsblr_thunk_x0:
+; HARDEN-LABEL: __llvm_slsblr_thunk_x0:
 ; HARDEN:    mov x16, x0
 ; HARDEN:    br x16
 ; ISBDSB-NEXT: dsb sy
@@ -208,7 +208,7 @@ entry:
 ; HARDEN-COMDAT-OFF-NOT:  .hidden __llvm_slsblr_thunk_x19
 ; HARDEN-COMDAT-OFF-NOT:  .weak __llvm_slsblr_thunk_x19
 ; HARDEN-COMDAT-OFF:      .type __llvm_slsblr_thunk_x19,@function
-; HARDEN-label: __llvm_slsblr_thunk_x19:
+; HARDEN-LABEL: __llvm_slsblr_thunk_x19:
 ; HARDEN:    mov x16, x19
 ; HARDEN:    br x16
 ; ISBDSB-NEXT: dsb sy

llvm/test/CodeGen/AArch64/stp-opt-with-renaming-undef-assert.mir

@@ -12,7 +12,7 @@
 
 # This test also checks that pairwise store STP is generated.
 
-# CHECK-LABLE: test
+# CHECK-LABEL: test
 # CHECK: bb.0:
 # CHECK-NEXT: liveins: $x0, $x17, $x18
 # CHECK: renamable $q13_q14_q15 = LD3Threev16b undef renamable $x17 :: (load (s384) from `ptr undef`, align 64)

llvm/test/CodeGen/AMDGPU/addrspacecast.ll

@@ -108,7 +108,7 @@ define amdgpu_kernel void @use_global_to_flat_addrspacecast(ptr addrspace(1) %pt
 }
 
 ; no-op
-; HSA-LABEl: {{^}}use_constant_to_flat_addrspacecast:
+; HSA-LABEL: {{^}}use_constant_to_flat_addrspacecast:
 ; HSA: s_load_dwordx2 s[[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]]
 ; HSA-DAG: v_mov_b32_e32 v[[VPTRLO:[0-9]+]], s[[PTRLO]]
 ; HSA-DAG: v_mov_b32_e32 v[[VPTRHI:[0-9]+]], s[[PTRHI]]
@@ -119,7 +119,7 @@ define amdgpu_kernel void @use_constant_to_flat_addrspacecast(ptr addrspace(4) %
   ret void
 }
 
-; HSA-LABEl: {{^}}use_constant_to_global_addrspacecast:
+; HSA-LABEL: {{^}}use_constant_to_global_addrspacecast:
 ; HSA: s_load_dwordx2 s[[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]]
 ; CI-DAG: v_mov_b32_e32 v[[VPTRLO:[0-9]+]], s[[PTRLO]]
 ; CI-DAG: v_mov_b32_e32 v[[VPTRHI:[0-9]+]], s[[PTRHI]]