AMDGPU: Stop using the wavemask register class for SCC cross class copies #161801
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…pies SCC should be copied to a 32-bit SGPR. Using a wave mask doesn't make sense.
arsenm
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cdevadas,
higher-performance,
jayfoad and
rampitec
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@llvm/pr-subscribers-backend-amdgpu Author: Matt Arsenault (arsenm) ChangesSCC should be copied to a 32-bit SGPR. Using a wave mask doesn't make Full diff: https://github.com/llvm/llvm-project/pull/161801.diff 1 Files Affected:
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index 21735f91f4ad7..ba29dd4ae61d4 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -1118,9 +1118,7 @@ SIRegisterInfo::getPointerRegClass(unsigned Kind) const {
const TargetRegisterClass *
SIRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
- if (RC == &AMDGPU::SCC_CLASSRegClass)
- return getWaveMaskRegClass();
- return RC;
+ return RC == &AMDGPU::SCC_CLASSRegClass ? &AMDGPU::SReg_32RegClass : RC;
}
static unsigned getNumSubRegsForSpillOp(const MachineInstr &MI,
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| if (RC == &AMDGPU::SCC_CLASSRegClass) | ||
| return getWaveMaskRegClass(); | ||
| return RC; | ||
| return RC == &AMDGPU::SCC_CLASSRegClass ? &AMDGPU::SReg_32RegClass : RC; |
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Shouldn't SCC_CLASS depend on the wavesize?
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No. These have nothing to do with each other. To extract a value into an allocatable register, a 32-bit SGPR is the natural choice
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Are there any codegen changes? |
I don't think so. There could maybe be dag scheduling changes but I haven't found them |
SCC should be copied to a 32-bit SGPR. Using a wave mask doesn't make
sense.