[DemandedBits] Support non-constant shift amounts #148880

karouzakisp · 2025-07-15T16:11:49Z

This patch adds support for the shift operators to handle non-constant shift operands.

ashr proof -->https://alive2.llvm.org/ce/z/EN-siK
lshr proof --> https://alive2.llvm.org/ce/z/eeGzyB
shl proof --> https://alive2.llvm.org/ce/z/dpvbkq

This is done by supporting shift operators to handle non constant shift amount.

github-actions · 2025-07-15T16:12:10Z

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llvmbot · 2025-07-15T16:12:42Z

@llvm/pr-subscribers-llvm-analysis

Author: Panagiotis K (karouzakisp)

Changes

This is part of a larger PR: #148853
To improve the DemandedBits Analysis.

Here we add support to the shift operators to handle non-constant shift operands.

Full diff: https://github.com/llvm/llvm-project/pull/148880.diff

2 Files Affected:

(modified) llvm/lib/Analysis/DemandedBits.cpp (+46)
(modified) llvm/test/Analysis/DemandedBits/shl.ll (+47-1)

diff --git a/llvm/lib/Analysis/DemandedBits.cpp b/llvm/lib/Analysis/DemandedBits.cpp
index 6694d5cc06c8c..2d30575c19130 100644
--- a/llvm/lib/Analysis/DemandedBits.cpp
+++ b/llvm/lib/Analysis/DemandedBits.cpp
@@ -36,6 +36,7 @@
 #include "llvm/Support/Casting.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/KnownBits.h"
+#include "llvm/Support/MathExtras.h"
 #include "llvm/Support/raw_ostream.h"
 #include <algorithm>
 #include <cstdint>
@@ -183,6 +184,17 @@ void DemandedBits::determineLiveOperandBits(
           AB |= APInt::getHighBitsSet(BitWidth, ShiftAmt+1);
         else if (S->hasNoUnsignedWrap())
           AB |= APInt::getHighBitsSet(BitWidth, ShiftAmt);
+      } else {
+        ComputeKnownBits(BitWidth, UserI->getOperand(1), nullptr);
+        unsigned Min = Known.getMinValue().getLimitedValue(BitWidth - 1);
+        unsigned Max = Known.getMaxValue().getLimitedValue(BitWidth - 1);
+        // similar to Lshr case
+        AB = (AOut.lshr(Min) | AOut.lshr(Max));
+        const auto *S = cast<ShlOperator>(UserI);
+        if (S->hasNoSignedWrap())
+          AB |= APInt::getHighBitsSet(BitWidth, Max + 1);
+        else if (S->hasNoUnsignedWrap())
+          AB |= APInt::getHighBitsSet(BitWidth, Max);
       }
     }
     break;
@@ -197,6 +209,19 @@ void DemandedBits::determineLiveOperandBits(
         // (they must be zero).
         if (cast<LShrOperator>(UserI)->isExact())
           AB |= APInt::getLowBitsSet(BitWidth, ShiftAmt);
+      } else {
+        ComputeKnownBits(BitWidth, UserI->getOperand(1), nullptr);
+        unsigned Min = Known.getMinValue().getLimitedValue(BitWidth - 1);
+        unsigned Max = Known.getMaxValue().getLimitedValue(BitWidth - 1);
+        // Suppose AOut == 0b0000 0011
+        // [min, max] = [1, 3]
+        // shift by 1 we get 0b0000 0110
+        // shift by 2 we get 0b0000 1100
+        // shift by 3 we get 0b0001 1000
+        // we take the or here because need to cover all the above possibilities
+        AB = (AOut.shl(Min) | AOut.shl(Max));
+        if (cast<LShrOperator>(UserI)->isExact())
+          AB |= APInt::getLowBitsSet(BitWidth, Max);
       }
     }
     break;
@@ -217,6 +242,27 @@ void DemandedBits::determineLiveOperandBits(
         // (they must be zero).
         if (cast<AShrOperator>(UserI)->isExact())
           AB |= APInt::getLowBitsSet(BitWidth, ShiftAmt);
+      } else {
+        ComputeKnownBits(BitWidth, UserI->getOperand(1), nullptr);
+        unsigned Min = Known.getMinValue().getLimitedValue(BitWidth - 1);
+        unsigned Max = Known.getMaxValue().getLimitedValue(BitWidth - 1);
+        AB = (AOut.shl(Min) | AOut.shl(Max));
+
+        if (Max) {
+          // Suppose AOut = 0011 1100
+          // [min, max] = [1, 3]
+          // ShiftAmount = 1 : Mask is 1000 0000
+          // ShiftAmount = 2 : Mask is 1100 0000
+          // ShiftAmount = 3 : Mask is 1110 0000
+          // The Mask with Max covers every case in [min, max],
+          // so we are done
+          if ((AOut & APInt::getHighBitsSet(BitWidth, Max)).getBoolValue())
+            AB.setSignBit();
+        }
+        // If the shift is exact, then the low bits are not dead
+        // (they must be zero).
+        if (cast<AShrOperator>(UserI)->isExact())
+          AB |= APInt::getLowBitsSet(BitWidth, Max);
       }
     }
     break;
diff --git a/llvm/test/Analysis/DemandedBits/shl.ll b/llvm/test/Analysis/DemandedBits/shl.ll
index e41f5f4107735..c3313a93c1e85 100644
--- a/llvm/test/Analysis/DemandedBits/shl.ll
+++ b/llvm/test/Analysis/DemandedBits/shl.ll
@@ -57,10 +57,56 @@ define i8 @test_shl(i32 %a, i32 %b) {
 ; CHECK-DAG:  DemandedBits: 0xff for %shl.t = trunc i32 %shl to i8
 ; CHECK-DAG:  DemandedBits: 0xff for %shl in %shl.t = trunc i32 %shl to i8
 ; CHECK-DAG:  DemandedBits: 0xff for %shl = shl i32 %a, %b
-; CHECK-DAG:  DemandedBits: 0xffffffff for %a in %shl = shl i32 %a, %b
+; CHECK-DAG:  DemandedBits: 0xff for %a in %shl = shl i32 %a, %b
 ; CHECK-DAG:  DemandedBits: 0xffffffff for %b in %shl = shl i32 %a, %b
 ;
   %shl = shl i32 %a, %b
   %shl.t = trunc i32 %shl to i8
   ret i8 %shl.t
 }
+
+define i8 @test_shl_var_amount(i32 %a, i32 %b){
+; CHECK-LABEL: 'test_shl_var_amount'
+; CHECK-DAG: DemandedBits: 0xff for   %5 = trunc i32 %4 to i8
+; CHECK-DAG: DemandedBits: 0xff for %4 in   %5 = trunc i32 %4 to i8
+; CHECK-DAG: DemandedBits: 0xff for   %4 = shl i32 %1, %3
+; CHECK-DAG: DemandedBits: 0xff for %1 in   %4 = shl i32 %1, %3
+; CHECK-DAG: DemandedBits: 0xffffffff for %3 in   %4 = shl i32 %1, %3
+; CHECK-DAG: DemandedBits: 0xff for   %2 = trunc i32 %1 to i8
+; CHECK-DAG: DemandedBits: 0xff for %1 in   %2 = trunc i32 %1 to i8
+; CHECK-DAG: DemandedBits: 0xffffffff for   %3 = zext i8 %2 to i32
+; CHECK-DAG: DemandedBits: 0xff for %2 in   %3 = zext i8 %2 to i32
+; CHECK-DAG: DemandedBits: 0xff for   %1 = add nsw i32 %a, %b
+; CHECK-DAG: DemandedBits: 0xff for %a in   %1 = add nsw i32 %a, %b
+; CHECK-DAG: DemandedBits: 0xff for %b in   %1 = add nsw i32 %a, %b
+;
+  %1 = add nsw i32 %a, %b
+  %2 = trunc i32 %1 to i8
+  %3 = zext i8 %2 to i32
+  %4 = shl i32 %1, %3
+  %5 = trunc i32 %4 to i8
+  ret i8 %5
+}
+
+define i8 @test_shl_var_amount_nsw(i32 %a, i32 %b){
+ ; CHECK-LABEL 'test_shl_var_amount_nsw'
+ ; CHECK-DAG: DemandedBits: 0xff for   %5 = trunc i32 %4 to i8
+ ; CHECK-DAG: DemandedBits: 0xff for %4 in   %5 = trunc i32 %4 to i8
+ ; CHECK-DAG: DemandedBits: 0xff for   %4 = shl nsw i32 %1, %3
+ ; CHECK-DAG: DemandedBits: 0xffffffff for %1 in   %4 = shl nsw i32 %1, %3
+ ; CHECK-DAG: DemandedBits: 0xffffffff for %3 in   %4 = shl nsw i32 %1, %3
+ ; CHECK-DAG: DemandedBits: 0xffffffff for   %3 = zext i8 %2 to i32
+ ; CHECK-DAG: DemandedBits: 0xff for %2 in   %3 = zext i8 %2 to i32
+ ; CHECK-DAG: DemandedBits: 0xff for   %2 = trunc i32 %1 to i8
+ ; CHECK-DAG: DemandedBits: 0xff for %1 in   %2 = trunc i32 %1 to i8
+ ; CHECK-DAG: DemandedBits: 0xffffffff for   %1 = add nsw i32 %a, %b
+ ; CHECK-DAG: DemandedBits: 0xffffffff for %a in   %1 = add nsw i32 %a, %b
+ ; CHECK-DAG: DemandedBits: 0xffffffff for %b in   %1 = add nsw i32 %a, %b
+ ;
+  %1 = add nsw i32 %a, %b
+  %2 = trunc i32 %1 to i8
+  %3 = zext i8 %2 to i32
+  %4 = shl nsw i32 %1, %3
+  %5 = trunc i32 %4 to i8
+  ret i8 %5
+}

karouzakisp · 2025-07-15T16:20:59Z

@nikic @artagnon @jayfoad Could you please review? Thanks

artagnon

Missing coverage for lshr and ashr? Could you kindly add tests for them?

topperc · 2025-07-15T16:30:06Z

Missing tests for right shifts?

artagnon · 2025-07-15T16:33:26Z

Kindly note that we only have a squash-and-merge. As a result:

Your commit message should be filled into the PR, including the title. The PR's title and body will be used as the commit message, and the text in your commit will be discarded when landing.
Kindly add additional changes as separate commits, and avoid force-pushing except when a rebase is required.

dtcxzyw

Please provide the alive2 proof. See also my previous comment #148853 (review)

llvm/lib/Analysis/DemandedBits.cpp

…dle non continued bits for AOut

karouzakisp · 2025-07-15T20:56:56Z

Missing tests for right shifts?

I just added the tests

karouzakisp · 2025-07-15T21:17:12Z

Please provide the alive2 proof. See also my previous comment #148853 (review)

I am not certain which transformation I should verify. Maybe the one on your previous comment?

artagnon · 2025-07-15T21:27:01Z

Please provide the alive2 proof. See also my previous comment #148853 (review)

I am not certain which transformation I should verify. Maybe the one on your previous comment?

I think what we want verified is the algorithm of the analysis itself, not a particular transformation: if can express the code you wrote for DemandedBits in a language that Alive2 can verify, that would be great (this isn't exactly straight-forward, but @dtcxzyw left some hints). Think about it, and try it out: we'll help out.

dtcxzyw

Miscompilation reproducer: https://alive2.llvm.org/ce/z/bSBzWM

; bin/opt -passes=bdce test.ll -S
define i16 @src(i32 range(i32 0, 2) %x) {
entry:
  %or = or i32 0, 48
  %shl = shl i32 %or, %x
  %trunc = trunc i32 %shl to i16
  ret i16 %trunc
}

define i16 @tgt(i32 range(i32 0, 2) %x) {
entry:
  %shl = shl i32 0, %x
  %trunc = trunc i32 %shl to i16
  ret i16 %trunc
}

…ore checks

karouzakisp · 2025-07-16T20:11:34Z

Miscompilation reproducer: https://alive2.llvm.org/ce/z/bSBzWM

; bin/opt -passes=bdce test.ll -S
define i16 @src(i32 range(i32 0, 2) %x) {
entry:
  %or = or i32 0, 48
  %shl = shl i32 %or, %x
  %trunc = trunc i32 %shl to i16
  ret i16 %trunc
}

define i16 @tgt(i32 range(i32 0, 2) %x) {
entry:
  %shl = shl i32 0, %x
  %trunc = trunc i32 %shl to i16
  ret i16 %trunc
}

Fixed, Alive verifications coming soon. Hopefully this week!

karouzakisp · 2025-07-18T14:07:27Z

Please provide the alive2 proof. See also my previous comment #148853 (review)

@dtcxzyw Here are the alive2 proofs -->
https://alive2.llvm.org/ce/z/SxgY_5

Please note that since my transformation contains a loop and the Alive syntax doesn't permit loops, I added various ranges.

Please let me know if it's okay.

@artagnon, Please let me know what you think.

dtcxzyw · 2025-07-19T15:10:22Z

my transformation contains a loop and the Alive syntax doesn't permit loops

You can use a smaller integer bitwidth (e.g., i4/i8), then unroll the loop with -src-unroll=8 -tgt-unroll=8.

karouzakisp · 2025-07-19T17:13:54Z

my transformation contains a loop and the Alive syntax doesn't permit loops

You can use a smaller integer bitwidth (e.g., i4/i8), then unroll the loop with -src-unroll=8 -tgt-unroll=8.

Thanks for the tip. Here is the updated proof --> https://alive2.llvm.org/ce/z/tCvUT6

dtcxzyw · 2025-07-20T06:24:51Z

my transformation contains a loop and the Alive syntax doesn't permit loops

You can use a smaller integer bitwidth (e.g., i4/i8), then unroll the loop with -src-unroll=8 -tgt-unroll=8.

Thanks for the tip. Here is the updated proof --> https://alive2.llvm.org/ce/z/tCvUT6

In your proof, the range of shamt is not taken into account. Updated: https://alive2.llvm.org/ce/z/n4hgkX
~~Can you please add proofs for shl nsw/shl nuw/lshr/lshr exact/ashr/ashr exact?~~
Can you please add proofs for lshr/ashr?
Then you should paste the links into the PR description.

llvm/lib/Analysis/DemandedBits.cpp

karouzakisp · 2025-07-21T11:54:02Z

my transformation contains a loop and the Alive syntax doesn't permit loops

You can use a smaller integer bitwidth (e.g., i4/i8), then unroll the loop with -src-unroll=8 -tgt-unroll=8.

Thanks for the tip. Here is the updated proof --> https://alive2.llvm.org/ce/z/tCvUT6

In your proof, the range of shamt is not taken into account. Updated: https://alive2.llvm.org/ce/z/n4hgkX ~~Can you please add proofs for shl nsw/shl nuw/lshr/lshr exact/ashr/ashr exact?~~ Can you please add proofs for lshr/ashr? Then you should paste the links into the PR description.

Thanks for the help.

I just added the proofs for lshr and ashr. Also, I updated the cpp code.

llvm/lib/Analysis/DemandedBits.cpp

karouzakisp · 2025-07-28T08:16:44Z

I just updated all the proofs. Making changes in the code now, to reduce the complexity to L times log(L)

llvm/lib/Analysis/DemandedBits.cpp

artagnon

Looks very good overall, with extensive testing, although I'll leave the final sign-off to @dtcxzyw.

llvm/lib/Analysis/DemandedBits.cpp

karouzakisp · 2025-07-30T14:04:40Z

Looks very good overall, with extensive testing, although I'll leave the final sign-off to @dtcxzyw.

Artagnon, thanks for the reviews and the comments.

I just updated the code.

karouzakisp · 2025-08-01T03:23:31Z

@dtcxzyw Could you please review? Thanks!

llvm/lib/Analysis/DemandedBits.cpp

Over-approximation fixed Co-authored-by: Yingwei Zheng <[email protected]>

dtcxzyw

LGTM. Thanks.

karouzakisp · 2025-08-16T17:35:40Z

LGTM. Thanks.

@dtcxzyw I don't have merge permission. Thanks

github-actions · 2025-08-18T17:11:33Z

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[LLVM] Enhance shift operators in the Demanded Bits Analysis

b802455

This is done by supporting shift operators to handle non constant shift amount.

llvmbot added the llvm:analysis Includes value tracking, cost tables and constant folding label Jul 15, 2025

artagnon requested review from artagnon, jayfoad and nikic July 15, 2025 16:22

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Task submission dtcxzyw/llvm-opt-benchmark#1312

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zyw-bot mentioned this pull request Jul 15, 2025

pre-commit: PR148880 dtcxzyw/llvm-opt-benchmark#2573

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Fuzz PR148880 dtcxzyw/llvm-fuzz-service#103

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[LLVM] created new tests for lshr and ashr, and updated the Range han…

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…dle non continued bits for AOut

karouzakisp changed the title ~~[LLVM] Improve the DemandedBits Analysis~~ [LLVM] Improve the shift operators of the DemandedBits Analysis Jul 15, 2025

removed comment

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nikic changed the title ~~[LLVM] Improve the shift operators of the DemandedBits Analysis~~ [DemandedBits] Support non-constant shift amounts Jul 16, 2025

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fixed or-->trunc->shl error, by updating the GetShiftedRange, needs m…

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…ore checks

added more range tests

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pre-commit: PR148880 dtcxzyw/llvm-opt-benchmark#2586

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removed wrong const and exceeding bit

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optimized loop to nlog(n) time complexity!

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karouzakisp added 2 commits July 29, 2025 20:14

added lambda

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wrong type fix

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updated types

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Looks correct

e9288bd

Over-approximation fixed Co-authored-by: Yingwei Zheng <[email protected]>

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dtcxzyw merged commit c2e7fad into llvm:main Aug 18, 2025
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[DemandedBits] Support non-constant shift amounts #148880

[DemandedBits] Support non-constant shift amounts #148880

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