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Ignore this!!! #288

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f40293d
lib/Support/Pipeline.cpp: Add optional field Fill and Size.
ArberSephirotheca Jun 30, 2025
4c2ab77
Add Zheyuan's tests
llvm-beanz Jul 12, 2025
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16 changes: 15 additions & 1 deletion lib/Support/Pipeline.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -111,13 +111,26 @@ void MappingTraits<offloadtest::Buffer>::mapping(IO &I,
I.mapRequired("Data", Arr); \
} else { \
int64_t ZeroInitSize; \
int64_t Size = 0; \
std::optional<Type> Fill; \
I.mapOptional("ZeroInitSize", ZeroInitSize, 0); \
I.mapOptional("Fill", Fill); \
I.mapOptional("Size", Size, 0); \
if (ZeroInitSize > 0) { \
B.Size = ZeroInitSize; \
B.Data.reset(new char[B.Size]); \
memset(B.Data.get(), 0, B.Size); \
break; \
} \
if (Fill.has_value()) { \
if (Size == 0) \
return I.setError("'Size' must be provided when using 'Fill'"); \
B.Size = Size * sizeof(Type); \
B.Data.reset(new char[B.Size]); \
std::fill_n(reinterpret_cast<Type *>(B.Data.get()), Size, \
Fill.value()); \
break; \
} \
llvm::SmallVector<Type, 64> Arr; \
I.mapRequired("Data", Arr); \
B.Size = Arr.size() * sizeof(Type); \
Expand All @@ -139,7 +152,8 @@ void MappingTraits<offloadtest::Buffer>::mapping(IO &I,
DATA_CASE(Float16, llvm::yaml::Hex16)
DATA_CASE(Float32, float)
DATA_CASE(Float64, double)
DATA_CASE(Bool, uint32_t) // Because sizeof(bool) is 1 but HLSL represents a bool using 4 bytes.
DATA_CASE(Bool, uint32_t) // Because sizeof(bool) is 1 but HLSL represents a
// bool using 4 bytes.
}

I.mapOptional("OutputProps", B.OutputProps);
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62 changes: 62 additions & 0 deletions test/MemExecModel/mem_conv_atomic_device.test
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Original file line number Diff line number Diff line change
@@ -0,0 +1,62 @@
#--- source.hlsl
RWStructuredBuffer<uint> write_val : register(u0);
RWStructuredBuffer<uint> buf : register(u1);

[numthreads(256,1,1)]
void main(uint3 TID : SV_DispatchThreadID) {
uint tid = TID.x;
uint temp;
InterlockedExchange(write_val[0], tid, temp);
uint read_val;
InterlockedAdd(write_val[0], 0, read_val);
// Check if all threads in the wave read the same value
buf[tid] = uint(WaveActiveAllEqual(read_val));
}
//--- pipeline.yaml
---
Shaders:
- Stage: Compute
Entry: main
DispatchSize: [6553, 1, 1]
Buffers:
- Name: write_val
Format: UInt32
Stride: 4
Data: [0]
- Name: buf
Format: UInt32
Stride: 4
Fill: 0
Size: 1677568
- Name: expected
Format: UInt32
Stride: 4
Fill: 1
Size: 1677568
Results:
- Result: Test1
Rule: BufferExact
Actual: buf
Expected: expected
DescriptorSets:
- Resources:
- Name: write_val
Kind: RWStructuredBuffer
DirectXBinding:
Register: 0
Space: 0
VulkanBinding:
Binding: 0
- Name: buf
Kind: RWStructuredBuffer
DirectXBinding:
Register: 1
Space: 0
VulkanBinding:
Binding: 1
...
#--- end

# RUN: split-file %s %t
# RUN: %dxc_target -T cs_6_0 -Fo %t.o %t/source.hlsl
# RUN: %offloader %t/pipeline.yaml %t.o
53 changes: 53 additions & 0 deletions test/MemExecModel/mem_conv_atomic_group.test
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@@ -0,0 +1,53 @@
#--- source.hlsl
RWStructuredBuffer<uint> buf : register(u0);
groupshared uint loc;

[numthreads(256,1,1)]
void main(uint3 TID : SV_DispatchThreadID) {
uint temp;
loc = 0;
GroupMemoryBarrierWithGroupSync();
uint tid = TID.x;
InterlockedExchange(loc, tid, temp);
uint read_val;
InterlockedAdd(loc, 0, read_val);
// Check if all threads in the wave read the same value
buf[tid] = uint(WaveActiveAllEqual(read_val));
}
//--- pipeline.yaml
---
Shaders:
- Stage: Compute
Entry: main
DispatchSize: [6553, 1, 1]
Buffers:
- Name: buf
Format: UInt32
Stride: 4
Fill: 0
Size: 1677568
- Name: expected
Format: UInt32
Stride: 4
Fill: 1
Size: 1677568
Results:
- Result: Test1
Rule: BufferExact
Actual: buf
Expected: expected
DescriptorSets:
- Resources:
- Name: buf
Kind: RWStructuredBuffer
DirectXBinding:
Register: 0
Space: 0
VulkanBinding:
Binding: 0
...
#--- end

# RUN: split-file %s %t
# RUN: %dxc_target -T cs_6_0 -Fo %t.o %t/source.hlsl
# RUN: %offloader %t/pipeline.yaml %t.o
61 changes: 61 additions & 0 deletions test/MemExecModel/mem_conv_device.test
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Original file line number Diff line number Diff line change
@@ -0,0 +1,61 @@
#--- source.hlsl
RWStructuredBuffer<uint> write_val : register(u0);
RWStructuredBuffer<uint> buf : register(u1);

[numthreads(256,1,1)]
void main(uint3 TID : SV_DispatchThreadID) {
uint tid = TID.x;
uint temp;
InterlockedExchange(write_val[0], tid, temp);
uint read_val = write_val[0];
// Check if all threads in the wave read the same value
buf[tid] = uint(WaveActiveAllEqual(read_val));
}
//--- pipeline.yaml
---
Shaders:
- Stage: Compute
Entry: main
DispatchSize: [6553, 1, 1]
Buffers:
- Name: write_val
Format: UInt32
Stride: 4
Data: [0]
- Name: buf
Format: UInt32
Stride: 4
Fill: 0
Size: 1677568
- Name: expected
Format: UInt32
Stride: 4
Fill: 1
Size: 1677568
Results:
- Result: Test1
Rule: BufferExact
Actual: buf
Expected: expected
DescriptorSets:
- Resources:
- Name: write_val
Kind: RWStructuredBuffer
DirectXBinding:
Register: 0
Space: 0
VulkanBinding:
Binding: 0
- Name: buf
Kind: RWStructuredBuffer
DirectXBinding:
Register: 1
Space: 0
VulkanBinding:
Binding: 1
...
#--- end

# RUN: split-file %s %t
# RUN: %dxc_target -T cs_6_0 -Fo %t.o %t/source.hlsl
# RUN: %offloader %t/pipeline.yaml %t.o
52 changes: 52 additions & 0 deletions test/MemExecModel/mem_conv_group.test
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Original file line number Diff line number Diff line change
@@ -0,0 +1,52 @@
#--- source.hlsl
RWStructuredBuffer<uint> buf : register(u0);
groupshared uint loc;

[numthreads(256,1,1)]
void main(uint3 TID : SV_DispatchThreadID) {
uint temp;
loc = 0;
GroupMemoryBarrierWithGroupSync();
uint tid = TID.x;
InterlockedExchange(loc, tid, temp);
uint read_val = loc;
// Check if all threads in the wave read the same value
buf[tid] = uint(WaveActiveAllEqual(read_val));
}
//--- pipeline.yaml
---
Shaders:
- Stage: Compute
Entry: main
DispatchSize: [6553, 1, 1]
Buffers:
- Name: buf
Format: UInt32
Stride: 4
Fill: 0
Size: 1677568
- Name: expected
Format: UInt32
Stride: 4
Fill: 1
Size: 1677568
Results:
- Result: Test1
Rule: BufferExact
Actual: buf
Expected: expected
DescriptorSets:
- Resources:
- Name: buf
Kind: RWStructuredBuffer
DirectXBinding:
Register: 0
Space: 0
VulkanBinding:
Binding: 0
...
#--- end

# RUN: split-file %s %t
# RUN: %dxc_target -T cs_6_0 -Fo %t.o %t/source.hlsl
# RUN: %offloader %t/pipeline.yaml %t.o
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