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shared/mega32x.cpp: use util::fifo for 68k to SH-2 comms
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3 files changed

+41
-99
lines changed

3 files changed

+41
-99
lines changed

hash/32x.xml

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2295,8 +2295,10 @@ Accesses [cart] backup RAM
22952295
<year>199?</year>
22962296
<publisher>Time Warner Interactive</publisher>
22972297
<notes><![CDATA[
2298+
Black screen, needs tighter sync after FIFO rewrite (?)
22982299
Uses [DE-9] port 2 button B for something
22992300
[Slave SH-2] tests [SCI] port
2301+
Writes 0x0f1f to $a130e0 in undefined [cart] area
23002302
]]></notes>
23012303
<part name="cart" interface="_32x_cart">
23022304
<dataarea name="rom" size="262144">

src/mame/shared/mega32x.cpp

Lines changed: 37 additions & 91 deletions
Original file line numberDiff line numberDiff line change
@@ -345,7 +345,7 @@ uint16_t sega_32x_device::m68k_a15106_r()
345345

346346
retval = m_a15106_reg;
347347

348-
if (m_fifo_block_a_full && m_fifo_block_b_full) retval |= 0x8080;
348+
if (m_fifo[0].full() && m_fifo[1].full()) retval |= 0x8080;
349349

350350
return retval;
351351
}
@@ -373,12 +373,10 @@ void sega_32x_device::m68k_a15106_w(address_space &space, offs_t offset, uint16_
373373

374374
if((m_a15106_reg & 4) == 0) // clears the FIFO state
375375
{
376-
m_current_fifo_block = m_fifo_block_a;
377-
m_current_fifo_readblock = m_fifo_block_b;
378-
m_current_fifo_write_pos = 0;
379-
m_current_fifo_read_pos = 0;
380-
m_fifo_block_a_full = 0;
381-
m_fifo_block_b_full = 0;
376+
m_fifo[0].clear();
377+
m_fifo[1].clear();
378+
m_fifo_write_block = 0;
379+
m_fifo_read_block = 0;
382380
}
383381

384382
//logerror("m68k_a15106_w %04x\n", data);
@@ -423,45 +421,18 @@ uint16_t sega_32x_device::dreq_common_r(address_space &space, offs_t offset)
423421
return 0xffff;
424422
}
425423

426-
uint16_t retdat = m_current_fifo_readblock[m_current_fifo_read_pos];
427-
428-
m_current_fifo_read_pos++;
429-
430-
// logerror("reading FIFO!\n");
431-
432-
if (m_current_fifo_readblock == m_fifo_block_a && !m_fifo_block_a_full)
433-
logerror("Fifo block a isn't filled!\n");
434-
435-
if (m_current_fifo_readblock == m_fifo_block_b && !m_fifo_block_b_full)
436-
logerror("%s Fifo block b isn't filled!\n", machine().describe_context());
437-
438-
439-
if (m_current_fifo_read_pos==4)
424+
if (m_fifo[m_fifo_read_block].empty())
440425
{
441-
if (m_current_fifo_readblock == m_fifo_block_a)
442-
{
443-
m_fifo_block_a_full = 0;
444-
445-
if (m_fifo_block_b_full)
446-
{
447-
m_current_fifo_readblock = m_fifo_block_b;
448-
m_current_fifo_block = m_fifo_block_a;
449-
}
450-
451-
m_current_fifo_read_pos = 0;
452-
}
453-
else if (m_current_fifo_readblock == m_fifo_block_b)
454-
{
455-
m_fifo_block_b_full = 0;
426+
logerror("Attempt to read FIFO while empty %c!\n", m_fifo_read_block ? 'B' : 'A');
427+
return 0xffff;
428+
}
456429

457-
if (m_fifo_block_a_full)
458-
{
459-
m_current_fifo_readblock = m_fifo_block_a;
460-
m_current_fifo_block = m_fifo_block_b;
461-
}
430+
uint16_t retdat = m_fifo[m_fifo_read_block].dequeue();
462431

463-
m_current_fifo_read_pos = 0;
464-
}
432+
if (m_fifo[m_fifo_read_block].empty())
433+
{
434+
m_fifo_read_block ^= 1;
435+
//m_main_cpu->resume(1);
465436
}
466437

467438
return retdat;
@@ -527,15 +498,11 @@ void sega_32x_device::dreq_common_w(address_space &space, offs_t offset, uint16_
527498
return;
528499
}
529500

530-
if (m_current_fifo_block==m_fifo_block_a && m_fifo_block_a_full)
531-
{
532-
logerror("attempt to write to Full Fifo block a!\n");
533-
return;
534-
}
535-
536-
if (m_current_fifo_block==m_fifo_block_b && m_fifo_block_b_full)
501+
if (m_fifo[m_fifo_write_block].full())
537502
{
538-
logerror("attempt to write to Full Fifo block b!\n");
503+
logerror("Attempt to write with FIFO full block %c!\n", m_fifo_write_block ? 'B' : 'A');
504+
m_main_cpu->defer_access();
505+
//m_main_cpu->suspend_until_trigger(1, true);
539506
return;
540507
}
541508

@@ -553,43 +520,23 @@ void sega_32x_device::dreq_common_w(address_space &space, offs_t offset, uint16_
553520
return;
554521
}
555522

556-
m_current_fifo_block[m_current_fifo_write_pos] = data;
557-
m_current_fifo_write_pos++;
523+
m_fifo[m_fifo_write_block].enqueue(data);
558524
m_dreq_size --;
559525

560-
if (m_current_fifo_write_pos==4)
526+
if (m_fifo[m_fifo_write_block].full())
561527
{
562-
if (m_current_fifo_block==m_fifo_block_a)
563-
{
564-
m_fifo_block_a_full = 1;
565-
if (!m_fifo_block_b_full)
566-
{
567-
m_current_fifo_block = m_fifo_block_b;
568-
m_current_fifo_readblock = m_fifo_block_a;
569-
// incase we have a stalled DMA in progress, let the SH2 know there is data available
570-
m_master_cpu->sh2_notify_dma_data_available();
571-
m_slave_cpu->sh2_notify_dma_data_available();
572-
573-
}
574-
m_current_fifo_write_pos = 0;
575-
}
576-
else
577-
{
578-
m_fifo_block_b_full = 1;
579-
580-
if (!m_fifo_block_a_full)
581-
{
582-
m_current_fifo_block = m_fifo_block_a;
583-
m_current_fifo_readblock = m_fifo_block_b;
584-
// incase we have a stalled DMA in progress, let the SH2 know there is data available
585-
m_master_cpu->sh2_notify_dma_data_available();
586-
m_slave_cpu->sh2_notify_dma_data_available();
587-
}
588-
589-
m_current_fifo_write_pos = 0;
590-
}
528+
m_fifo_write_block ^= 1;
529+
m_master_cpu->sh2_notify_dma_data_available();
530+
m_slave_cpu->sh2_notify_dma_data_available();
591531
}
592532

533+
//if (m_fifo[0].full() && m_fifo[1].full())
534+
//{
535+
// //m_fifo_read_block ^= 1;
536+
// //m_master_cpu->sh2_notify_dma_data_available();
537+
// //m_slave_cpu->sh2_notify_dma_data_available();
538+
//}
539+
593540
break;
594541
}
595542
}
@@ -1560,10 +1507,10 @@ SH2_DMA_FIFO_DATA_AVAILABLE_CB(sega_32x_device::_32x_fifo_available_callback)
15601507
{
15611508
if (src==0x4012)
15621509
{
1563-
if (m_current_fifo_readblock==m_fifo_block_a && m_fifo_block_a_full)
1510+
if (!m_fifo[0].empty() && m_fifo_read_block == 0)
15641511
return 1;
15651512

1566-
if (m_current_fifo_readblock==m_fifo_block_b && m_fifo_block_b_full)
1513+
if (!m_fifo[1].empty() && m_fifo_read_block == 1)
15671514
return 1;
15681515

15691516
return 0;
@@ -1724,6 +1671,7 @@ void sega_32x_device::device_add_mconfig(machine_config &config)
17241671
// (update: actually fixed by using synchronize in comms space)
17251672
// sharrierju: "press start button" will flicker at /512 onward
17261673
// chaotixju: hangs after sega logo at /256
1674+
// twcmd: expects /64 after FIFO rewrite
17271675

17281676
// some games appear to dislike 'perfect' levels of interleave, probably due to
17291677
// non-emulated cache, ram waitstates and other issues?
@@ -1807,12 +1755,10 @@ void sega_32x_device::device_reset()
18071755
m_32x_displaymode = 0;
18081756
m_32x_240mode = 0;
18091757

1810-
m_current_fifo_block = m_fifo_block_a;
1811-
m_current_fifo_readblock = m_fifo_block_b;
1812-
m_current_fifo_write_pos = 0;
1813-
m_current_fifo_read_pos = 0;
1814-
m_fifo_block_a_full = 0;
1815-
m_fifo_block_b_full = 0;
1758+
m_fifo[0].clear();
1759+
m_fifo[1].clear();
1760+
m_fifo_write_block = 0;
1761+
m_fifo_read_block = 0;
18161762

18171763
m_32x_hcount_compare_val = -1;
18181764
m_32x_hcount_reg = 0;

src/mame/shared/mega32x.h

Lines changed: 2 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -192,14 +192,8 @@ class sega_32x_device : public device_t, public device_palette_interface, public
192192
uint16_t *m_32x_display_dram = nullptr, *m_32x_access_dram = nullptr;
193193
std::unique_ptr<uint16_t[]> m_32x_palette;
194194

195-
uint16_t m_fifo_block_a[4]{};
196-
uint16_t m_fifo_block_b[4]{};
197-
uint16_t* m_current_fifo_block = nullptr;
198-
uint16_t* m_current_fifo_readblock = nullptr;
199-
int m_current_fifo_write_pos = 0;
200-
int m_current_fifo_read_pos = 0;
201-
int m_fifo_block_a_full = 0;
202-
int m_fifo_block_b_full = 0;
195+
util::fifo<u16, 4> m_fifo[2];
196+
u8 m_fifo_write_block, m_fifo_read_block;
203197
};
204198

205199

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