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Merge pull request #32 from maxiwoj/tm/jtag-low-level
Tm/jtag
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‎Inc/adiv5/adiv5.h‎

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/*
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* This file is part of the Black Magic Debug project.
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*
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* Copyright (C) 2011 Black Sphere Technologies Ltd.
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* Written by Gareth McMullin <[email protected]>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ADIV5_H
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#define __ADIV5_H
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#include "stm32f4xx_it.h"
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/* ADIv5 DP Register addresses */
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#define ADIV5_DP_IDCODE 0x0
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#define ADIV5_DP_ABORT 0x0
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#define ADIV5_DP_CTRLSTAT 0x4
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#define ADIV5_DP_SELECT 0x8
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#define ADIV5_DP_RDBUFF 0xC
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/* AP Abort Register (ABORT) */
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/* Bits 31:5 - Reserved */
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#define ADIV5_DP_ABORT_ORUNERRCLR (1 << 4)
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#define ADIV5_DP_ABORT_WDERRCLR (1 << 3)
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#define ADIV5_DP_ABORT_STKERRCLR (1 << 2)
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#define ADIV5_DP_ABORT_STKCMPCLR (1 << 1)
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/* Bits 5:1 - SW-DP only, reserved in JTAG-DP */
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#define ADIV5_DP_ABORT_DAPABORT (1 << 0)
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/* Control/Status Register (CTRLSTAT) */
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#define ADIV5_DP_CTRLSTAT_CSYSPWRUPACK (1u << 31)
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#define ADIV5_DP_CTRLSTAT_CSYSPWRUPREQ (1u << 30)
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#define ADIV5_DP_CTRLSTAT_CDBGPWRUPACK (1u << 29)
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#define ADIV5_DP_CTRLSTAT_CDBGPWRUPREQ (1u << 28)
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#define ADIV5_DP_CTRLSTAT_CDBGRSTACK (1u << 27)
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#define ADIV5_DP_CTRLSTAT_CDBGRSTREQ (1u << 26)
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/* Bits 25:24 - Reserved */
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/* Bits 23:12 - TRNCNT */
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#define ADIV5_DP_CTRLSTAT_TRNCNT
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/* Bits 11:8 - MASKLANE */
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#define ADIV5_DP_CTRLSTAT_MASKLANE
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/* Bits 7:6 - Reserved in JTAG-DP */
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#define ADIV5_DP_CTRLSTAT_WDATAERR (1u << 7)
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#define ADIV5_DP_CTRLSTAT_READOK (1u << 6)
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#define ADIV5_DP_CTRLSTAT_STICKYERR (1u << 5)
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#define ADIV5_DP_CTRLSTAT_STICKYCMP (1u << 4)
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#define ADIV5_DP_CTRLSTAT_TRNMODE_MASK (3u << 2)
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#define ADIV5_DP_CTRLSTAT_STICKYORUN (1u << 1)
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#define ADIV5_DP_CTRLSTAT_ORUNDETECT (1u << 0)
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/* ADIv5 MEM-AP Registers */
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#define ADIV5_AP_CSW 0x00
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#define ADIV5_AP_TAR 0x04
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/* 0x08 - Reserved */
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#define ADIV5_AP_DRW 0x0C
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#define ADIV5_AP_DB(x) (0x10 + (4*(x)))
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/* 0x20:0xF0 - Reserved */
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#define ADIV5_AP_CFG 0xF4
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#define ADIV5_AP_BASE 0xF8
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#define ADIV5_AP_IDR 0xFC
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/* AP Control and Status Word (CSW) */
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#define ADIV5_AP_CSW_DBGSWENABLE (1u << 31)
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/* Bits 30:24 - Prot, Implementation defined, for Cortex-M3: */
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#define ADIV5_AP_CSW_MASTERTYPE_DEBUG (1u << 29)
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#define ADIV5_AP_CSW_HPROT1 (1u << 25)
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#define ADIV5_AP_CSW_SPIDEN (1u << 23)
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/* Bits 22:12 - Reserved */
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/* Bits 11:8 - Mode, must be zero */
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#define ADIV5_AP_CSW_TRINPROG (1u << 7)
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#define ADIV5_AP_CSW_DEVICEEN (1u << 6)
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#define ADIV5_AP_CSW_ADDRINC_NONE (0u << 4)
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#define ADIV5_AP_CSW_ADDRINC_SINGLE (1u << 4)
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#define ADIV5_AP_CSW_ADDRINC_PACKED (2u << 4)
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#define ADIV5_AP_CSW_ADDRINC_MASK (3u << 4)
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/* Bit 3 - Reserved */
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#define ADIV5_AP_CSW_SIZE_BYTE (0u << 0)
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#define ADIV5_AP_CSW_SIZE_HALFWORD (1u << 0)
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#define ADIV5_AP_CSW_SIZE_WORD (2u << 0)
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#define ADIV5_AP_CSW_SIZE_MASK (7u << 0)
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/* Constants to make RnW and APnDP parameters more clear in code */
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#define ADIV5_LOW_WRITE 0
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#define ADIV5_LOW_READ 1
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#define ADIV5_LOW_DP 0
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#define ADIV5_LOW_AP 1
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typedef struct ADIv5_DP_s ADIv5_DP_t;
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/* low level functions to access ADIv5_DP */
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typedef struct ADIv5_DP_OPS_s {
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void (*dp_write)(void *priv, uint8_t addr, uint32_t value);
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uint32_t (*dp_read)(void *priv, uint8_t addr);
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uint32_t (*error)(void *priv);
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uint32_t (*low_access)(void *priv, uint8_t APnDP, uint8_t RnW,
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uint8_t addr, uint32_t value);
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void (*priv_free)(ADIv5_DP_t *this);
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} ADIv5_DP_OPS_t;
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typedef struct ADIv5_DP_s {
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uint16_t ap_count;
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ADIv5_DP_OPS_t *ops;
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void *priv;
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} ADIv5_DP_t;
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/* Structure describing AP */
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typedef struct ADIv5_AP_s ADIv5_AP_t;
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typedef struct ADIv5_AP_PRIV_s {
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ADIv5_DP_t *dp;
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uint8_t apsel;
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uint32_t idr;
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uint32_t cfg;
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uint32_t base;
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uint32_t csw;
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} ADIv5_AP_PRIV_t;
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typedef struct ADIv5_AP_OPS_s {
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uint32_t (*mem_read_word)(ADIv5_AP_PRIV_t *ap, uint32_t addr);
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void (*mem_write_word)(ADIv5_AP_PRIV_t *ap, uint32_t addr, uint32_t value);
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uint32_t (*mem_read_words)(ADIv5_AP_PRIV_t *ap, uint32_t *dest, uint32_t src, uint32_t len);
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uint32_t (*mem_write_words)(ADIv5_AP_PRIV_t *ap, uint32_t dest, const uint32_t *src, uint32_t len);
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uint32_t (*error_check)(ADIv5_AP_PRIV_t *ap);
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void (*priv_free)(ADIv5_AP_t *this);
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} ADIv5_AP_OPS_t;
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typedef struct ADIv5_AP_s {
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ADIv5_AP_OPS_t *ops;
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ADIv5_AP_PRIV_t *priv;
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} ADIv5_AP_t;
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uint16_t adiv5_init(ADIv5_DP_t *dp_low_level);
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#endif //__ADIV5_H

‎Inc/adiv5/adiv5_jtag.h‎

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#ifndef __ADIV5_JTAG_H
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#define __ADIV5_JTAG_H
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#include "adiv5/adiv5.h"
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typedef struct ADIv5_DP_JTAG_s {
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int jtag_dev_num;
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} ADIv5_DP_JTAG_t;
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int adiv5_jtag_handler(int dev_num);
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#endif //__ADIV5_JTAG_H

‎Inc/cortexm/cortexm.h‎

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#ifndef __CORTEXM_H
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#define __CORTEXM_H
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#include "stm32f4xx_it.h"
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/* target options recognised by the Cortex-M target */
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#define TOPT_FLAVOUR_V6M (1<<0) /* if not set, target is assumed to be v7m */
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#define TOPT_FLAVOUR_V7MF (1<<1) /* if set, floating-point enabled. */
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/* Private peripheral bus base address */
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#define CORTEXM_PPB_BASE 0xE0000000
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#define CORTEXM_SCS_BASE (CORTEXM_PPB_BASE + 0xE000)
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#define CORTEXM_AIRCR (CORTEXM_SCS_BASE + 0xD0C)
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#define CORTEXM_CFSR (CORTEXM_SCS_BASE + 0xD28)
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#define CORTEXM_HFSR (CORTEXM_SCS_BASE + 0xD2C)
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#define CORTEXM_DFSR (CORTEXM_SCS_BASE + 0xD30)
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#define CORTEXM_CPACR (CORTEXM_SCS_BASE + 0xD88)
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#define CORTEXM_DHCSR (CORTEXM_SCS_BASE + 0xDF0)
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#define CORTEXM_DCRSR (CORTEXM_SCS_BASE + 0xDF4)
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#define CORTEXM_DCRDR (CORTEXM_SCS_BASE + 0xDF8)
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#define CORTEXM_DEMCR (CORTEXM_SCS_BASE + 0xDFC)
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#define CORTEXM_FPB_BASE (CORTEXM_PPB_BASE + 0x2000)
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/* ARM Literature uses FP_*, we use CORTEXM_FPB_* consistently */
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#define CORTEXM_FPB_CTRL (CORTEXM_FPB_BASE + 0x000)
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#define CORTEXM_FPB_REMAP (CORTEXM_FPB_BASE + 0x004)
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#define CORTEXM_FPB_COMP(i) (CORTEXM_FPB_BASE + 0x008 + (4*(i)))
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#define CORTEXM_DWT_BASE (CORTEXM_PPB_BASE + 0x1000)
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#define CORTEXM_DWT_CTRL (CORTEXM_DWT_BASE + 0x000)
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#define CORTEXM_DWT_COMP(i) (CORTEXM_DWT_BASE + 0x020 + (0x10*(i)))
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#define CORTEXM_DWT_MASK(i) (CORTEXM_DWT_BASE + 0x024 + (0x10*(i)))
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#define CORTEXM_DWT_FUNC(i) (CORTEXM_DWT_BASE + 0x028 + (0x10*(i)))
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/* Application Interrupt and Reset Control Register (AIRCR) */
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#define CORTEXM_AIRCR_VECTKEY (0x05FA << 16)
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/* Bits 31:16 - Read as VECTKETSTAT, 0xFA05 */
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#define CORTEXM_AIRCR_ENDIANESS (1 << 15)
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/* Bits 15:11 - Unused, reserved */
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#define CORTEXM_AIRCR_PRIGROUP (7 << 8)
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/* Bits 7:3 - Unused, reserved */
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#define CORTEXM_AIRCR_SYSRESETREQ (1 << 2)
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#define CORTEXM_AIRCR_VECTCLRACTIVE (1 << 1)
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#define CORTEXM_AIRCR_VECTRESET (1 << 0)
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/* HardFault Status Register (HFSR) */
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#define CORTEXM_HFSR_DEBUGEVT (1 << 31)
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#define CORTEXM_HFSR_FORCED (1 << 30)
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/* Bits 29:2 - Not specified */
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#define CORTEXM_HFSR_VECTTBL (1 << 1)
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/* Bits 0 - Reserved */
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/* Debug Fault Status Register (DFSR) */
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/* Bits 31:5 - Reserved */
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#define CORTEXM_DFSR_RESETALL 0x1F
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#define CORTEXM_DFSR_EXTERNAL (1 << 4)
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#define CORTEXM_DFSR_VCATCH (1 << 3)
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#define CORTEXM_DFSR_DWTTRAP (1 << 2)
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#define CORTEXM_DFSR_BKPT (1 << 1)
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#define CORTEXM_DFSR_HALTED (1 << 0)
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/* Debug Halting Control and Status Register (DHCSR) */
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/* This key must be written to bits 31:16 for write to take effect */
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#define CORTEXM_DHCSR_DBGKEY 0xA05F0000
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/* Bits 31:26 - Reserved */
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#define CORTEXM_DHCSR_S_RESET_ST (1 << 25)
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#define CORTEXM_DHCSR_S_RETIRE_ST (1 << 24)
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/* Bits 23:20 - Reserved */
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#define CORTEXM_DHCSR_S_LOCKUP (1 << 19)
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#define CORTEXM_DHCSR_S_SLEEP (1 << 18)
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#define CORTEXM_DHCSR_S_HALT (1 << 17)
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#define CORTEXM_DHCSR_S_REGRDY (1 << 16)
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/* Bits 15:6 - Reserved */
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#define CORTEXM_DHCSR_C_SNAPSTALL (1 << 5) /* v7m only */
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/* Bit 4 - Reserved */
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#define CORTEXM_DHCSR_C_MASKINTS (1 << 3)
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#define CORTEXM_DHCSR_C_STEP (1 << 2)
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#define CORTEXM_DHCSR_C_HALT (1 << 1)
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#define CORTEXM_DHCSR_C_DEBUGEN (1 << 0)
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/* Debug Core Register Selector Register (DCRSR) */
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#define CORTEXM_DCRSR_REGWnR 0x00010000
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#define CORTEXM_DCRSR_REGSEL_MASK 0x0000001F
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#define CORTEXM_DCRSR_REGSEL_XPSR 0x00000010
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#define CORTEXM_DCRSR_REGSEL_MSP 0x00000011
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#define CORTEXM_DCRSR_REGSEL_PSP 0x00000012
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/* Debug Exception and Monitor Control Register (DEMCR) */
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/* Bits 31:25 - Reserved */
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#define CORTEXM_DEMCR_TRCENA (1 << 24)
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/* Bits 23:20 - Reserved */
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#define CORTEXM_DEMCR_MON_REQ (1 << 19) /* v7m only */
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#define CORTEXM_DEMCR_MON_STEP (1 << 18) /* v7m only */
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#define CORTEXM_DEMCR_VC_MON_PEND (1 << 17) /* v7m only */
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#define CORTEXM_DEMCR_VC_MON_EN (1 << 16) /* v7m only */
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/* Bits 15:11 - Reserved */
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#define CORTEXM_DEMCR_VC_HARDERR (1 << 10)
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#define CORTEXM_DEMCR_VC_INTERR (1 << 9) /* v7m only */
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#define CORTEXM_DEMCR_VC_BUSERR (1 << 8) /* v7m only */
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#define CORTEXM_DEMCR_VC_STATERR (1 << 7) /* v7m only */
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#define CORTEXM_DEMCR_VC_CHKERR (1 << 6) /* v7m only */
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#define CORTEXM_DEMCR_VC_NOCPERR (1 << 5) /* v7m only */
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#define CORTEXM_DEMCR_VC_MMERR (1 << 4) /* v7m only */
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/* Bits 3:1 - Reserved */
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#define CORTEXM_DEMCR_VC_CORERESET (1 << 0)
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/* Flash Patch and Breakpoint Control Register (FP_CTRL) */
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/* Bits 32:15 - Reserved */
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/* Bits 14:12 - NUM_CODE2 */ /* v7m only */
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/* Bits 11:8 - NUM_LIT */ /* v7m only */
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/* Bits 7:4 - NUM_CODE1 */
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/* Bits 3:2 - Unspecified */
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#define CORTEXM_FPB_CTRL_KEY (1 << 1)
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#define CORTEXM_FPB_CTRL_ENABLE (1 << 0)
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/* Data Watchpoint and Trace Mask Register (DWT_MASKx) */
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#define CORTEXM_DWT_MASK_BYTE (0 << 0)
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#define CORTEXM_DWT_MASK_HALFWORD (1 << 0)
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#define CORTEXM_DWT_MASK_WORD (3 << 0)
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/* Data Watchpoint and Trace Function Register (DWT_FUNCTIONx) */
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#define CORTEXM_DWT_FUNC_MATCHED (1 << 24)
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#define CORTEXM_DWT_FUNC_DATAVSIZE_WORD (2 << 10) /* v7m only */
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#define CORTEXM_DWT_FUNC_FUNC_READ (5 << 0)
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#define CORTEXM_DWT_FUNC_FUNC_WRITE (6 << 0)
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#define CORTEXM_DWT_FUNC_FUNC_ACCESS (7 << 0)
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/* Signals returned by cortexm_halt_wait() */
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#define SIGINT 2
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#define SIGTRAP 5
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#define SIGSEGV 11
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typedef struct ADIv5_AP_s ADIv5_AP_t;
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typedef struct CORTEXM_s CORTEXM_t;
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typedef struct CORTEXM_PRIV_s
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{
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ADIv5_AP_t *ap;
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} CORTEXM_PRIV_t;
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typedef struct CORTEXM_OPS_s
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{
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uint32_t (*read_word)(CORTEXM_PRIV_t *priv, uint32_t addr);
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void (*write_word)(CORTEXM_PRIV_t *priv, uint32_t addr, uint32_t value);
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uint32_t (*read_words)(CORTEXM_PRIV_t *priv, uint32_t *dest, uint32_t src, uint32_t len);
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uint32_t (*write_words)(CORTEXM_PRIV_t *priv, uint32_t dest, const uint32_t *src, uint32_t len);
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uint32_t (*pc_read)(CORTEXM_PRIV_t *priv);
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void (*pc_write)(CORTEXM_PRIV_t *priv, uint32_t val);
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void (*halt_request)(CORTEXM_PRIV_t *priv);
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uint32_t (*halt_wait)(CORTEXM_PRIV_t *priv);
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void (*halt_resume)(CORTEXM_PRIV_t *priv);
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uint32_t (*check_error)(CORTEXM_PRIV_t *priv);
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void (*restart)(CORTEXM_PRIV_t *priv);
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void (*free)(CORTEXM_t *cortexm);
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} CORTEXM_OPS_t;
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typedef struct CORTEXM_s
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{
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CORTEXM_OPS_t *ops;
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CORTEXM_PRIV_t *priv;
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} CORTEXM_t;
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int probe_cortexm(ADIv5_AP_t *ap);
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#endif //__CORTEXM_H

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