Add STM32L4xx support

This patch add support for STM32L4xx family.
Additionlay fixed memory managment bug in stm32f4.c (founded while
debuging and changing code to work with STM32L4xx).

Author: Chimstaz

Inc/cortexm/stm32/stm32l4.h

@@ -0,0 +1,79 @@
+#ifndef __STM32L4_H
+#define __STM32L4_H
+
+#define STM32L4_PAGE_SIZE   0x800
+/* Flash Program ad Erase Controller Register Map */
+#define STM32L4_FPEC_BASE			0x40022000
+#define STM32L4_FLASH_ACR			(STM32L4_FPEC_BASE+0x00)
+#define STM32L4_FLASH_KEYR			(STM32L4_FPEC_BASE+0x08)
+#define STM32L4_FLASH_OPTKEYR		(STM32L4_FPEC_BASE+0x0c)
+#define STM32L4_FLASH_SR			(STM32L4_FPEC_BASE+0x10)
+#define STM32L4_FLASH_CR			(STM32L4_FPEC_BASE+0x14)
+#define STM32L4_FLASH_OPTR			(STM32L4_FPEC_BASE+0x20)
+
+#define STM32L4_FLASH_CR_PG			(1 << 0)
+#define STM32L4_FLASH_CR_PER		(1 << 1)
+#define STM32L4_FLASH_CR_MER1		(1 << 2)
+#define STM32L4_FLASH_CR_PAGE_SHIFT	3
+#define STM32L4_FLASH_CR_BKER		(1 << 11)
+#define STM32L4_FLASH_CR_MER2		(1 << 15)
+#define STM32L4_FLASH_CR_STRT		(1 << 16)
+#define STM32L4_FLASH_CR_OPTSTRT	(1 << 17)
+#define STM32L4_FLASH_CR_FSTPG	 	(1 << 18)
+#define STM32L4_FLASH_CR_EOPIE		(1 << 24)
+#define STM32L4_FLASH_CR_ERRIE		(1 << 25)
+#define STM32L4_FLASH_CR_OBL_LAUNCH	(1 << 27)
+#define STM32L4_FLASH_CR_OPTLOCK	(1 << 30)
+#define STM32L4_FLASH_CR_LOCK		(1 << 31)
+
+#define STM32L4_FLASH_SR_EOP		(1 << 0)
+#define STM32L4_FLASH_SR_OPERR		(1 << 1)
+#define STM32L4_FLASH_SR_PROGERR	(1 << 3)
+#define STM32L4_FLASH_SR_WRPERR		(1 << 4)
+#define STM32L4_FLASH_SR_PGAERR		(1 << 5)
+#define STM32L4_FLASH_SR_SIZERR		(1 << 6)
+#define STM32L4_FLASH_SR_PGSERR		(1 << 7)
+#define STM32L4_FLASH_SR_MSERR		(1 << 8)
+#define STM32L4_FLASH_SR_FASTERR	(1 << 9)
+#define STM32L4_FLASH_SR_RDERR		(1 << 14)
+#define STM32L4_FLASH_SR_OPTVERR	(1 << 15)
+#define STM32L4_FLASH_SR_ERROR_MASK	0xC3FA
+#define STM32L4_FLASH_SR_BSY		(1 << 16)
+
+#define STM32L4_KEY1 0x45670123
+#define STM32L4_KEY2 0xCDEF89AB
+
+#define STM32L4_OPTKEY1 0x08192A3B
+#define STM32L4_OPTKEY2 0x4C5D6E7F
+
+#define STM32L4_SR_ERROR_MASK	0xF2
+#define STM32L4_SR_EOP		0x01
+
+#define STM32L4_OR_DUALBANK		(1 << 21)
+
+#define STM32L4_DBGMCU_IDCODE	0xE0042000
+#define STM32L4_FLASH_SIZE_REG 0x1FFF75E0
+
+#define STM32L4_SIZE_OF_ONE_WRITE    0x1000
+#define STM32L4_ERASE_TIME_IN_WRITES 10
+
+/* 
+ * flash errors returned to flash_target_task
+ * 0x0 - 0x1000   - reserved for target (we can use this pool here)
+ * bit 9 (0x200)  - error while flash erasing. [8..0] represent FLASH_SR[8..0]
+ * bit 10 (0x400) - error while flash writing. [8..0] represent FLASH_SR[8..0]
+ */
+#define STM32L4_ERASE_ERROR_BIT            0x200
+#define STM32L4_FLASH_ERROR_BIT            0x400
+#define STM32L4_ERASE_NEVER_END            0x800
+#define STM32L4_ERROR_ON_FLASH_WRITE_SETUP 0x801
+
+typedef struct CORTEXM_s CORTEXM_t;
+
+typedef struct STM32L4_PRIV_s {
+  CORTEXM_t *cortex;
+} STM32L4_PRIV_t;
+
+int stm32l4_probe(CORTEXM_t *cortexm);
+
+#endif //__STM32L4_H

Makefile

@@ -170,6 +170,7 @@ Src/adiv5/adiv5_jtag.c \
 Src/adiv5/adiv5.c \
 Src/cortexm/cortexm.c \
 Src/cortexm/stm32/stm32f4.c \
+Src/cortexm/stm32/stm32l4.c \
 Src/target.c
 
 # ASM sources

Src/cortexm/cortexm.c

@@ -3,6 +3,7 @@
 #include "adiv5/adiv5.h"
 #include "cortexm/cortexm.h"
 #include "cortexm/stm32/stm32f4.h"
+#include "cortexm/stm32/stm32l4.h"
 
 inline static uint32_t cortexm_read_word(CORTEXM_PRIV_t *priv, uint32_t addr)
 {
@@ -135,6 +136,10 @@ int probe_cortexm(ADIv5_AP_t *ap)
     return 1;
   }
 
+  if(stm32l4_probe(cortexm)){
+    return 1;
+  }
+
   // Non of the targets successful probed. Cleanup
   vPortFree(cortexm->priv);
   vPortFree(cortexm);

Src/cortexm/stm32/flash_stubs/stm32l4_flash_stub.S

@@ -0,0 +1,44 @@
+  .text
+  .syntax unified
+  .cpu cortex-m4
+  .thumb
+
+
+#define STM32_FLASH_CR_OFFSET	0x14	/* offset of CR register in FLASH struct */
+#define STM32_FLASH_SR_OFFSET	0x10	/* offset of SR register in FLASH struct */
+
+_start:
+  ldr r0, _flashbase
+  ldr r1, _addr
+  adr r2, _data
+  ldr r3, _size
+  ldr r5, _cr
+_next:
+  cbz r3, _done
+  str r5, [r0, #STM32_FLASH_CR_OFFSET]
+  ldr r4, [r2]
+  str r4, [r1]
+_wait:
+  ldr  r4, [r0, #STM32_FLASH_SR_OFFSET]
+  tst  r6, #0x10000   /* BSY (bit16) == 1 => operation in progress */
+  bne _wait
+  tst r6, #0xfa       /* PGSERR | PGPERR | PGAERR | WRPERR | PROGERR*/
+  bne _done           /* fail... */
+
+  subs r3, #4
+  adds r1, #4
+  adds r2, #4
+  b _next
+_done:
+  bkpt
+
+_cr:
+  .word 0x00000001 /*(Value to write to FLASH_CR) PG*/
+_flashbase:
+  .word 0x40022000 /* (FPEC_BASE) */
+_addr:
+  .word 0x0
+_size:
+  .word 0x0
+_data:
+  .word 0x0

Src/cortexm/stm32/flash_stubs/stm32l4_flash_stub.o

@@ -218,7 +218,7 @@ static int stm32f4_program(void *priv_void, FIL *file, int *progress)
   UINT br;
   uint8_t unaligned;
   uint32_t addr = 0x8000000; // start of flash memory
-  uint32_t *data = pvPortMalloc(STM32F4_SIZE_OF_ONE_WRITE/sizeof(uint32_t));
+  uint32_t *data = pvPortMalloc(STM32F4_SIZE_OF_ONE_WRITE);
   STM32F4_PRIV_t *priv = priv_void;
   uint16_t result;
   uint32_t file_len = f_size(file);