Verilog constructs

[mik1234mc]

Hello,

we are using some of the great AXI IPs from ZipCPU in our VHDL design. I tried to analyze one using nvc giving me the errors below. Do you plan to support these Verilog constructs in your Verilog implementation? I saw there is already attempt (pull request #1160) for ANSI parameter declaration; but the other constructs are not discussed to be supported right now (always @(*), case, &&, ...). What is the most challenging item to be implemented from the log below?

Best regard,
Michael

https://github.com/ZipCPU/wb2axip/blob/master/rtl/axis2mm.v

$ nvc -a ./axis2mm.v 
** Error: unexpected # while parsing module ANSI header, expecting ;
     > ./axis2mm.v:212
     |
 212 | module  axis2mm #(
     |                 ^ this token was unexpected
** Error: unexpected # while parsing hierarchical instance, expecting identifier
     > ./axis2mm.v:501
     |
 501 |         skidbuffer #(
     |                    ^ this token was unexpected
** Error: unexpected . while parsing hierarchical instance, expecting identifier
     > ./axis2mm.v:506
     |
 506 |                 .OPT_LOWPOWER(OPT_LOWPOWER),
     |                 ^ this token was unexpected
** Error: unexpected # while parsing hierarchical instance, expecting identifier
     > ./axis2mm.v:587
     |
 587 |         skidbuffer #(
     |                    ^ this token was unexpected
** Error: unexpected (* while parsing event control, expecting (
     > ./axis2mm.v:685
     |
 685 |         always @(*)
     |                 ^^ this token was unexpected
** Error: unexpected = while parsing hierarchical instance, expecting identifier
     > ./axis2mm.v:688
     |
 688 |                 w_cmd_abort = (axil_write_ready && awskd_addr == CMD_CONTROL)
     |                             ^ this token was unexpected
** Error: unexpected && while parsing module instantiation, expecting one of , or ;
     > ./axis2mm.v:689
     |
 689 |                         && (wskd_strb[3] && wskd_data[31:24] == ABORT_KEY);
     |                         ^^ this token was unexpected
** Error: unexpected (* while parsing event control, expecting (
     > ./axis2mm.v:711
     |
 711 |         always @(*)
     |                 ^^ this token was unexpected
** Error: unexpected (* while parsing event control, expecting (
     > ./axis2mm.v:822
     |
 822 |         always @(*)
     |                 ^^ this token was unexpected
** Error: unexpected [ while parsing hierarchical instance, expecting identifier
     > ./axis2mm.v:825
     |
 825 |                 wide_address[C_AXI_ADDR_WIDTH-1:0] = cmd_addr;
     |                             ^ this token was unexpected
** Error: unexpected ( while parsing operator assignment, expecting =
     > ./axis2mm.v:915
     |
 915 |                 case(awskd_addr)
     |                     ^ this token was unexpected
** Error: unexpected : while parsing operator assignment, expecting =
     > ./axis2mm.v:918
     |
 918 |                 CMD_ADDRLO:
     |                           ^ this token was unexpected
** Error: unexpected : while parsing bit select, expecting ]
     > ./axis2mm.v:919
     |
 919 |                         cmd_addr <= new_wideaddr[C_AXI_ADDR_WIDTH-1:0];
     |                                                                    ^ this token was unexpected
** Error: unexpected : while parsing bit select, expecting ]
     > ./axis2mm.v:922
     |
 922 |                         cmd_addr <= new_wideaddr[C_AXI_ADDR_WIDTH-1:0];
     |                                                                    ^ this token was unexpected
** Error: unexpected : while parsing expression, expecting one of identifier, string, number, unsigned, real, system task, (, {, -, ~, !, &, |, ^, ++ or --
     > ./axis2mm.v:926
     |
 926 |                         zero_length <= (new_widelen[ADDRLSB +: LGLENW] == 0);
     |                                                              ^ this token was unexpected
** Error: unexpected : while parsing bit select, expecting ]
     > ./axis2mm.v:927
     |
 927 |                         aw_multiple_full_bursts  <= |new_widelen[LGLEN-1:(ADDRLSB+LGMAXBURST)];
     |                                                                         ^ this token was unexpected
** Error: unexpected : while parsing bit select, expecting ]
     > ./axis2mm.v:928
     |
 928 |                         aw_multiple_fixed_bursts <= |new_widelen[LGLEN-1:(ADDRLSB+LGMAX_FIXED_BURST)];
     |                                                                         ^ this token was unexpected
** Error: unexpected begin while parsing hierarchical instance, expecting one of , or )
     > ./axis2mm.v:932
     |
 932 |                         begin
     |                         ^^^^^ this token was unexpected
** Error: unexpected : while parsing expression, expecting one of identifier, string, number, unsigned, real, system task, (, {, -, ~, !, &, |, ^, ++ or --
     > ./axis2mm.v:934
     |
 934 |                         zero_length <= (new_widelen[ADDRLSB +: LGLENW] == 0);
     |                                                              ^ this token was unexpected
** Error: unexpected : while parsing bit select, expecting ]
     > ./axis2mm.v:935
     |
 935 |                         aw_multiple_full_bursts  <= |new_widelen[LGLEN-1:(ADDRLSB+LGMAXBURST)];
     |                                                                         ^ this token was unexpected
** Fatal: too many errors, giving up

[nickg]

I merged that PR and added support for always @(*) but realistically there's quite a lot more to be done before the module above can be used. I'm rewriting the Verilog code generation at the moment which will mean slow progress for a while.

[mik1234mc]

@nickg, thank you for the updates you did over the week to make it working. I see there still other constructs to be resolved (#(), bit selection, case, ). Anyway, I think that the referenced repository is a good source of Verilog resources to verify nvc with. We are looking forward for the upcoming Verilog support updates.

[nickg]

I've made some progress and that file can be parsed now but it contains a lot of constructs that are not currently supported for compilation/simulation.

[mik1234mc]

Thank you for the parser updates. If I understand correctly, it is necessary to map Verilog-parsed structures to existing VHDL compilation/simulation backend, right?

[mik1234mc]

nvc could use for (System)Verilog standard compliance this tool in future: https://github.com/chipsalliance/sv-tests