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fix when parentModule not found
1 parent 6235d8f commit 9b1ecbd

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2 files changed

+4
-2
lines changed

2 files changed

+4
-2
lines changed

compiler/modules/modulegraphs.nim

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -599,7 +599,7 @@ proc parentModule*(g: ModuleGraph; fileIdx: FileIndex): FileIndex =
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if fileIdx.int32 >= 0 and fileIdx.int32 < g.ifaces.len and g.ifaces[fileIdx.int32].module != nil:
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result = fileIdx
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else:
602-
result = g.inclToMod.getOrDefault(fileIdx)
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result = g.inclToMod.getOrDefault(fileIdx, InvalidFileIdx)
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proc markDirty*(g: ModuleGraph; fileIdx: FileIndex) =
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let m = g.getModule fileIdx

compiler/tools/suggest.nim

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -492,7 +492,9 @@ proc executeCmd*(cmd: IdeCmd, file, dirtyfile: AbsoluteFile, line, col: int;
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dirtyfile.isEmpty:
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discard "no need to recompile anything"
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else:
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let modIdx = graph.parentModule(dirtyIdx)
495+
var modIdx = graph.parentModule(dirtyIdx)
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if modIdx == InvalidFileIdx:
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modIdx = dirtyIdx
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graph.markDirty dirtyIdx
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graph.markClientsDirty dirtyIdx
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# partially recompiling the project means that that VM and JIT state

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