trace.tpiu: Count packetizer timeout from start of packet.

Author: zyp

orbtrace/trace/tpiu.py

@@ -148,9 +148,6 @@ def elaborate(self, platform):
         with m.If(timeout_cnt):
             m.d.sync += timeout_cnt.eq(timeout_cnt - 1)
 
-        with m.If(self.input.valid):
-            m.d.sync += timeout_cnt.eq(self.timeout)
-
         with m.FSM() as fsm:
             with m.State('HEADER'):
                 m.d.comb += [
@@ -166,6 +163,7 @@ def elaborate(self, platform):
                         channel.eq(self.input.payload.channel),
                         byte_cnt.eq(0),
                         data.eq(self.input.payload.data),
+                        timeout_cnt.eq(self.timeout),
                     ]
 
             with m.State('DATA'):

tests/test_tpiu.py

@@ -1,5 +1,7 @@
 from sim_helpers import *
 
+import itertools
+
 from amaranth.sim import Simulator, SimulatorContext
 
 from orbtrace.trace import tpiu
@@ -29,6 +31,32 @@ async def timeout(ctx: SimulatorContext):
 
     sim.run()
 
+def test_packetizer_slow_timeout():
+    dut = tpiu.Packetizer(timeout = 1000)
+
+    sim = Simulator(dut)
+    sim.add_clock(1e-6)
+
+    @sim.add_process
+    async def input_testbench(ctx: SimulatorContext):
+        await ctx.tick()
+
+        for i in itertools.count():
+            await stream_put(ctx, dut.input, {'channel': 1, 'data': i & 0xff})
+            await ctx.tick().repeat(100)
+
+    @sim.add_testbench
+    async def output_testbench(ctx: SimulatorContext):
+        assert await recv_packet(ctx, dut.output) == [1, *((i & 0xff) for i in range(10))]
+        assert await recv_packet(ctx, dut.output) == [1, *((i & 0xff) for i in range(10, 20))]
+
+    @sim.add_process
+    async def timeout(ctx: SimulatorContext):
+        await ctx.tick().repeat(10_000)
+        raise TimeoutError('Simulation timed out')
+
+    sim.run()
+
 def test_demux():
     dut = tpiu.TPIUDemux(timeout = 1000)