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draft: support for Hexagon VM
Status: boots linux kernel up to setup_command_line() before panic Hacks: * vmnewmap call not implemented (does get invoked by linux) * vmyield call not implemented (does get invoked by linux) * trap0 not quite right (not _yet_ invoked by linux) Signed-off-by: Brian Cain <[email protected]>
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‎docs/system/hexagon/hvm.rst

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Hexagon Virtual Machine
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=======================
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The hexagon virtual machine is a hypervisor that can partition a single
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Hexagon DSP among multiple guest operating systems, and abstracts the
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specific details of a DSP architectural revision for the sake of consistency
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among generations.
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The ``virt`` machine has Hexagon VM emulation enabled by default.
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Events
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------
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The guest operating system should register the Guest Event Vector Base
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via the ``vmsetvec`` virtual instruction at system startup. The vector table
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and handlers are determined by the guest OS.
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Guests return from event handlers with ``vmrte``. This instruction will restore
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the mode (user versus guest), interrupt enable state, PC, SP.
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.. list-table:: Event types
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:header-rows: 1
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* - Number
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- Name
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- Description
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- Maskable
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- Detail
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* - 0
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- Reserved
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-
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-
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-
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* - 1
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- Machine check event
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- unrecoverable VM state
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- No
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- execution terminates if unhandled
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* - 2
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- General exception
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- internal hardware or software exception
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- No
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-
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* - 3-4
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- Reserved
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-
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-
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-
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* - 5
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- ``trap0``
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- ``trap0`` instruction
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- No
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-
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* - 6
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- Reserved
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-
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-
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-
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* - 7
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- Interrupt
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- external interrupts
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- Yes
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- increasing interrupt numbers have descending priority
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Startup
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-------
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In order to transition to user-mode, the guest OS must set the ``UM`` bit in
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the guest status register and specify the address to start executing in
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user mode in the guest event link register.
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Virtual Instructions
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--------------------
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.. list-table:: Virtual Instructions
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:header-rows: 1
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* - Instruction
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- Behavior
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- Operand
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- Input
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- Output
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* - vmversion
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- returns the VM version
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- 0x0
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- requested VM version
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- provided VM version
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* - vmrte
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- return from event
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- 0x1
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- Event info in g3:0
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- N/A
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* - vmsetvec
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- set event vector
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- 0x2
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- r0 is set to vector table addr
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- r0 is 0 on success, 1 otherwise
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* - vmsetie
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- set interrupt enabled
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- 0x3
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- r0 is set to 1 to enable, 0 to disable
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- previous IE bit is stored as LSB of r0
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* - vmgetie
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- get interrupt enabled
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- 0x4
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- N/A
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- current IE bit is stored as LSB of r0
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* - vmintop
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- interrupt operation
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- 0x5
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- r0 = Interrupt Op, r1-r4: Depends on Op
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- r0 - value depends on operation
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* - vmclrmap
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- clear virtual memory map
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- 0xa
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- r0 = Interrupt Op, r1-r4: Depends on Op
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- r0 - value depends on operation
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* - vmnewmap
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- set new virtual memory map
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- 0xb
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- r0 contains logical address of new segment table, r1 =Type of translations
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- r0 contains 0 on success, otherwise negative error code
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* - vmcache
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- VM cache control: not modeled
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- 0xd
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- r0 contains the operation to be performed, r1 = Starting virtual address, r2 contains the length in bytes
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- r0 contains 0 on success, otherwise -1. Cache behavior is not modeled so this operation always succeeds.
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* - vmgettime
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- Get virtual machine time
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- 0xe
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- N/A
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- r0 contains the least significant 32 bits of timestamp, r1 contains the most significant 32 bits of timestamp
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* - vmsettime
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- Set virtual machine time
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- 0xf
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- r0 contains the least significant 32 bits of timestamp, r1 contains the most significant 32 bits of timestamp
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- N/A
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* - vmwait
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- wait for interrupt
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- 0x10
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- N/A
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- r0 contains the interrupt number of the interrupt waking the guest
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* - vmyield
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- voluntarily yield VM task
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- 0x11
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- N/A
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- N/A
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* - vmstart
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- Create new virtual processor instance
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- 0x12
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- r0 contains the starting execution address, r1 contains the starting stack pointer
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- r0 contains the Virtual processor number of new virtual processor on success, otherwise -1
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* - vmstop
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- terminate current virtual processor instance
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- 0x13
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- N/A
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- N/A
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* - vmvpid
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- get the virtual processor ID
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- 0x14
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- N/A
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- r0 contains the virtual processor number of virtual processor executing the instruction
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* - vmsetregs
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- Set guest registers
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- 0x15
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- r0-3 hold g0-3 values
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- N/A
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* - vmgetregs
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- Get guest registers
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- 0x16
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- N/A
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- r0-3 hold g0-3 values
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* - vmtimerop
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- perform an operation on a system timer
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- 0x18
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- getfreq = 0
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getres = 1
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gettime = 2
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gettimeout = 3
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settimeout = 4
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deltatimeout = 5
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- TBD
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* - vmgetinfo
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- Get system info
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- 0x1a
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- Index of the system info parameter: FIXME another table
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- value of the indicated system info parameter

‎hw/hexagon/hexagon_testboard.c

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@@ -180,6 +180,7 @@ static void hexagon_common_init(MachineState *machine, Rev_t rev,
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CPUHexagonState *env = &cpu->env;
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qemu_register_reset(do_cpu_reset, cpu);
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qdev_prop_set_bit(DEVICE(cpu), "hexagon-vm", true);
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qdev_prop_set_uint32(DEVICE(cpu), "thread-count", machine->smp.cpus);
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qdev_prop_set_uint32(DEVICE(cpu), "config-table-addr",
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cfgExtensions->cfgbase);

‎target/hexagon/cpu.c

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@@ -127,6 +127,7 @@ static Property hexagon_cpu_properties[] = {
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DEFINE_PROP_BOOL("isdben-dfd-enable", HexagonCPU, isdben_dfd_enable, false),
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DEFINE_PROP_BOOL("isdben-trusted", HexagonCPU, isdben_trusted, false),
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DEFINE_PROP_BOOL("isdben-secure", HexagonCPU, isdben_secure, false),
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DEFINE_PROP_BOOL("hexagon-vm", HexagonCPU, hexagon_vm, false),
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DEFINE_PROP_STRING("dump-json-reg-file", HexagonCPU, dump_json_file),
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#endif
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DEFINE_PROP_UINT32("dsp-rev", HexagonCPU, rev_reg, 0),
@@ -573,11 +574,17 @@ static void hexagon_restore_state_to_opc(CPUState *cs,
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#if !defined(CONFIG_USER_ONLY)
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void hexagon_cpu_soft_reset(CPUHexagonState *env)
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{
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CPUState *cs = env_cpu(env);
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HexagonCPU *cpu = HEXAGON_CPU(cs);
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ARCH_SET_SYSTEM_REG(env, HEX_SREG_SSR, 0);
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hexagon_ssr_set_cause(env, HEX_CAUSE_RESET);
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target_ulong evb = ARCH_GET_SYSTEM_REG(env, HEX_SREG_EVB);
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ARCH_SET_THREAD_REG(env, HEX_REG_PC, evb);
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if (cpu->hexagon_vm) {
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ARCH_SET_SYSTEM_REG(env, HEX_SREG_IMASK, 0xffffffff);
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}
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}
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#endif
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‎target/hexagon/cpu.h

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@@ -458,6 +458,7 @@ struct ArchCPU {
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bool isdben_dfd_enable;
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bool isdben_trusted;
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bool isdben_secure;
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bool hexagon_vm;
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#endif
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uint32_t rev_reg;
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bool lldb_compat;

‎target/hexagon/gen_tcg.h

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do { RsV = RsV; } while (0)
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#define fGEN_TCG_Y2_icinva(SHORTCODE) \
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do { RsV = RsV; } while (0)
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#define fGEN_TCG_J2_trap1(SHORTCODE) \
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do { (void) uiV; } while (0)
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#else
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/* data/insn cache ops can raise exceptions */
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#define fGEN_TCG_CACHEOP(HELPER) \

‎target/hexagon/gen_tcg_sys.h

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tcg_gen_extrh_i64_i32(ctx->t_sreg_new_value[HEX_SREG_SGP1], tmp); \
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} while (0)
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#define fGEN_TCG_J2_trap1(SHORTCODE) \
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do { \
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gen_vminst(ctx, uiV); \
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} while (0)
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#endif

‎target/hexagon/genptr.c

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@@ -1862,5 +1862,103 @@ static void gen_vtcm_memcpy(DisasContext *ctx, TCGv dst, TCGv src, TCGv size)
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gen_set_label(finish);
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}
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#if !defined(CONFIG_USER_ONLY)
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enum hex_virt_opc {
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HEX_VIRT_VMVERSION = 0x00,
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HEX_VIRT_VMRETURN = 0x01,
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HEX_VIRT_VMSETVEC = 0x02,
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HEX_VIRT_VMSETIE = 0x03,
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HEX_VIRT_VMGETIE = 0x04,
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HEX_VIRT_VMINTOP = 0x05,
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HEX_VIRT_VMCLRMAP = 0x0A,
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HEX_VIRT_VMNEWMAP = 0x0B,
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HEX_VIRT_VMCACHECTL = 0x0D,
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HEX_VIRT_VMGETTIME = 0x0E,
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HEX_VIRT_VMSETTIME = 0x0F,
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HEX_VIRT_VMWAIT = 0x10,
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HEX_VIRT_VMYIELD = 0x11,
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HEX_VIRT_VMSTART = 0x12,
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HEX_VIRT_VMSTOP = 0x13,
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HEX_VIRT_VMVMPID = 0x14,
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HEX_VIRT_VMSETREGS = 0x15,
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HEX_VIRT_VMGETREGS = 0x16,
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HEX_VIRT_VMTIMEROP = 0x18,
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HEX_VIRT_VMPMUCTRL = 0x19,
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HEX_VIRT_VMGETINFO = 0x1A,
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};
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#include "hex_vm.c.inc"
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static void gen_vminst(DisasContext *ctx, int operand)
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{
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if (!ctx->has_hexagon_vm) {
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/* FIXME: raise an exception instead? */
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return;
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}
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/* TODO: when swapping guest/user, must exchange GOSP, R29... */
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switch (operand) {
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case HEX_VIRT_VMVERSION:
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gen_vmversion();
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break;
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case HEX_VIRT_VMSETREGS:
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gen_vmsetregs();
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break;
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case HEX_VIRT_VMGETREGS:
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gen_vmgetregs();
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break;
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case HEX_VIRT_VMSETIE:
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gen_vmsetie();
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break;
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case HEX_VIRT_VMGETIE:
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gen_vmgetie();
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break;
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case HEX_VIRT_VMVMPID:
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gen_vmvpid();
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break;
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case HEX_VIRT_VMCACHECTL:
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gen_vmcache();
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break;
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case HEX_VIRT_VMSTOP:
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gen_vmstop();
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break;
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case HEX_VIRT_VMYIELD:
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gen_vmyield();
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break;
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case HEX_VIRT_VMGETTIME:
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gen_vmgettime();
1930+
break;
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case HEX_VIRT_VMRETURN:
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gen_vmrte();
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break;
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case HEX_VIRT_VMCLRMAP:
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gen_vmclrmap();
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break;
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case HEX_VIRT_VMNEWMAP:
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gen_vmnewmap();
1939+
break;
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case HEX_VIRT_VMSETVEC:
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gen_vmsetvec();
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break;
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case HEX_VIRT_VMINTOP:
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gen_vmintop();
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break;
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case HEX_VIRT_VMGETINFO:
1947+
gen_vmgetinfo();
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break;
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case HEX_VIRT_VMTIMEROP:
1950+
gen_vmtimerop();
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break;
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default:
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/* FIXME: Invalid packet exception? */
1956+
fprintf(stderr, "Unknown VM instruction 0x%08x\n", operand);
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g_assert_not_reached();
1958+
break;
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}
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}
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#endif
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#include "tcg_funcs_generated.c.inc"
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#include "tcg_func_table_generated.c.inc"

‎target/hexagon/helper.h

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@@ -148,6 +148,7 @@ DEF_HELPER_2(greg_read, i32, env, i32)
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DEF_HELPER_2(greg_read_pair, i64, env, i32)
149149
DEF_HELPER_1(inc_gcycle_xt, void, env)
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DEF_HELPER_3(modify_ssr, void, env, i32, i32)
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DEF_HELPER_2(modify_syscfg, void, env, i32)
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DEF_HELPER_1(pending_interrupt, void, env)
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DEF_HELPER_3(raise_stack_overflow, void, env, i32, i32)
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DEF_HELPER_1(resched, void, env)

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