draft: Implement vmnewmap inst

androm3da · androm3da · commit d83a7e31d9dd · 2024-07-10T15:31:39.000-07:00
FIXME: while following the spec for vmnewmap and the kernel source, I thought
I understood the expected behavior but based on what I've seen so far I
think it's not yet implemented correctly.

Signed-off-by: Brian Cain &lt;bcain@quicinc.com&gt;
diff --git a/docs/system/hexagon/hvm.rst b/docs/system/hexagon/hvm.rst
@@ -117,7 +117,7 @@ Virtual Instructions
    * - vmnewmap
      - set new virtual memory map
      - 0xb
-     - r0 contains logical address of new segment table, r1 =Type of translations
+     - r0 contains logical address of new segment table, r1 = type of translations: 0 indicates a logical address of a zero-terminated linear list, 1 indicates a set of page tables.
      - r0 contains 0 on success, otherwise negative error code
    * - vmcache
      - VM cache control: not modeled
diff --git a/target/hexagon/helper.h b/target/hexagon/helper.h
@@ -51,6 +51,8 @@ DEF_HELPER_2(nmi, void, env, i32)
 DEF_HELPER_3(setprio, void, env, i32, i32)
 DEF_HELPER_2(start, void, env, i32)
 DEF_HELPER_1(stop, void, env)
+
+DEF_HELPER_4(vmnewmap, void, env, i32, i32, i32)
 #endif
 
 DEF_HELPER_5(check_vtcm_memcpy, void, env, i32, i32, i32, i32)
diff --git a/target/hexagon/hex_vm.c.inc b/target/hexagon/hex_vm.c.inc
@@ -43,8 +43,7 @@ static inline void gen_vmsetie(void)
 
     TCGv new_syscfg = tcg_temp_new();
     tcg_gen_deposit_tl(new_syscfg, hex_g_sreg[HEX_SREG_SYSCFG],
-                       hex_gpr[HEX_REG_R00],
-                       reg_field_info[SYSCFG_GIE].offset,
+                       hex_gpr[HEX_REG_R00], reg_field_info[SYSCFG_GIE].offset,
                        reg_field_info[SYSCFG_GIE].width);
     gen_helper_modify_syscfg(tcg_env, new_syscfg);
     tcg_gen_mov_tl(hex_gpr[HEX_REG_R00], old_ie);
@@ -96,7 +95,8 @@ static inline void gen_vmyield(void)
 }
 static inline void gen_vmnewmap(void)
 {
-    /* g_assert_not_reached(); HACK FIXME */
+    gen_helper_vmnewmap(tcg_env, hex_gpr[HEX_REG_R01], hex_gpr[HEX_REG_R00],
+                        hex_gpr[HEX_REG_R02]);
 }
 static inline void gen_vmclrmap(void)
 {
@@ -142,18 +142,14 @@ static inline void gen_vmintop(void)
                        local_en);
     tcg_gen_brcondi_tl(TCG_COND_EQ, hex_gpr[HEX_REG_R00], VMINTOP_LOCDIS,
                        local_dis);
-    tcg_gen_brcondi_tl(TCG_COND_EQ, hex_gpr[HEX_REG_R00], VMINTOP_GET,
-                       get);
+    tcg_gen_brcondi_tl(TCG_COND_EQ, hex_gpr[HEX_REG_R00], VMINTOP_GET, get);
     tcg_gen_brcondi_tl(TCG_COND_EQ, hex_gpr[HEX_REG_R00], VMINTOP_AFFINITY,
                        affinity);
-    tcg_gen_brcondi_tl(TCG_COND_EQ, hex_gpr[HEX_REG_R00], VMINTOP_PEEK,
-                       peek);
+    tcg_gen_brcondi_tl(TCG_COND_EQ, hex_gpr[HEX_REG_R00], VMINTOP_PEEK, peek);
     tcg_gen_brcondi_tl(TCG_COND_EQ, hex_gpr[HEX_REG_R00], VMINTOP_STATUS,
                        status);
-    tcg_gen_brcondi_tl(TCG_COND_EQ, hex_gpr[HEX_REG_R00], VMINTOP_POST,
-                       post);
-    tcg_gen_brcondi_tl(TCG_COND_EQ, hex_gpr[HEX_REG_R00], VMINTOP_CLEAR,
-                       clear);
+    tcg_gen_brcondi_tl(TCG_COND_EQ, hex_gpr[HEX_REG_R00], VMINTOP_POST, post);
+    tcg_gen_brcondi_tl(TCG_COND_EQ, hex_gpr[HEX_REG_R00], VMINTOP_CLEAR, clear);
 
     TCGv irq_mask = tcg_temp_new();
     TCGv set_mask = tcg_temp_new();
@@ -286,8 +282,7 @@ static inline void gen_vmrte(void)
                        reg_field_info[GSR_IE].offset,
                        reg_field_info[GSR_IE].width);
     tcg_gen_deposit_tl(hex_g_sreg[HEX_SREG_SYSCFG], hex_g_sreg[HEX_SREG_SYSCFG],
-                       gsr_ie,
-                       reg_field_info[SYSCFG_GIE].offset,
+                       gsr_ie, reg_field_info[SYSCFG_GIE].offset,
                        reg_field_info[SYSCFG_GIE].width);
 
     TCGv gsr_um = tcg_temp_new();
diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c
@@ -2708,6 +2708,147 @@ void HELPER(check_vtcm_memcpy)(CPUHexagonState *env, uint32_t dst, uint32_t src,
     }
 }
 
+
+typedef enum {
+    HEXVM_ENTRY_DIRECTORY,
+    HEXVM_ENTRY_TABLE,
+    HEXVM_ENTRY_INVALID,
+} HexVMPTEEntryType;
+
+typedef struct {
+    HexVMPTEEntryType entry_type;
+    uint32_t page_size_bytes;
+    uint32_t l2_entries;
+    uint32_t addr_start_bit;
+    uint32_t addr_bit_count;
+} l1_pte_types;
+
+
+#define COPY_FIELD(dest, src, FIELD)                                  \
+    dest = deposit64(dest, reg_field_info[FIELD].offset,              \
+                     reg_field_info[FIELD].width,                     \
+                     extract32(src, reg_field_info[VM##FIELD].offset, \
+                               reg_field_info[VM##FIELD].width))
+
+void HELPER(vmnewmap)(CPUHexagonState *env, uint32_t map_type, uint32_t input,
+                      uint32_t tlb_inval)
+{
+    CPUState *cs = env_cpu(env);
+    static const l1_pte_types PTE_TYPES[] = {
+        /* FIXME: off-by-one bit start/count? */
+        { HEXVM_ENTRY_DIRECTORY, 4 * 1024, 1024, 12, 20, },
+        { HEXVM_ENTRY_DIRECTORY, 16 * 1024, 256, 10, 22, },
+        { HEXVM_ENTRY_DIRECTORY, 64 * 1024, 64, 8, 24, },
+        { HEXVM_ENTRY_DIRECTORY, 256 * 1024, 16, 6, 26, },
+        { HEXVM_ENTRY_DIRECTORY, 1024 * 1024, 4, 4, 28, },
+        { HEXVM_ENTRY_TABLE, 4 * 1024 * 1024, 0, 0, 0, },
+        { HEXVM_ENTRY_TABLE, 16 * 1024 * 1024, 0, 0, 0, },
+        { HEXVM_ENTRY_INVALID, 0, 0, 0, 0, },
+    };
+    static const int TYPE_MASK = 0x07;
+
+    bool fail = false;
+
+    /*
+     * LARGE PARTS OF THE CODE BELOW APPEARS TO BE WRONG. IT DOES
+     * NOT WORK AS EXPECTED.
+     */
+
+    switch (map_type) {
+    case 0:
+        /* FIXME: linear list... */
+        g_assert_not_reached();
+        break;
+    case 1:
+        ;
+        const l1_pte_types e = PTE_TYPES[input & TYPE_MASK];
+        switch (e.entry_type) {
+        case HEXVM_ENTRY_DIRECTORY:
+            ;
+            uint32_t l2_table_la = input & ~(0x0f);
+            /* FIXME check the table addr alignment, should match table size */
+            uint32_t i;
+            for (i = 0; i < e.l2_entries; i++) {
+                /* L2 entries are 32-bits long */
+                uint32_t entry;
+                uint32_t offset = i * sizeof(entry);
+                address_space_read(cs->as, l2_table_la + offset,
+                                   MEMTXATTRS_UNSPECIFIED, &entry,
+                                   sizeof(entry));
+
+                /*
+                 * How to know what terminates the list?
+                 * linear lists are null-terminated.
+                 */
+                if (entry == 0) {
+                    break;
+                }
+                uint64_t phys_entry = 0;
+                deposit64(phys_entry, reg_field_info[PTE_V].offset,
+                          reg_field_info[PTE_V].width, true);
+
+                COPY_FIELD(phys_entry, entry, PTE_R);
+                COPY_FIELD(phys_entry, entry, PTE_W);
+                COPY_FIELD(phys_entry, entry, PTE_X);
+                COPY_FIELD(phys_entry, entry, PTE_U);
+                COPY_FIELD(phys_entry, entry, PTE_C);
+                uint32_t logical_page_num =
+                    extract32(entry, e.addr_start_bit, e.addr_bit_count);
+                /* COPY_FIELD(phys_entry, entry, PTE_VPN); */
+                phys_entry =
+                    deposit64(phys_entry, reg_field_info[PTE_PPD].offset,
+                              reg_field_info[PTE_PPD].width, logical_page_num);
+                phys_entry =
+                    deposit64(phys_entry, reg_field_info[PTE_VPN].offset,
+                              reg_field_info[PTE_VPN].width, logical_page_num);
+
+                bool r = extract32(entry, reg_field_info[VMPTE_R].offset,
+                                   reg_field_info[VMPTE_R].width);
+                bool w = extract32(entry, reg_field_info[VMPTE_W].offset,
+                                   reg_field_info[VMPTE_W].width);
+                bool x = extract32(entry, reg_field_info[VMPTE_X].offset,
+                                   reg_field_info[VMPTE_X].width);
+                g_assert(r || w || x);
+
+                switch (e.page_size_bytes) {
+                case 4 * 1024:
+                    phys_entry = deposit64(phys_entry, 0, 1, true);
+                    break;
+                case 16 * 1024:
+                    phys_entry = deposit64(
+                        phys_entry, reg_field_info[PTE_PPD].offset, 1, true);
+                    break;
+                default:
+                    g_assert_not_reached();
+                    break;
+                }
+
+                /*
+                 * How to know which base TLB index to use?
+                 * Keep some state for where the last added one was?
+                 */
+                hex_tlbw(env, i, phys_entry);
+            }
+            g_assert_not_reached();
+
+            break;
+        case HEXVM_ENTRY_TABLE:
+            g_assert_not_reached();
+            break;
+        case HEXVM_ENTRY_INVALID:
+        default:
+            /* FIXME raise protection violation exception event */
+            fail = true;
+            break;
+        }
+        break;
+    default:
+        fail = true;
+        break;
+    }
+    env->gpr[HEX_REG_R00] = fail ? -1 : 0;
+}
+
 /* These macros can be referenced in the generated helper functions */
 #define warn(...) /* Nothing */
 #define fatal(...) g_assert_not_reached();
diff --git a/target/hexagon/reg_fields_def.h.inc b/target/hexagon/reg_fields_def.h.inc
@@ -211,3 +211,14 @@ DEF_REG_FIELD(PMUCFG_THMASK, 16, 3)
 DEF_REG_FIELD(GSR_UM,  31, 1)
 DEF_REG_FIELD(GSR_IE,  30, 1)
 DEF_REG_FIELD(GSR_CAUSE,  0, 16)
+
+/* Hexagon VM L2 Page table entries */
+
+/* VPN aka LPN: */
+DEF_REG_FIELD(VMPTE_VPN, 12, 20)
+DEF_REG_FIELD(VMPTE_X, 11, 1)
+DEF_REG_FIELD(VMPTE_W, 10, 1)
+DEF_REG_FIELD(VMPTE_R, 9, 1)
+DEF_REG_FIELD(VMPTE_C, 6, 3)
+DEF_REG_FIELD(VMPTE_U, 5, 1)
+DEF_REG_FIELD(VMPTE_TRUSTED, 4, 1)
