multicore_fifo_get_status and multicore_fifo_clear_irq functions do not make sense. #459
Description
I have successfully tested the blocking (multicore_fifo_pop_blocking and multicore_fifo_push_blocking) and non-blocking (multicore_fifo_rvalid and multicore_fifo_wready) functions and I have managed to replicate the behaviour as per SDK.
I am now reading the Pico C SDK documentation about the function multicore_fifo_get_status and the description about the setting of bits does not quite make sense to me.
Maybe someone can help.
So am I correct in my understanding that the setting of bit 0 to 1 is equivalent to multicore_fifo_rvalid returning true and similarly if bit 1 is set to 1 that this is equivalent to multicore_fifo_wready returning true.
Then my point of confusion.
According to the documentation, for bit 2 to be set (and remain set, as in it's sticky) means that the TX FIFO was written to when full and that this write was ignored by the FIFO. Does that mean that somehow the multicore_fifo_push_blocking function did not work (as in it did not block the write event). If that is the case is this not an error code.
Similarly for bit 3 to be set (and remain set, as in it's sticky) means that the RX FIFO was read when empty, as in multicore_fifo_pop_blocking did not block, and thus this read was ignored by the FIFO.
Then if bits 2 and bits 3 are sticky, and then remain set, how do these bits then clear assuming that this is not automated. Is that not the function of multicore_fifo_clear_irq or is there some other method of clearing, which is not documented.