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feat: smctr csr
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‎spec/std/isa/csr/Smctr/mctrctl.yaml‎

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# Copyright (c) Muhammad Abdullah — 10xEngineers
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# SPDX-License-Identifier: BSD-3-Clause-Clear
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# yaml-language-server: $schema=../../../../schemas/csr_schema.json
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$schema: csr_schema.json#
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kind: csr
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name: mctrctl
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long_name: Machine Control Transfer Records Control Register
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address: 0x34E
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writable: true
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priv_mode: M
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length: 64
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definedBy: Smctr
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description: |
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The `mctrctl` register enables and configures the Control Transfer Records capability in M mode.
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fields:
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U:
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location: 0
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type: RW
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reset_value: UNDEFINED_LEGAL
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description: |
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Enable transfer recording in the User mode.
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S:
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location: 1
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type: RW
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reset_value: UNDEFINED_LEGAL
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description: |
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Enable transfer recording in the Supervisor mode.
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M:
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location: 2
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type: RW
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reset_value: UNDEFINED_LEGAL
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description: |
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Enable transfer recording in the Machine mode.
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RASEMU:
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location: 7
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type: RW
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reset_value: UNDEFINED_LEGAL
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description: |
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When set, it enables RAS (Return Address Stack) Emulation Mode.
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STE:
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location: 8
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type: RW
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reset_value: UNDEFINED_LEGAL
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description: |
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Enables recording of traps to S-mode when S=0.
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MTE:
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location: 9
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type: RW
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reset_value: UNDEFINED_LEGAL
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description: |
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Enables recording of traps to M-mode when M=0.
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BPFRZ:
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location: 11
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type: RW
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reset_value: UNDEFINED_LEGAL
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description: |
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Set `sctrstatus.FROZEN` on a breakpoint exception that traps to M or S mode.
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LCOFIFRZ:
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location: 12
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type: RW
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reset_value: UNDEFINED_LEGAL
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description: |
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Set `sctrstatus.FROZEN` on local-counter-overflow interrupt (LCOFI) that traps
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to M or S mode.
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definedBy: Sscofpmf
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EXCINH:
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location: 33
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type: RW
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reset_value: UNDEFINED_LEGAL
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description: |
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When set, it inhibits recording of exceptions.
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INTRINH:
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location: 34
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type: RW
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reset_value: UNDEFINED_LEGAL
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description: |
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When set, it inhibits recording of interrupts.
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TRETINH:
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location: 35
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type: RW
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reset_value: UNDEFINED_LEGAL
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description: |
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When set, it inhibits recording of trap returns.
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NTBREN:
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location: 36
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type: RW
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reset_value: UNDEFINED_LEGAL
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description: |
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When set, it enables recording of not-taken branches.
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TKBRINH:
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location: 37
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type: RW
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reset_value: UNDEFINED_LEGAL
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description: |
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When set, it inhibits recording of taken branches.
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INDCALLINH:
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location: 40
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type: RW
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reset_value: UNDEFINED_LEGAL
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description: |
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When set, it inhibits recording of indirect calls.
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DIRCALLINH:
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location: 41
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type: RW
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reset_value: UNDEFINED_LEGAL
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description: |
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When set, it inhibits recording of direct calls.
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INDJMPINH:
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location: 42
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type: RW
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reset_value: UNDEFINED_LEGAL
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description: |
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When set, it inhibits recording of indirect jumps (without linkage).
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DIRJMPINH:
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location: 43
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type: RW
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reset_value: UNDEFINED_LEGAL
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description: |
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When set, it inhibits recording of direct jumps (without linkage).
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CORSWAPINH:
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location: 44
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type: RW
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reset_value: UNDEFINED_LEGAL
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description: |
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When set, it inhibits recording of co-routine swaps.
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RETINH:
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location: 45
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type: RW
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reset_value: UNDEFINED_LEGAL
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description: |
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When set, it inhibits recording of function returns.
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INDLJMPINH:
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location: 46
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type: RW
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reset_value: UNDEFINED_LEGAL
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description: |
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When set, it inhibits recording of other indirect jumps (with linkage).
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DIRLJMPINH:
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location: 47
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type: RW
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reset_value: UNDEFINED_LEGAL
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description: |
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When set, it inhibits recording of other direct jumps (with linkage).
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CUSTOM:
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location: 63-60
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type: RW
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reset_value: UNDEFINED_LEGAL
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description: |
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WARL bits designated for custom use. The value 0 must correspond to standard behavior.
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sw_read(): |
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Bits<12> mctrctl_addr = 0x34E;
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Bits<64> mctrctl_mask = 0x787F9F80000FC7;
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Csr csr_handle = direct_csr_lookup(mctrctl_addr);
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if (!csr_handle.valid) {
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unimplemented_csr($encoding);
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}
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return (CSR[mctrctl] & mctrctl_mask);

‎spec/std/isa/csr/Smctr/sctrctl.yaml‎

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# Copyright (c) Muhammad Abdullah — 10xEngineers
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# SPDX-License-Identifier: BSD-3-Clause-Clear
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# yaml-language-server: $schema=../../../../schemas/csr_schema.json
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$schema: csr_schema.json#
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kind: csr
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name: sctrctl
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long_name: Supervisor Control Transfer Records Control Register
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address: 0x14E
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writable: true
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priv_mode: S
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length: 64
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definedBy: Smctr
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description: The `sctrctl` register enables and configures the Control Transfer Records capability in S mode.
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fields:
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U:
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location: 0
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type: RW
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alias: mctrctl.U
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reset_value: UNDEFINED_LEGAL
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description: |
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Enable transfer recording in the User mode.
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S:
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location: 1
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type: RW
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alias: mctrctl.S
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reset_value: UNDEFINED_LEGAL
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description: |
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Enable transfer recording in the Supervisor mode.
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RASEMU:
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location: 7
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type: RW
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alias: mctrctl.RASEMU
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reset_value: UNDEFINED_LEGAL
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description: |
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When set, it enables RAS (Return Address Stack) Emulation Mode.
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STE:
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location: 8
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type: RW
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alias: mctrctl.STE
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reset_value: UNDEFINED_LEGAL
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description: |
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Enables recording of traps to S-mode when S=0.
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BPFRZ:
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location: 11
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type: RW
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alias: mctrctl.BPFRZ
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reset_value: UNDEFINED_LEGAL
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description: |
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Set `sctrstatus.FROZEN` on a breakpoint exception that traps to M or S mode.
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LCOFIFRZ:
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location: 12
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type: RW
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alias: mctrctl.LCOFIFRZ
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reset_value: UNDEFINED_LEGAL
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description: |
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Set `sctrstatus.FROZEN` on local-counter-overflow interrupt (LCOFI) that traps
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to M or S mode.
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definedBy: Sscofpmf
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EXCINH:
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location: 33
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type: RW
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alias: mctrctl.EXCINH
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reset_value: UNDEFINED_LEGAL
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description: |
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When set, it inhibits recording of exceptions.
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INTRINH:
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location: 34
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type: RW
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alias: mctrctl.INTRINH
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reset_value: UNDEFINED_LEGAL
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description: |
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When set, it inhibits recording of interrupts.
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TRETINH:
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location: 35
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type: RW
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alias: mctrctl.TRETINH
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reset_value: UNDEFINED_LEGAL
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description: |
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When set, it inhibits recording of trap returns.
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NTBREN:
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location: 36
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type: RW
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alias: mctrctl.NTBREN
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reset_value: UNDEFINED_LEGAL
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description: |
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When set, it enables recording of not-taken branches.
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TKBRINH:
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location: 37
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type: RW
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alias: mctrctl.TKBRINH
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reset_value: UNDEFINED_LEGAL
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description: |
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When set, it inhibits recording of taken branches.
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INDCALLINH:
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location: 40
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type: RW
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alias: mctrctl.INDCALLINH
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reset_value: UNDEFINED_LEGAL
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description: |
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When set, it inhibits recording of indirect calls.
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DIRCALLINH:
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location: 41
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type: RW
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alias: mctrctl.DIRCALLINH
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reset_value: UNDEFINED_LEGAL
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description: |
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When set, it inhibits recording of direct calls.
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INDJMPINH:
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location: 42
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type: RW
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alias: mctrctl.INDJMPINH
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reset_value: UNDEFINED_LEGAL
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description: |
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When set, it inhibits recording of indirect jumps (without linkage).
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DIRJMPINH:
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location: 43
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type: RW
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alias: mctrctl.DIRJMPINH
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reset_value: UNDEFINED_LEGAL
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description: |
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When set, it inhibits recording of direct jumps (without linkage).
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CORSWAPINH:
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location: 44
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type: RW
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alias: mctrctl.CORSWAPINH
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reset_value: UNDEFINED_LEGAL
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description: |
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When set, it inhibits recording of co-routine swaps.
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RETINH:
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location: 45
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type: RW
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alias: mctrctl.RETINH
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reset_value: UNDEFINED_LEGAL
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description: |
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When set, it inhibits recording of function returns.
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INDLJMPINH:
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location: 46
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type: RW
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alias: mctrctl.INDLJMPINH
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reset_value: UNDEFINED_LEGAL
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description: |
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When set, it inhibits recording of other indirect jumps (with linkage).
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DIRLJMPINH:
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location: 47
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type: RW
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alias: mctrctl.DIRLJMPINH
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reset_value: UNDEFINED_LEGAL
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description: |
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When set, it inhibits recording of other direct jumps (with linkage).
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CUSTOM:
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location: 63-60
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type: RW
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alias: mctrctl.CUSTOM
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reset_value: UNDEFINED_LEGAL
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description: |
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WARL bits designated for custom use. The value 0 must correspond to standard behavior.
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sw_read(): |
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Bits<12> sctrctl_addr = 0x14E;
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Bits<64> sctrctl_mask = 0x787F9F80000DC3;
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Csr csr_handle = direct_csr_lookup(sctrctl_addr);
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if (!csr_handle.valid) {
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unimplemented_csr($encoding);
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}
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return (CSR[mctrctl] & sctrctl_mask);

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