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Funtional verilog ping_pong simulator
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6 files changed

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README.md

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Original file line numberDiff line numberDiff line change
@@ -8,12 +8,13 @@ The eventual goal(?) is to build a general-purpose processor integrated with sim
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## Sample Programs
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* Ping Pong
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* 16x8 LED display with W/S/Up/Down keyboard controller
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* Source: [ping_pong.asm](programs/ping_pong.asm)
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* Generate resolved assembly: `python3 -m planner asm -r programs/ping_pong.asm` [[example](output/programs/ping_pong_resolved.asm)]
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* Generate binary: `python3 -m planner asm -b programs/ping_pong.asm` [[example](output/programs/ping_pong.bin)]
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* Run on emulator: `python3 -m planner compile_and_execute ping_pong`
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* 16x8 LED display with W/S/Up/Down keyboard controller
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* Run on python emulator: `python3 -m planner compile_and_execute ping_pong`
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* ![image](https://github.com/user-attachments/assets/9fa2f68f-73ae-465c-a29c-cc92b0dc421a)
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* Run on verilog emulator: `make verilog_simulate`
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## Design
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emulator/Makefile.mk

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@@ -3,9 +3,9 @@ SRC_EMULATOR = $(SRC_DIR)/emulator
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.PHONY: verilog_modules test_verilog_modules verilog_data_prerequisites verilog_simulate
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$(BUILD_EMULATOR)/%_test: $(SRC_EMULATOR)/%_test.v
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$(BUILD_EMULATOR)/%_test: $(SRC_EMULATOR)/%_test.v $(SRC_EMULATOR)/%.v
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mkdir -p $(dir $@)
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iverilog -o $@ $^
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iverilog -o $@ $<
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verilog_modules: $(BUILD_EMULATOR)/executable_chipset $(patsubst $(SRC_EMULATOR)/%_test.v, $(BUILD_EMULATOR)/%_test, $(shell find $(SRC_EMULATOR) -name '*_test.v'))
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mkdir -p $(BUILD_EMULATOR)/io

emulator/module/ipc.cpp

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This file was deleted.

emulator/seq/io_devices.v

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@@ -31,7 +31,7 @@ module IODevices(
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ROM_PINGPONG prom(.out(prom_value), .address(value_in[15:0]));
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reg[31:0] _value;
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always @(device_id) begin
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always @(clk) begin
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case (device_id)
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// TODO: Is it ok to use continous circuit with value_in as address?
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`PROM_ID: _value <= prom_value;

emulator/seq/io_devices_test.v

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@@ -27,6 +27,10 @@ module IODevices_test;
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clk = 0;
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# 10
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device_id = 3; // const
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# 1
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clk = 1;
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# 1
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clk = 0;
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# 5
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$display("IO_DEVICES_TEST: device_id=%b value_out=%b", device_id, value_out);
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if (value_out !== INPUT1) begin
@@ -36,6 +40,10 @@ module IODevices_test;
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# 10
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device_id = 2; // PROM
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value_in = 0;
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# 1
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clk = 1;
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# 1
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clk = 0;
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# 10
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$display("IO_DEVICES_TEST: device_id=%b value_out=%b", device_id, value_out);
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if (value_out === INPUT1) begin

planner/sim/verilog_devices.py

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Original file line numberDiff line numberDiff line change
@@ -1,25 +1,18 @@
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from planner.sim import devices
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import threading
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import os
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from ctypes import cdll, c_int, CFUNCTYPE
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IO_DEVICES = 16
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LIB = "build/emulator/module/libipc.so"
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INPUT_FILE = "/tmp/ourpc_input.txt"
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IO_DEVICES = 8
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INPUT_FILE = "/tmp/ourpc_input"
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global_io = None
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@CFUNCTYPE(None, c_int, c_int)
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def handle_output(pid, value):
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print("Got PID(%d) Value(%d)" % (pid, value))
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global_io.output_devices[pid].update(value)
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def io_loop(hh):
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def io_loop():
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while True:
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s = input()
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print(s)
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s=s.split()
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if s[0]=="IPC":
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pid,value = s[1],s[2]
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pid,value = s[1], s[2]
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pid=int(pid, 16)
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value=int(value, 16)
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print("Got PID(%d) Value(%d)" % (pid, value))
@@ -34,12 +27,10 @@ def __init__(self):
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self.input_devices = [None]*IO_DEVICES
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self.output_devices = [None]*IO_DEVICES
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# lib = cdll.LoadLibrary(LIB)
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# lib.fast_io_loop
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global global_io
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global_io = self
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self.mu = threading.Lock()
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self.t = threading.Thread(target=io_loop, args=[handle_output])
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self.t = threading.Thread(target=io_loop, args=[])
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def run(self, blocking=True):
@@ -57,13 +48,10 @@ def write_input(self, new_val, old_val):
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with open(INPUT_FILE, "w") as f:
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f.write(data_str)
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def set_input_device(self, index: int, d: devices.InputDevice):
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d.add_change_handler(self.write_input)
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self.input_devices[index] = d
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def set_output_device(self, index: int, d: devices.Device):
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self.output_devices[index] = d
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