diff --git a/draft/display.circ b/draft/display.circ deleted file mode 100644 index d9ac786..0000000 --- a/draft/display.circ +++ /dev/null @@ -1,205 +0,0 @@ - - - This file is intended to be loaded by Logisim-evolution v3.8.0(https://github.com/logisim-evolution/). - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - addr/data: 8 8 -3c 66 3 3 73 66 7c 0 -0 0 1e 30 3e 33 6e 0 -0 0 6e 33 33 3e 30 1f -0 0 1e 30 3e 33 6e 0 -0 0 1f 4*33 9*0 67 66 36 -1e 36 66 67 0 0 0 4*33 -6e 0 0 0 33 7f 7f 6b -63 0 0 0 1e 30 3e 33 -6e 0 0 0 3b 6e 66 6 -f - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/planner/pcb/validator/mod_ram.py b/planner/pcb/validator/mod_ram.py new file mode 100644 index 0000000..5f14cc8 --- /dev/null +++ b/planner/pcb/validator/mod_ram.py @@ -0,0 +1,43 @@ +from planner.pcb.validator import rasp + + +# From module prespective +PIN_ADDRESS_IN = list(range(2,10)) +PIN_VALUE_IN = list(range(10,18)) +PIN_VALUE_OUT = list(range(18,26)) +PIN_IS_WRITE = 26 +PIN_CLK = 27 + + +class ModRamValidator: + '''Validate RAM sub-module. + + RAM sub-module is equally divided + - At 1/4 at value line. + - At 1/2 at address line. + + RAM module will export + - Input: 2*8 bits address line + - Input: 4*8 bits value line + - Output: 32 bits value line + - Input: 1 bit is_write + - Input: 1 bit clk + ''' + def __init__(self, r: rasp.PiController): + self.r = r + + def setup(self): + # from validator prespective + address_out = [self.r.assign_out(p) for p in PIN_ADDRESS_IN] + value_out = [self.r.assign_out(p) for p in PIN_VALUE_IN] + value_in = [self.r.assign_in(p) for p in PIN_VALUE_OUT] + is_write_out = self.r.assign_out(PIN_IS_WRITE) + is_clk = self.r.assign_out(PIN_CLK) + + def execute_write(self, address: int, value: int): + assert address >= 0 and address < (1<<8) + assert value >=0 and value < (1<<8) + + + + diff --git a/planner/pcb/validator/rasp.py b/planner/pcb/validator/rasp.py new file mode 100644 index 0000000..f4271e6 --- /dev/null +++ b/planner/pcb/validator/rasp.py @@ -0,0 +1,53 @@ +import atexit + +import RPi.GPIO as GPIO + +RESERVED_PINS = set([0, 1]) + +class PiPin: + def __init__(self, pin: int): + assert pin not in RESERVED_PINS + assert pin in list(range(28)) + self.pin = pin + +class PiOut(PiPin): + def __init__(self, *args): + super().__init__(*args) + GPIO.setup(self.pin, GPIO.OUT) + + def set(self, high: bool): + GPIO.output(self.pin, GPIO.HIGH if high else GPIO.LOW) + +class PiInput(PiPin): + def __init__(self, *args): + super().__init__(*args) + GPIO.setup(self.pin, GPIO.IN) + + def is_high(self): + return GPIO.input(self.pin) == GPIO.HIGH + + +class PiController: + def __init__(self): + self.pins = [None]*28 # pytype: List[PiPin | None] + self.setup() + + def setup(self): + def cleanup(): + GPIO.cleanup() + GPIO.setmode(GPIO.BCM) + GPIO.setup + atexit.register(cleanup) + + def assign_out(self, index: int): + assert self.pins[index] is None + out = PiOut(index) + self.pins[index] = out + return out + + def assign_in(self, index: int): + assert index not in self.reserved_pins + assert self.pins[index] is None + input = PiInput(index) + self.pins[index] = input + return input