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Manually apply kevinpt#17
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hdlparse/verilog_parser.py

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -14,34 +14,34 @@
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'root': [
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# patterns
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# pattern, action, new_state
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(r'\bmodule\s+(\w+)\s*', 'module', 'module'),
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(r'\bmodule\s*(\w+)\s*', 'module', 'module'),
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(r'/\*', 'block_comment', 'block_comment'),
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(r'//#+(.*)\n', 'metacomment'),
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(r'//.*\n', None),
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],
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'module': [
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(r'parameter\s*(signed|integer|realtime|real|time)?\s*(\[[^]]+\])?', 'parameter_start', 'parameters'),
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(r'parameter\s+(?:(signed|integer|realtime|real|time)\s+)?(\[[^]]+\])?', 'parameter_start', 'parameters'),
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(
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r'^[\(\s]*(input|inout|output)\s+(reg|supply0|supply1|tri|triand|trior|tri0|tri1|wire|wand|wor|logic)?'
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r'\s*(signed)?\s*((\[[^]]+\])+)?',
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r'^[\(\s]*(input|inout|output)\s+(?:(reg|supply0|supply1|tri|triand|trior|tri0|tri1|wire|wand|wor|logic)\s+)?'
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r'(?:(signed)\s+)?((\[[^]]+\])+)?',
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'module_port_start', 'module_port'),
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(r'endmodule', 'end_module', '#pop'),
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(r'/\*', 'block_comment', 'block_comment'),
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(r'//#\s*{{(.*)}}\n', 'section_meta'),
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(r'//.*\n', None),
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],
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'parameters': [
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(r'\s*parameter\s*(signed|integer|realtime|real|time)?\s*(\[[^]]+\])?', 'parameter_start'),
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(r'\s*(\w+)\s*=\s*((?:(?!\/\/|[,)]).)*)', 'param_item'),
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(r'\s*parameter\s+(?:(signed|integer|realtime|real|time)\s+)?(\[[^]]+\])?', 'parameter_start'),
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(r'\s*(\w+)\s*=\s*((?:(?!\/\/|[,)]).)+)', 'param_item'),
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(r'//#+(.*)\n', 'metacomment'),
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(r',', None),
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(r'//.*\n', None),
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(r'[);]', None, '#pop'),
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],
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'module_port': [
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(
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r'\s*(input|inout|output)\s+(reg|supply0|supply1|tri|triand|trior|tri0|tri1|wire|wand|wor|logic)?'
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r'\s*(signed)?\s*((\[[^]]+\])+)?',
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r'\s*(input|inout|output)\s+(?:(reg|supply0|supply1|tri|triand|trior|tri0|tri1|wire|wand|wor|logic)\s+)?'
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r'(signed)?\s*((\[[^]]+\])+)?',
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'module_port_start'),
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(r'\s*(\w+)\s*,?', 'port_param'),
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(r'/\*', 'block_comment', 'block_comment'),

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