diff --git a/.github/workflows/wheels.yml b/.github/workflows/wheels.yml index aee266c..a47ac2f 100644 --- a/.github/workflows/wheels.yml +++ b/.github/workflows/wheels.yml @@ -30,7 +30,7 @@ jobs: name: Packages path: dist - - uses: pypa/gh-action-pypi-publish@v1.12.4 + - uses: pypa/gh-action-pypi-publish@v1.13.0 - name: Add wheels to GitHub release artifacts uses: softprops/action-gh-release@v2 diff --git a/logiklib/__init__.py b/logiklib/__init__.py index 82d6172..75e8798 100644 --- a/logiklib/__init__.py +++ b/logiklib/__init__.py @@ -1,8 +1,7 @@ -__version__ = "0.1.0" +__version__ = "0.1.2" -def register_part_data(fpga, part_name, package_name): - fpga.register_source( +def register_part_data(fpga, package_name, part_name): + fpga.set_dataroot( package_name, - f"github://siliconcompiler/logiklib/v{__version__}/{part_name}_cad.tar.gz", - f"v{__version__}") + f"github://siliconcompiler/logiklib/v{__version__}/{part_name}_cad.tar.gz") diff --git a/logiklib/zeroasic/z1000/z1000.py b/logiklib/zeroasic/z1000/z1000.py index 55f259c..dc9eb5a 100644 --- a/logiklib/zeroasic/z1000/z1000.py +++ b/logiklib/zeroasic/z1000/z1000.py @@ -1,61 +1,143 @@ -# Copyright 2025 Zero ASIC Corporation -# Licensed under the Apache 2.0 License (see LICENSE for details) -from logiklib import register_part_data +from siliconcompiler.tools.vpr import VPRFPGA +from siliconcompiler.tools.yosys import YosysFPGA +from siliconcompiler.tools.opensta import OpenSTAFPGA -from siliconcompiler import FPGA +from logiklib import register_part_data #################################################### # Setup for z1000 FPGA #################################################### -def setup(): + +class z1000(YosysFPGA, VPRFPGA, OpenSTAFPGA): ''' - z1000 is the first in a series of open FPGA architectures. - The baseline z1000 part is an architecture with 2K LUTs - and no hard macros. + Logik driver for z1000 ''' - part_name = 'z1000' - - fpga = FPGA(part_name, package=f"zeroasic-efpga-{part_name}") - - register_part_data(fpga, part_name, f"zeroasic-efpga-{part_name}") - - fpga.set('fpga', part_name, 'vendor', 'zeroasic') - - # Set a variable for VPR to use to detect the correct section - # of the architecture XML file - fpga.set('fpga', part_name, 'var', 'vpr_device_code', part_name) - - fpga.set('fpga', part_name, 'lutsize', 4) - fpga.set('fpga', part_name, 'var', 'feature_set', [ - 'async_reset', 'enable']) - - fpga.set('fpga', part_name, 'var', 'vpr_clock_model', 'route') - - fpga.set('fpga', part_name, 'file', 'archfile', f'cad/{part_name}.xml') - fpga.set('fpga', part_name, 'file', 'graphfile', f'cad/{part_name}_rr_graph.xml') - - for tool in ('vpr', 'yosys'): - fpga.set('fpga', part_name, 'var', f'{tool}_registers', [ - 'dff', - 'dffr', - 'dffe', - 'dffer']) - - fpga.set('fpga', part_name, 'file', 'yosys_flop_techmap', 'techlib/tech_flops.v') - - fpga.set('fpga', part_name, 'file', 'bitstream_map', f'cad/{part_name}_bitstream_map.json') - - fpga.set('fpga', part_name, 'file', 'constraints_map', f'cad/{part_name}_constraint_map.json') - - fpga.set('fpga', part_name, 'var', 'channelwidth', 100) - - return fpga + def __init__(self): + super().__init__() + self.set_name('z1000') + + self.define_tool_parameter('convert_bitstream', 'bitstream_map', 'file', + 'bitstream map') + + register_part_data(self, "logik-fpga-z1000", 'z1000') + + self.package.set_vendor("fpga_architect") + + self.set_vpr_devicecode("z1000") + + self.set_lutsize(4) + yosys_featureset = [] + yosys_featureset.append("async_reset") + yosys_featureset.append("enable") + + self.add_yosys_featureset(yosys_featureset) + self.set_vpr_clockmodel("route") + + with self.active_dataroot("logik-fpga-z1000"): + self.set_vpr_archfile('cad/z1000.xml') + self.set_vpr_graphfile('cad/z1000_rr_graph.xml') + self.set_yosys_config('cad/z1000_yosys_config.json') + self.set_yosys_flipfloptechmap('cad/tech_flops.v') + + # Define the macros that can be techmapped to based on the modes + # that exist in the design + self.add_yosys_registertype(['dff', 'dffe', 'dffer', 'dffr']) + self.add_vpr_registertype(['dff', 'dffe', 'dffer', 'dffr']) + + self.add_yosys_dsptype(['dsp_mult', + 'efpga_acc', + 'efpga_acc_regi', + 'efpga_adder', + 'efpga_adder_regi', + 'efpga_adder_regio', + 'efpga_adder_rego', + 'efpga_macc', + 'efpga_macc_pipe', + 'efpga_macc_pipe_regi', + 'efpga_macc_regi', + 'efpga_mult', + 'efpga_mult_addc', + 'efpga_mult_addc_regi', + 'efpga_mult_addc_regio', + 'efpga_mult_addc_rego', + 'efpga_mult_regi', + 'efpga_mult_regio', + 'efpga_mult_rego']) + self.add_vpr_dsptype(['dsp_mult', + 'efpga_acc', + 'efpga_acc_regi', + 'efpga_adder', + 'efpga_adder_regi', + 'efpga_adder_regio', + 'efpga_adder_rego', + 'efpga_macc', + 'efpga_macc_pipe', + 'efpga_macc_pipe_regi', + 'efpga_macc_regi', + 'efpga_mult', + 'efpga_mult_addc', + 'efpga_mult_addc_regi', + 'efpga_mult_addc_regio', + 'efpga_mult_addc_rego', + 'efpga_mult_regi', + 'efpga_mult_regio', + 'efpga_mult_rego']) + + self.add_yosys_bramtype(['sdpram_1024x1', + 'sdpram_128x8', + 'sdpram_256x4', + 'sdpram_512x2', + 'spram_1024x1', + 'spram_128x8', + 'spram_256x4', + 'spram_512x2', + 'spram_64x16', + 'sram_sdp', + 'sram_sp', + 'sram_tdp', + 'tdpram_1024x1', + 'tdpram_128x8', + 'tdpram_256x4', + 'tdpram_512x2']) + self.add_vpr_bramtype(['sdpram_1024x1', + 'sdpram_128x8', + 'sdpram_256x4', + 'sdpram_512x2', + 'spram_1024x1', + 'spram_128x8', + 'spram_256x4', + 'spram_512x2', + 'spram_64x16', + 'sram_sdp', + 'sram_sp', + 'sram_tdp', + 'tdpram_1024x1', + 'tdpram_128x8', + 'tdpram_256x4', + 'tdpram_512x2']) + + # TODO: blackbox_options + + with self.active_dataroot("logik-fpga-z1000"): + self.set("tool", "convert_bitstream", "bitstream_map", 'cad/z1000_bitstream_map.json') + self.set_vpr_constraintsmap('cad/z1000_constraint_map.json') + + self.set_vpr_channelwidth(100) + + with self.active_dataroot("logik-fpga-z1000"): + with self.active_fileset("z1000_opensta_liberty_files"): + self.add_file('cad/vtr_primitives.lib') + self.add_file(['cad/tech_flops.lib']) + self.add_opensta_liberty_fileset() + + self.set_vpr_router_lookahead('classic') ######################### if __name__ == "__main__": - fpga = setup() + fpga = z1000 + assert fpga.check_filepaths() fpga.write_manifest(f'{fpga.design}.json') diff --git a/logiklib/zeroasic/z1002/z1002.py b/logiklib/zeroasic/z1002/z1002.py index c7b4b52..2f39684 100644 --- a/logiklib/zeroasic/z1002/z1002.py +++ b/logiklib/zeroasic/z1002/z1002.py @@ -1,107 +1,143 @@ -# Copyright 2025 Zero ASIC Corporation -# Licensed under the Apache 2.0 License (see LICENSE for details) -# Auto-generated by FPGA Architect -from logiklib import register_part_data +from siliconcompiler.tools.vpr import VPRFPGA +from siliconcompiler.tools.yosys import YosysFPGA +from siliconcompiler.tools.opensta import OpenSTAFPGA -from siliconcompiler import FPGA +from logiklib import register_part_data #################################################### # Setup for z1002 FPGA #################################################### -def setup(): - - part_name = 'z1002' - - fpga = FPGA(part_name, package='logik-fpga-z1002') - - register_part_data(fpga, part_name, f"logik-fpga-{part_name}") - - fpga.set('fpga', part_name, 'vendor', 'fpga_architect') - - fpga.set('fpga', part_name, 'var', 'vpr_device_code', 'z1002') - - fpga.set('fpga', part_name, 'lutsize', 4) - fpga.add('fpga', part_name, 'var', 'feature_set', 'async_reset') - fpga.add('fpga', part_name, 'var', 'feature_set', 'enable') - fpga.add('fpga', part_name, 'var', 'vpr_clock_model', 'route') - fpga.set('fpga', part_name, 'file', 'archfile', 'cad/z1002.xml') - fpga.set('fpga', part_name, 'file', 'graphfile', 'cad/z1002_rr_graph.xml') - fpga.set('fpga', part_name, 'file', 'yosys_fpga_config', 'cad/z1002_yosys_config.json') - fpga.set('fpga', part_name, 'file', 'yosys_flop_techmap', 'cad/tech_flops.v') - - # Define the macros that can be techmapped to based on the modes - # that exist in the design - for tool in ('vpr', 'yosys'): - fpga.set('fpga', part_name, 'var', f'{tool}_registers', ['dffe', 'dffr', 'dffer', 'dff']) - - for tool in ('vpr', 'yosys'): - fpga.set('fpga', part_name, 'var', f'{tool}_dsps', - ['efpga_mult_addc', - 'efpga_acc_regi', - 'efpga_mult_addc_regi', - 'efpga_adder_regio', - 'dsp_mult', - 'efpga_acc', - 'efpga_adder_rego', - 'efpga_macc_pipe_regi', - 'efpga_mult_addc_rego', - 'efpga_mult_addc_regio', - 'efpga_mult', - 'efpga_macc_regi', - 'efpga_mult_regi', - 'efpga_mult_rego', - 'efpga_adder_regi', - 'efpga_macc', - 'efpga_macc_pipe', - 'efpga_mult_regio', - 'efpga_adder']) - - for tool in ('vpr', 'yosys'): - fpga.set('fpga', part_name, 'var', f'{tool}_brams', - ['sram_sdp', - 'tdpram_256x4', - 'sdpram_1024x1', - 'sdpram_512x2', - 'sram_sp', - 'spram_64x16', - 'tdpram_128x8', - 'tdpram_512x2', - 'spram_512x2', - 'spram_128x8', - 'sdpram_128x8', - 'spram_256x4', - 'sram_tdp', - 'sdpram_256x4', - 'tdpram_1024x1', - 'spram_1024x1']) - - # Set the dsp options for the yosys built-in DSP correctly for this - # architecture - fpga.add('fpga', part_name, 'var', 'yosys_dsp_options', 'DSP_A_MAXWIDTH=18') - fpga.add('fpga', part_name, 'var', 'yosys_dsp_options', 'DSP_B_MAXWIDTH=18') - fpga.add('fpga', part_name, 'var', 'yosys_dsp_options', 'DSP_A_MINWIDTH=2') - fpga.add('fpga', part_name, 'var', 'yosys_dsp_options', 'DSP_B_MINWIDTH=2') - fpga.add('fpga', part_name, 'var', 'yosys_dsp_options', 'DSP_NAME=_dsp_block_') - - fpga.add('fpga', part_name, 'var', 'dsp_blackbox_options', 'BLACKBOX_MACROS') - - fpga.set('fpga', part_name, 'file', 'bitstream_map', 'cad/z1002_bitstream_map.json') - - fpga.set('fpga', part_name, 'file', 'constraints_map', 'cad/z1002_constraint_map.json') - - fpga.set('fpga', part_name, 'var', 'channelwidth', 150) - - # Add the liberty files to the fpga part. - fpga.set('fpga', part_name, 'file', 'vtr_primitives_lib', 'vtr_primitives.lib') - fpga.set('fpga', part_name, 'file', 'fpga_macros_libs', ['tech_flops.lib']) - - return fpga + +class z1002(YosysFPGA, VPRFPGA, OpenSTAFPGA): + ''' + Logik driver for z1002 + ''' + + def __init__(self): + super().__init__() + self.set_name('z1002') + + self.define_tool_parameter('convert_bitstream', 'bitstream_map', 'file', + 'bitstream map') + + register_part_data(self, "logik-fpga-z1002", 'z1002') + + self.package.set_vendor("fpga_architect") + + self.set_vpr_devicecode("z1002") + + self.set_lutsize(4) + yosys_featureset = [] + yosys_featureset.append("async_reset") + yosys_featureset.append("enable") + + self.add_yosys_featureset(yosys_featureset) + self.set_vpr_clockmodel("route") + + with self.active_dataroot("logik-fpga-z1002"): + self.set_vpr_archfile('cad/z1002.xml') + self.set_vpr_graphfile('cad/z1002_rr_graph.xml') + self.set_yosys_config('cad/z1002_yosys_config.json') + self.set_yosys_flipfloptechmap('cad/tech_flops.v') + + # Define the macros that can be techmapped to based on the modes + # that exist in the design + self.add_yosys_registertype(['dff', 'dffe', 'dffer', 'dffr']) + self.add_vpr_registertype(['dff', 'dffe', 'dffer', 'dffr']) + + self.add_yosys_dsptype(['dsp_mult', + 'efpga_acc', + 'efpga_acc_regi', + 'efpga_adder', + 'efpga_adder_regi', + 'efpga_adder_regio', + 'efpga_adder_rego', + 'efpga_macc', + 'efpga_macc_pipe', + 'efpga_macc_pipe_regi', + 'efpga_macc_regi', + 'efpga_mult', + 'efpga_mult_addc', + 'efpga_mult_addc_regi', + 'efpga_mult_addc_regio', + 'efpga_mult_addc_rego', + 'efpga_mult_regi', + 'efpga_mult_regio', + 'efpga_mult_rego']) + self.add_vpr_dsptype(['dsp_mult', + 'efpga_acc', + 'efpga_acc_regi', + 'efpga_adder', + 'efpga_adder_regi', + 'efpga_adder_regio', + 'efpga_adder_rego', + 'efpga_macc', + 'efpga_macc_pipe', + 'efpga_macc_pipe_regi', + 'efpga_macc_regi', + 'efpga_mult', + 'efpga_mult_addc', + 'efpga_mult_addc_regi', + 'efpga_mult_addc_regio', + 'efpga_mult_addc_rego', + 'efpga_mult_regi', + 'efpga_mult_regio', + 'efpga_mult_rego']) + + self.add_yosys_bramtype(['sdpram_1024x1', + 'sdpram_128x8', + 'sdpram_256x4', + 'sdpram_512x2', + 'spram_1024x1', + 'spram_128x8', + 'spram_256x4', + 'spram_512x2', + 'spram_64x16', + 'sram_sdp', + 'sram_sp', + 'sram_tdp', + 'tdpram_1024x1', + 'tdpram_128x8', + 'tdpram_256x4', + 'tdpram_512x2']) + self.add_vpr_bramtype(['sdpram_1024x1', + 'sdpram_128x8', + 'sdpram_256x4', + 'sdpram_512x2', + 'spram_1024x1', + 'spram_128x8', + 'spram_256x4', + 'spram_512x2', + 'spram_64x16', + 'sram_sdp', + 'sram_sp', + 'sram_tdp', + 'tdpram_1024x1', + 'tdpram_128x8', + 'tdpram_256x4', + 'tdpram_512x2']) + + # TODO: blackbox_options + + with self.active_dataroot("logik-fpga-z1002"): + self.set("tool", "convert_bitstream", "bitstream_map", 'cad/z1002_bitstream_map.json') + self.set_vpr_constraintsmap('cad/z1002_constraint_map.json') + + self.set_vpr_channelwidth(150) + + with self.active_dataroot("logik-fpga-z1002"): + with self.active_fileset("z1002_opensta_liberty_files"): + self.add_file('cad/vtr_primitives.lib') + self.add_file(['cad/tech_flops.lib']) + self.add_opensta_liberty_fileset() + + self.set_vpr_router_lookahead('classic') ######################### if __name__ == "__main__": - fpga = setup() + fpga = z1002 assert fpga.check_filepaths() fpga.write_manifest(f'{fpga.design}.json') diff --git a/logiklib/zeroasic/z1010/z1010.py b/logiklib/zeroasic/z1010/z1010.py index 231e4ea..43c00c1 100644 --- a/logiklib/zeroasic/z1010/z1010.py +++ b/logiklib/zeroasic/z1010/z1010.py @@ -1,131 +1,190 @@ -# Copyright 2025 Zero ASIC Corporation -# Licensed under the Apache 2.0 License (see LICENSE for details) -# Auto-generated by FPGA Architect -from logiklib import register_part_data +from siliconcompiler.tools.vpr import VPRFPGA +from siliconcompiler.tools.yosys import YosysFPGA +from siliconcompiler.tools.opensta import OpenSTAFPGA -from siliconcompiler import FPGA +from logiklib import register_part_data #################################################### # Setup for z1010 FPGA #################################################### -def setup(): - - part_name = 'z1010' - - fpga = FPGA(part_name, package='logik-fpga-z1010') - - register_part_data(fpga, part_name, f"logik-fpga-{part_name}") - - fpga.set('fpga', part_name, 'vendor', 'fpga_architect') - - fpga.set('fpga', part_name, 'var', 'vpr_device_code', 'z1010') - - fpga.set('fpga', part_name, 'lutsize', 4) - fpga.add('fpga', part_name, 'var', 'feature_set', 'async_reset') - fpga.add('fpga', part_name, 'var', 'feature_set', 'enable') - fpga.add('fpga', part_name, 'var', 'vpr_clock_model', 'route') - fpga.set('fpga', part_name, 'file', 'archfile', 'cad/z1010.xml') - fpga.set('fpga', part_name, 'file', 'graphfile', 'cad/z1010_rr_graph.xml') - fpga.set('fpga', part_name, 'file', 'yosys_fpga_config', 'cad/z1010_yosys_config.json') - fpga.set('fpga', part_name, 'file', 'yosys_flop_techmap', 'cad/tech_flops.v') - fpga.set('fpga', part_name, 'file', 'yosys_memory_techmap', 'cad/tech_bram.v') - fpga.set('fpga', part_name, 'file', 'yosys_memory_libmap', 'cad/bram_memory_map.txt') - fpga.set('fpga', part_name, 'file', 'yosys_dsp_techmap', 'cad/tech_dsp.v') - fpga.set('fpga', part_name, 'file', 'yosys_extractlib', 'cad/tech_dsp_extract.v') - fpga.set('fpga', part_name, 'file', 'yosys_macrolib', 'cad/tech_dsp_blackbox.v') - - # Define the macros that can be techmapped to based on the modes - # that exist in the design - for tool in ('vpr', 'yosys'): - fpga.set('fpga', part_name, 'var', f'{tool}_registers', - ['dffelr', - 'dffhlr', - 'dffl', - 'dffe', - 'dffhr', - 'dffehlr', - 'dffer', - 'dfflr', - 'dffehl', - 'dff', - 'dffeh', - 'dffel', - 'dffhl', - 'dffr', - 'dffh', - 'dffehr']) - - for tool in ('vpr', 'yosys'): - fpga.set('fpga', part_name, 'var', f'{tool}_dsps', - ['efpga_acc', - 'efpga_mult_rego', - 'efpga_mult_regio', - 'efpga_mult_addc_regi', - 'efpga_mult_addc_rego', - 'efpga_mult', - 'efpga_adder_rego', - 'efpga_adder', - 'efpga_mult_regi', - 'efpga_acc_regi', - 'efpga_macc_regi', - 'efpga_mult_addc_regio', - 'efpga_adder_regi', - 'efpga_mult_addc', - 'efpga_adder_regio', - 'efpga_macc_pipe_regi', - 'dsp_mult', - 'efpga_macc', - 'efpga_macc_pipe']) - - for tool in ('vpr', 'yosys'): - fpga.set('fpga', part_name, 'var', f'{tool}_brams', - ['sram_sp', - 'spram_8192x2', - 'spram_2048x8', - 'tdpram_1024x16', - 'sdpram_8192x2', - 'sdpram_2048x8', - 'sdpram_1024x16', - 'spram_1024x16', - 'sdpram_4096x4', - 'spram_16384x1', - 'tdpram_16384x1', - 'sram_tdp', - 'spram_4096x4', - 'sdpram_16384x1', - 'sram_sdp', - 'spram_512x32', - 'tdpram_4096x4', - 'tdpram_2048x8', - 'tdpram_8192x2']) - - # Set the dsp options for the yosys built-in DSP correctly for this - # architecture - fpga.add('fpga', part_name, 'var', 'yosys_dsp_options', 'DSP_A_MAXWIDTH=18') - fpga.add('fpga', part_name, 'var', 'yosys_dsp_options', 'DSP_B_MAXWIDTH=18') - fpga.add('fpga', part_name, 'var', 'yosys_dsp_options', 'DSP_A_MINWIDTH=2') - fpga.add('fpga', part_name, 'var', 'yosys_dsp_options', 'DSP_B_MINWIDTH=2') - fpga.add('fpga', part_name, 'var', 'yosys_dsp_options', 'DSP_NAME=_dsp_block_') - - fpga.add('fpga', part_name, 'var', 'dsp_blackbox_options', 'BLACKBOX_MACROS') - - fpga.set('fpga', part_name, 'file', 'bitstream_map', 'cad/z1010_bitstream_map.json') - - fpga.set('fpga', part_name, 'file', 'constraints_map', 'cad/z1010_constraint_map.json') - - fpga.set('fpga', part_name, 'var', 'channelwidth', 100) - - # Add the liberty files to the fpga part. - fpga.set('fpga', part_name, 'file', 'vtr_primitives_lib', 'vtr_primitives.lib') - fpga.set('fpga', part_name, 'file', 'fpga_macros_libs', ['tech_flops.lib', 'tech_dsp.lib', 'tech_bram.lib']) - - return fpga + +class z1010(YosysFPGA, VPRFPGA, OpenSTAFPGA): + ''' + Logik driver for z1010 + ''' + + def __init__(self): + super().__init__() + self.set_name('z1010') + + self.define_tool_parameter('convert_bitstream', 'bitstream_map', 'file', + 'bitstream map') + + register_part_data(self, "logik-fpga-z1010", 'z1010') + + self.package.set_vendor("fpga_architect") + + self.set_vpr_devicecode("z1010") + + self.set_lutsize(4) + yosys_featureset = [] + yosys_featureset.append("async_reset") + yosys_featureset.append("enable") + + self.add_yosys_featureset(yosys_featureset) + self.set_vpr_clockmodel("route") + + with self.active_dataroot("logik-fpga-z1010"): + self.set_vpr_archfile('cad/z1010.xml') + self.set_vpr_graphfile('cad/z1010_rr_graph.xml') + self.set_yosys_config('cad/z1010_yosys_config.json') + self.set_yosys_flipfloptechmap('cad/tech_flops.v') + self.set_yosys_memorymap(techmap='cad/tech_bram.v') + self.set_yosys_memorymap(libmap='cad/bram_memory_map.txt') + self.set_yosys_dsptechmap('cad/tech_dsp.v', + options={'DSP_SIGNEDONLY': '1', + 'DSP_A_MAXWIDTH': '18', + 'DSP_B_MAXWIDTH': '18', + 'DSP_A_MINWIDTH': '2', + 'DSP_B_MINWIDTH': '2', + 'DSP_Y_MINWIDTH': '2', + 'DSP_NAME': '_dsp_block_'}) + self.add_yosys_macrolib('cad/tech_dsp_blackbox.v') + + # Define the macros that can be techmapped to based on the modes + # that exist in the design + self.add_yosys_registertype(['dff', + 'dffe', + 'dffeh', + 'dffehl', + 'dffehlr', + 'dffehr', + 'dffel', + 'dffelr', + 'dffer', + 'dffh', + 'dffhl', + 'dffhlr', + 'dffhr', + 'dffl', + 'dfflr', + 'dffr']) + self.add_vpr_registertype(['dff', + 'dffe', + 'dffeh', + 'dffehl', + 'dffehlr', + 'dffehr', + 'dffel', + 'dffelr', + 'dffer', + 'dffh', + 'dffhl', + 'dffhlr', + 'dffhr', + 'dffl', + 'dfflr', + 'dffr']) + + self.add_yosys_dsptype(['dsp_mult', + 'efpga_acc', + 'efpga_acc_regi', + 'efpga_adder', + 'efpga_adder_regi', + 'efpga_adder_regio', + 'efpga_adder_rego', + 'efpga_macc', + 'efpga_macc_pipe', + 'efpga_macc_pipe_regi', + 'efpga_macc_regi', + 'efpga_mult', + 'efpga_mult_addc', + 'efpga_mult_addc_regi', + 'efpga_mult_addc_regio', + 'efpga_mult_addc_rego', + 'efpga_mult_regi', + 'efpga_mult_regio', + 'efpga_mult_rego']) + self.add_vpr_dsptype(['dsp_mult', + 'efpga_acc', + 'efpga_acc_regi', + 'efpga_adder', + 'efpga_adder_regi', + 'efpga_adder_regio', + 'efpga_adder_rego', + 'efpga_macc', + 'efpga_macc_pipe', + 'efpga_macc_pipe_regi', + 'efpga_macc_regi', + 'efpga_mult', + 'efpga_mult_addc', + 'efpga_mult_addc_regi', + 'efpga_mult_addc_regio', + 'efpga_mult_addc_rego', + 'efpga_mult_regi', + 'efpga_mult_regio', + 'efpga_mult_rego']) + + self.add_yosys_bramtype(['sdpram_1024x16', + 'sdpram_16384x1', + 'sdpram_2048x8', + 'sdpram_4096x4', + 'sdpram_8192x2', + 'spram_1024x16', + 'spram_16384x1', + 'spram_2048x8', + 'spram_4096x4', + 'spram_512x32', + 'spram_8192x2', + 'sram_sdp', + 'sram_sp', + 'sram_tdp', + 'tdpram_1024x16', + 'tdpram_16384x1', + 'tdpram_2048x8', + 'tdpram_4096x4', + 'tdpram_8192x2']) + self.add_vpr_bramtype(['sdpram_1024x16', + 'sdpram_16384x1', + 'sdpram_2048x8', + 'sdpram_4096x4', + 'sdpram_8192x2', + 'spram_1024x16', + 'spram_16384x1', + 'spram_2048x8', + 'spram_4096x4', + 'spram_512x32', + 'spram_8192x2', + 'sram_sdp', + 'sram_sp', + 'sram_tdp', + 'tdpram_1024x16', + 'tdpram_16384x1', + 'tdpram_2048x8', + 'tdpram_4096x4', + 'tdpram_8192x2']) + + # TODO: blackbox_options + + with self.active_dataroot("logik-fpga-z1010"): + self.set("tool", "convert_bitstream", "bitstream_map", 'cad/z1010_bitstream_map.json') + self.set_vpr_constraintsmap('cad/z1010_constraint_map.json') + + self.set_vpr_channelwidth(100) + + with self.active_dataroot("logik-fpga-z1010"): + with self.active_fileset("z1010_opensta_liberty_files"): + self.add_file('cad/vtr_primitives.lib') + self.add_file(['cad/tech_flops.lib', 'cad/tech_dsp.lib', 'cad/tech_bram.lib']) + self.add_opensta_liberty_fileset() + + self.set_vpr_router_lookahead('classic') ######################### if __name__ == "__main__": - fpga = setup() + fpga = z1010 assert fpga.check_filepaths() fpga.write_manifest(f'{fpga.design}.json') diff --git a/logiklib/zeroasic/z1012/z1012.py b/logiklib/zeroasic/z1012/z1012.py index 353cacb..ea1a4e2 100644 --- a/logiklib/zeroasic/z1012/z1012.py +++ b/logiklib/zeroasic/z1012/z1012.py @@ -1,131 +1,190 @@ -# Copyright 2025 Zero ASIC Corporation -# Licensed under the Apache 2.0 License (see LICENSE for details) -# Auto-generated by FPGA Architect -from logiklib import register_part_data +from siliconcompiler.tools.vpr import VPRFPGA +from siliconcompiler.tools.yosys import YosysFPGA +from siliconcompiler.tools.opensta import OpenSTAFPGA -from siliconcompiler import FPGA +from logiklib import register_part_data #################################################### # Setup for z1012 FPGA #################################################### -def setup(): - - part_name = 'z1012' - - fpga = FPGA(part_name, package='logik-fpga-z1012') - - register_part_data(fpga, part_name, f"logik-fpga-{part_name}") - - fpga.set('fpga', part_name, 'vendor', 'fpga_architect') - - fpga.set('fpga', part_name, 'var', 'vpr_device_code', 'z1012') - - fpga.set('fpga', part_name, 'lutsize', 4) - fpga.add('fpga', part_name, 'var', 'feature_set', 'async_reset') - fpga.add('fpga', part_name, 'var', 'feature_set', 'enable') - fpga.add('fpga', part_name, 'var', 'vpr_clock_model', 'route') - fpga.set('fpga', part_name, 'file', 'archfile', 'cad/z1012.xml') - fpga.set('fpga', part_name, 'file', 'graphfile', 'cad/z1012_rr_graph.xml') - fpga.set('fpga', part_name, 'file', 'yosys_fpga_config', 'cad/z1012_yosys_config.json') - fpga.set('fpga', part_name, 'file', 'yosys_flop_techmap', 'cad/tech_flops.v') - fpga.set('fpga', part_name, 'file', 'yosys_memory_techmap', 'cad/tech_bram.v') - fpga.set('fpga', part_name, 'file', 'yosys_memory_libmap', 'cad/bram_memory_map.txt') - fpga.set('fpga', part_name, 'file', 'yosys_dsp_techmap', 'cad/tech_dsp.v') - fpga.set('fpga', part_name, 'file', 'yosys_extractlib', 'cad/tech_dsp_extract.v') - fpga.set('fpga', part_name, 'file', 'yosys_macrolib', 'cad/tech_dsp_blackbox.v') - - # Define the macros that can be techmapped to based on the modes - # that exist in the design - for tool in ('vpr', 'yosys'): - fpga.set('fpga', part_name, 'var', f'{tool}_registers', - ['dffhl', - 'dffer', - 'dffhr', - 'dfflr', - 'dffeh', - 'dffh', - 'dffhlr', - 'dffehlr', - 'dffl', - 'dffel', - 'dffe', - 'dff', - 'dffehl', - 'dffehr', - 'dffr', - 'dffelr']) - - for tool in ('vpr', 'yosys'): - fpga.set('fpga', part_name, 'var', f'{tool}_dsps', - ['efpga_adder_regio', - 'efpga_adder_regi', - 'efpga_macc_regi', - 'efpga_mult', - 'efpga_adder', - 'efpga_mult_addc_regio', - 'efpga_macc_pipe_regi', - 'efpga_acc', - 'efpga_acc_regi', - 'efpga_macc_pipe', - 'efpga_macc', - 'efpga_mult_addc_rego', - 'dsp_mult', - 'efpga_mult_addc_regi', - 'efpga_mult_regio', - 'efpga_mult_regi', - 'efpga_adder_rego', - 'efpga_mult_rego', - 'efpga_mult_addc']) - - for tool in ('vpr', 'yosys'): - fpga.set('fpga', part_name, 'var', f'{tool}_brams', - ['spram_16384x1', - 'sram_sp', - 'tdpram_16384x1', - 'tdpram_2048x8', - 'spram_8192x2', - 'spram_512x32', - 'sdpram_8192x2', - 'sdpram_4096x4', - 'spram_4096x4', - 'tdpram_8192x2', - 'tdpram_1024x16', - 'sdpram_1024x16', - 'sdpram_16384x1', - 'tdpram_4096x4', - 'spram_1024x16', - 'sram_tdp', - 'sdpram_2048x8', - 'spram_2048x8', - 'sram_sdp']) - - # Set the dsp options for the yosys built-in DSP correctly for this - # architecture - fpga.add('fpga', part_name, 'var', 'yosys_dsp_options', 'DSP_A_MAXWIDTH=18') - fpga.add('fpga', part_name, 'var', 'yosys_dsp_options', 'DSP_B_MAXWIDTH=18') - fpga.add('fpga', part_name, 'var', 'yosys_dsp_options', 'DSP_A_MINWIDTH=2') - fpga.add('fpga', part_name, 'var', 'yosys_dsp_options', 'DSP_B_MINWIDTH=2') - fpga.add('fpga', part_name, 'var', 'yosys_dsp_options', 'DSP_NAME=_dsp_block_') - - fpga.add('fpga', part_name, 'var', 'dsp_blackbox_options', 'BLACKBOX_MACROS') - - fpga.set('fpga', part_name, 'file', 'bitstream_map', 'cad/z1012_bitstream_map.json') - - fpga.set('fpga', part_name, 'file', 'constraints_map', 'cad/z1012_constraint_map.json') - - fpga.set('fpga', part_name, 'var', 'channelwidth', 100) - - # Add the liberty files to the fpga part. - fpga.set('fpga', part_name, 'file', 'vtr_primitives_lib', 'vtr_primitives.lib') - fpga.set('fpga', part_name, 'file', 'fpga_macros_libs', ['tech_flops.lib', 'tech_dsp.lib', 'tech_bram.lib']) - - return fpga + +class z1012(YosysFPGA, VPRFPGA, OpenSTAFPGA): + ''' + Logik driver for z1012 + ''' + + def __init__(self): + super().__init__() + self.set_name('z1012') + + self.define_tool_parameter('convert_bitstream', 'bitstream_map', 'file', + 'bitstream map') + + register_part_data(self, "logik-fpga-z1012", 'z1012') + + self.package.set_vendor("fpga_architect") + + self.set_vpr_devicecode("z1012") + + self.set_lutsize(4) + yosys_featureset = [] + yosys_featureset.append("async_reset") + yosys_featureset.append("enable") + + self.add_yosys_featureset(yosys_featureset) + self.set_vpr_clockmodel("route") + + with self.active_dataroot("logik-fpga-z1012"): + self.set_vpr_archfile('cad/z1012.xml') + self.set_vpr_graphfile('cad/z1012_rr_graph.xml') + self.set_yosys_config('cad/z1012_yosys_config.json') + self.set_yosys_flipfloptechmap('cad/tech_flops.v') + self.set_yosys_memorymap(techmap='cad/tech_bram.v') + self.set_yosys_memorymap(libmap='cad/bram_memory_map.txt') + self.set_yosys_dsptechmap('cad/tech_dsp.v', + options={'DSP_SIGNEDONLY': '1', + 'DSP_A_MAXWIDTH': '18', + 'DSP_B_MAXWIDTH': '18', + 'DSP_A_MINWIDTH': '2', + 'DSP_B_MINWIDTH': '2', + 'DSP_Y_MINWIDTH': '2', + 'DSP_NAME': '_dsp_block_'}) + self.add_yosys_macrolib('cad/tech_dsp_blackbox.v') + + # Define the macros that can be techmapped to based on the modes + # that exist in the design + self.add_yosys_registertype(['dff', + 'dffe', + 'dffeh', + 'dffehl', + 'dffehlr', + 'dffehr', + 'dffel', + 'dffelr', + 'dffer', + 'dffh', + 'dffhl', + 'dffhlr', + 'dffhr', + 'dffl', + 'dfflr', + 'dffr']) + self.add_vpr_registertype(['dff', + 'dffe', + 'dffeh', + 'dffehl', + 'dffehlr', + 'dffehr', + 'dffel', + 'dffelr', + 'dffer', + 'dffh', + 'dffhl', + 'dffhlr', + 'dffhr', + 'dffl', + 'dfflr', + 'dffr']) + + self.add_yosys_dsptype(['dsp_mult', + 'efpga_acc', + 'efpga_acc_regi', + 'efpga_adder', + 'efpga_adder_regi', + 'efpga_adder_regio', + 'efpga_adder_rego', + 'efpga_macc', + 'efpga_macc_pipe', + 'efpga_macc_pipe_regi', + 'efpga_macc_regi', + 'efpga_mult', + 'efpga_mult_addc', + 'efpga_mult_addc_regi', + 'efpga_mult_addc_regio', + 'efpga_mult_addc_rego', + 'efpga_mult_regi', + 'efpga_mult_regio', + 'efpga_mult_rego']) + self.add_vpr_dsptype(['dsp_mult', + 'efpga_acc', + 'efpga_acc_regi', + 'efpga_adder', + 'efpga_adder_regi', + 'efpga_adder_regio', + 'efpga_adder_rego', + 'efpga_macc', + 'efpga_macc_pipe', + 'efpga_macc_pipe_regi', + 'efpga_macc_regi', + 'efpga_mult', + 'efpga_mult_addc', + 'efpga_mult_addc_regi', + 'efpga_mult_addc_regio', + 'efpga_mult_addc_rego', + 'efpga_mult_regi', + 'efpga_mult_regio', + 'efpga_mult_rego']) + + self.add_yosys_bramtype(['sdpram_1024x16', + 'sdpram_16384x1', + 'sdpram_2048x8', + 'sdpram_4096x4', + 'sdpram_8192x2', + 'spram_1024x16', + 'spram_16384x1', + 'spram_2048x8', + 'spram_4096x4', + 'spram_512x32', + 'spram_8192x2', + 'sram_sdp', + 'sram_sp', + 'sram_tdp', + 'tdpram_1024x16', + 'tdpram_16384x1', + 'tdpram_2048x8', + 'tdpram_4096x4', + 'tdpram_8192x2']) + self.add_vpr_bramtype(['sdpram_1024x16', + 'sdpram_16384x1', + 'sdpram_2048x8', + 'sdpram_4096x4', + 'sdpram_8192x2', + 'spram_1024x16', + 'spram_16384x1', + 'spram_2048x8', + 'spram_4096x4', + 'spram_512x32', + 'spram_8192x2', + 'sram_sdp', + 'sram_sp', + 'sram_tdp', + 'tdpram_1024x16', + 'tdpram_16384x1', + 'tdpram_2048x8', + 'tdpram_4096x4', + 'tdpram_8192x2']) + + # TODO: blackbox_options + + with self.active_dataroot("logik-fpga-z1012"): + self.set("tool", "convert_bitstream", "bitstream_map", 'cad/z1012_bitstream_map.json') + self.set_vpr_constraintsmap('cad/z1012_constraint_map.json') + + self.set_vpr_channelwidth(150) + + with self.active_dataroot("logik-fpga-z1012"): + with self.active_fileset("z1012_opensta_liberty_files"): + self.add_file('cad/vtr_primitives.lib') + self.add_file(['cad/tech_flops.lib', 'cad/tech_dsp.lib', 'cad/tech_bram.lib']) + self.add_opensta_liberty_fileset() + + self.set_vpr_router_lookahead('classic') ######################### if __name__ == "__main__": - fpga = setup() + fpga = z1012 assert fpga.check_filepaths() fpga.write_manifest(f'{fpga.design}.json') diff --git a/logiklib/zeroasic/z1060/z1060.py b/logiklib/zeroasic/z1060/z1060.py index 0972e2b..b5732d6 100644 --- a/logiklib/zeroasic/z1060/z1060.py +++ b/logiklib/zeroasic/z1060/z1060.py @@ -1,131 +1,190 @@ -# Copyright 2025 Zero ASIC Corporation -# Licensed under the Apache 2.0 License (see LICENSE for details) -# Auto-generated by FPGA Architect -from logiklib import register_part_data +from siliconcompiler.tools.vpr import VPRFPGA +from siliconcompiler.tools.yosys import YosysFPGA +from siliconcompiler.tools.opensta import OpenSTAFPGA -from siliconcompiler import FPGA +from logiklib import register_part_data #################################################### # Setup for z1060 FPGA #################################################### -def setup(): - - part_name = 'z1060' - - fpga = FPGA(part_name, package='logik-fpga-z1060') - - register_part_data(fpga, part_name, f"logik-fpga-{part_name}") - - fpga.set('fpga', part_name, 'vendor', 'fpga_architect') - - fpga.set('fpga', part_name, 'var', 'vpr_device_code', 'z1060') - - fpga.set('fpga', part_name, 'lutsize', 6) - fpga.add('fpga', part_name, 'var', 'feature_set', 'async_reset') - fpga.add('fpga', part_name, 'var', 'feature_set', 'enable') - fpga.add('fpga', part_name, 'var', 'vpr_clock_model', 'route') - fpga.set('fpga', part_name, 'file', 'archfile', 'cad/z1060.xml') - fpga.set('fpga', part_name, 'file', 'graphfile', 'cad/z1060_rr_graph.xml') - fpga.set('fpga', part_name, 'file', 'yosys_fpga_config', 'cad/z1060_yosys_config.json') - fpga.set('fpga', part_name, 'file', 'yosys_flop_techmap', 'cad/tech_flops.v') - fpga.set('fpga', part_name, 'file', 'yosys_memory_techmap', 'cad/tech_bram.v') - fpga.set('fpga', part_name, 'file', 'yosys_memory_libmap', 'cad/bram_memory_map.txt') - fpga.set('fpga', part_name, 'file', 'yosys_dsp_techmap', 'cad/tech_dsp.v') - fpga.set('fpga', part_name, 'file', 'yosys_extractlib', 'cad/tech_dsp_extract.v') - fpga.set('fpga', part_name, 'file', 'yosys_macrolib', 'cad/tech_dsp_blackbox.v') - - # Define the macros that can be techmapped to based on the modes - # that exist in the design - for tool in ('vpr', 'yosys'): - fpga.set('fpga', part_name, 'var', f'{tool}_registers', - ['dffe', - 'dffeh', - 'dffr', - 'dffelr', - 'dffh', - 'dffehr', - 'dfflr', - 'dffer', - 'dffhr', - 'dffhlr', - 'dffel', - 'dff', - 'dffhl', - 'dffl', - 'dffehlr', - 'dffehl']) - - for tool in ('vpr', 'yosys'): - fpga.set('fpga', part_name, 'var', f'{tool}_dsps', - ['dsp_mult', - 'efpga_mult_regi', - 'efpga_mult_rego', - 'efpga_adder_regio', - 'efpga_macc_regi', - 'efpga_macc_pipe_regi', - 'efpga_adder_rego', - 'efpga_mult_addc_regi', - 'efpga_adder_regi', - 'efpga_macc', - 'efpga_acc_regi', - 'efpga_acc', - 'efpga_mult_addc_rego', - 'efpga_mult_addc_regio', - 'efpga_macc_pipe', - 'efpga_mult', - 'efpga_adder', - 'efpga_mult_regio', - 'efpga_mult_addc']) - - for tool in ('vpr', 'yosys'): - fpga.set('fpga', part_name, 'var', f'{tool}_brams', - ['sdpram_2048x8', - 'sram_tdp', - 'spram_512x32', - 'tdpram_8192x2', - 'tdpram_2048x8', - 'tdpram_16384x1', - 'tdpram_1024x16', - 'sdpram_8192x2', - 'spram_1024x16', - 'tdpram_4096x4', - 'spram_8192x2', - 'sdpram_16384x1', - 'sdpram_1024x16', - 'spram_4096x4', - 'spram_16384x1', - 'sram_sp', - 'spram_2048x8', - 'sdpram_4096x4', - 'sram_sdp']) - - # Set the dsp options for the yosys built-in DSP correctly for this - # architecture - fpga.add('fpga', part_name, 'var', 'yosys_dsp_options', 'DSP_A_MAXWIDTH=18') - fpga.add('fpga', part_name, 'var', 'yosys_dsp_options', 'DSP_B_MAXWIDTH=18') - fpga.add('fpga', part_name, 'var', 'yosys_dsp_options', 'DSP_A_MINWIDTH=2') - fpga.add('fpga', part_name, 'var', 'yosys_dsp_options', 'DSP_B_MINWIDTH=2') - fpga.add('fpga', part_name, 'var', 'yosys_dsp_options', 'DSP_NAME=_dsp_block_') - - fpga.add('fpga', part_name, 'var', 'dsp_blackbox_options', 'BLACKBOX_MACROS') - - fpga.set('fpga', part_name, 'file', 'bitstream_map', 'cad/z1060_bitstream_map.json') - - fpga.set('fpga', part_name, 'file', 'constraints_map', 'cad/z1060_constraint_map.json') - - fpga.set('fpga', part_name, 'var', 'channelwidth', 100) - - # Add the liberty files to the fpga part. - fpga.set('fpga', part_name, 'file', 'vtr_primitives_lib', 'vtr_primitives.lib') - fpga.set('fpga', part_name, 'file', 'fpga_macros_libs', ['tech_flops.lib', 'tech_dsp.lib', 'tech_bram.lib']) - - return fpga + +class z1060(YosysFPGA, VPRFPGA, OpenSTAFPGA): + ''' + Logik driver for z1060 + ''' + + def __init__(self): + super().__init__() + self.set_name('z1060') + + self.define_tool_parameter('convert_bitstream', 'bitstream_map', 'file', + 'bitstream map') + + register_part_data(self, "logik-fpga-z1060", 'z1060') + + self.package.set_vendor("fpga_architect") + + self.set_vpr_devicecode("z1060") + + self.set_lutsize(6) + yosys_featureset = [] + yosys_featureset.append("async_reset") + yosys_featureset.append("enable") + + self.add_yosys_featureset(yosys_featureset) + self.set_vpr_clockmodel("route") + + with self.active_dataroot("logik-fpga-z1060"): + self.set_vpr_archfile('cad/z1060.xml') + self.set_vpr_graphfile('cad/z1060_rr_graph.xml') + self.set_yosys_config('cad/z1060_yosys_config.json') + self.set_yosys_flipfloptechmap('cad/tech_flops.v') + self.set_yosys_memorymap(techmap='cad/tech_bram.v') + self.set_yosys_memorymap(libmap='cad/bram_memory_map.txt') + self.set_yosys_dsptechmap('cad/tech_dsp.v', + options={'DSP_SIGNEDONLY': '1', + 'DSP_A_MAXWIDTH': '18', + 'DSP_B_MAXWIDTH': '18', + 'DSP_A_MINWIDTH': '2', + 'DSP_B_MINWIDTH': '2', + 'DSP_Y_MINWIDTH': '2', + 'DSP_NAME': '_dsp_block_'}) + self.add_yosys_macrolib('cad/tech_dsp_blackbox.v') + + # Define the macros that can be techmapped to based on the modes + # that exist in the design + self.add_yosys_registertype(['dff', + 'dffe', + 'dffeh', + 'dffehl', + 'dffehlr', + 'dffehr', + 'dffel', + 'dffelr', + 'dffer', + 'dffh', + 'dffhl', + 'dffhlr', + 'dffhr', + 'dffl', + 'dfflr', + 'dffr']) + self.add_vpr_registertype(['dff', + 'dffe', + 'dffeh', + 'dffehl', + 'dffehlr', + 'dffehr', + 'dffel', + 'dffelr', + 'dffer', + 'dffh', + 'dffhl', + 'dffhlr', + 'dffhr', + 'dffl', + 'dfflr', + 'dffr']) + + self.add_yosys_dsptype(['dsp_mult', + 'efpga_acc', + 'efpga_acc_regi', + 'efpga_adder', + 'efpga_adder_regi', + 'efpga_adder_regio', + 'efpga_adder_rego', + 'efpga_macc', + 'efpga_macc_pipe', + 'efpga_macc_pipe_regi', + 'efpga_macc_regi', + 'efpga_mult', + 'efpga_mult_addc', + 'efpga_mult_addc_regi', + 'efpga_mult_addc_regio', + 'efpga_mult_addc_rego', + 'efpga_mult_regi', + 'efpga_mult_regio', + 'efpga_mult_rego']) + self.add_vpr_dsptype(['dsp_mult', + 'efpga_acc', + 'efpga_acc_regi', + 'efpga_adder', + 'efpga_adder_regi', + 'efpga_adder_regio', + 'efpga_adder_rego', + 'efpga_macc', + 'efpga_macc_pipe', + 'efpga_macc_pipe_regi', + 'efpga_macc_regi', + 'efpga_mult', + 'efpga_mult_addc', + 'efpga_mult_addc_regi', + 'efpga_mult_addc_regio', + 'efpga_mult_addc_rego', + 'efpga_mult_regi', + 'efpga_mult_regio', + 'efpga_mult_rego']) + + self.add_yosys_bramtype(['sdpram_1024x16', + 'sdpram_16384x1', + 'sdpram_2048x8', + 'sdpram_4096x4', + 'sdpram_8192x2', + 'spram_1024x16', + 'spram_16384x1', + 'spram_2048x8', + 'spram_4096x4', + 'spram_512x32', + 'spram_8192x2', + 'sram_sdp', + 'sram_sp', + 'sram_tdp', + 'tdpram_1024x16', + 'tdpram_16384x1', + 'tdpram_2048x8', + 'tdpram_4096x4', + 'tdpram_8192x2']) + self.add_vpr_bramtype(['sdpram_1024x16', + 'sdpram_16384x1', + 'sdpram_2048x8', + 'sdpram_4096x4', + 'sdpram_8192x2', + 'spram_1024x16', + 'spram_16384x1', + 'spram_2048x8', + 'spram_4096x4', + 'spram_512x32', + 'spram_8192x2', + 'sram_sdp', + 'sram_sp', + 'sram_tdp', + 'tdpram_1024x16', + 'tdpram_16384x1', + 'tdpram_2048x8', + 'tdpram_4096x4', + 'tdpram_8192x2']) + + # TODO: blackbox_options + + with self.active_dataroot("logik-fpga-z1060"): + self.set("tool", "convert_bitstream", "bitstream_map", 'cad/z1060_bitstream_map.json') + self.set_vpr_constraintsmap('cad/z1060_constraint_map.json') + + self.set_vpr_channelwidth(100) + + with self.active_dataroot("logik-fpga-z1060"): + with self.active_fileset("z1060_opensta_liberty_files"): + self.add_file('cad/vtr_primitives.lib') + self.add_file(['cad/tech_flops.lib', 'cad/tech_dsp.lib', 'cad/tech_bram.lib']) + self.add_opensta_liberty_fileset() + + self.set_vpr_router_lookahead('classic') ######################### if __name__ == "__main__": - fpga = setup() + fpga = z1060 assert fpga.check_filepaths() fpga.write_manifest(f'{fpga.design}.json') diff --git a/logiklib/zeroasic/z1062/z1062.py b/logiklib/zeroasic/z1062/z1062.py index d471fc8..275c4a7 100644 --- a/logiklib/zeroasic/z1062/z1062.py +++ b/logiklib/zeroasic/z1062/z1062.py @@ -1,131 +1,190 @@ -# Copyright 2025 Zero ASIC Corporation -# Licensed under the Apache 2.0 License (see LICENSE for details) -# Auto-generated by FPGA Architect -from logiklib import register_part_data +from siliconcompiler.tools.vpr import VPRFPGA +from siliconcompiler.tools.yosys import YosysFPGA +from siliconcompiler.tools.opensta import OpenSTAFPGA -from siliconcompiler import FPGA +from logiklib import register_part_data #################################################### # Setup for z1062 FPGA #################################################### -def setup(): - - part_name = 'z1062' - - fpga = FPGA(part_name, package='logik-fpga-z1062') - - register_part_data(fpga, part_name, f"logik-fpga-{part_name}") - - fpga.set('fpga', part_name, 'vendor', 'fpga_architect') - - fpga.set('fpga', part_name, 'var', 'vpr_device_code', 'z1062') - - fpga.set('fpga', part_name, 'lutsize', 6) - fpga.add('fpga', part_name, 'var', 'feature_set', 'async_reset') - fpga.add('fpga', part_name, 'var', 'feature_set', 'enable') - fpga.add('fpga', part_name, 'var', 'vpr_clock_model', 'route') - fpga.set('fpga', part_name, 'file', 'archfile', 'cad/z1062.xml') - fpga.set('fpga', part_name, 'file', 'graphfile', 'cad/z1062_rr_graph.xml') - fpga.set('fpga', part_name, 'file', 'yosys_fpga_config', 'cad/z1062_yosys_config.json') - fpga.set('fpga', part_name, 'file', 'yosys_flop_techmap', 'cad/tech_flops.v') - fpga.set('fpga', part_name, 'file', 'yosys_memory_techmap', 'cad/tech_bram.v') - fpga.set('fpga', part_name, 'file', 'yosys_memory_libmap', 'cad/bram_memory_map.txt') - fpga.set('fpga', part_name, 'file', 'yosys_dsp_techmap', 'cad/tech_dsp.v') - fpga.set('fpga', part_name, 'file', 'yosys_extractlib', 'cad/tech_dsp_extract.v') - fpga.set('fpga', part_name, 'file', 'yosys_macrolib', 'cad/tech_dsp_blackbox.v') - - # Define the macros that can be techmapped to based on the modes - # that exist in the design - for tool in ('vpr', 'yosys'): - fpga.set('fpga', part_name, 'var', f'{tool}_registers', - ['dffehlr', - 'dffer', - 'dffhlr', - 'dffel', - 'dffhl', - 'dffl', - 'dff', - 'dffeh', - 'dffr', - 'dffh', - 'dffhr', - 'dfflr', - 'dffehr', - 'dffelr', - 'dffe', - 'dffehl']) - - for tool in ('vpr', 'yosys'): - fpga.set('fpga', part_name, 'var', f'{tool}_dsps', - ['efpga_mult_regi', - 'efpga_adder_regi', - 'efpga_macc_pipe_regi', - 'efpga_macc_pipe', - 'efpga_adder', - 'efpga_macc', - 'efpga_mult_regio', - 'efpga_mult_addc', - 'efpga_mult_addc_regio', - 'efpga_adder_regio', - 'efpga_mult_addc_regi', - 'efpga_macc_regi', - 'efpga_mult', - 'efpga_acc_regi', - 'efpga_mult_rego', - 'dsp_mult', - 'efpga_adder_rego', - 'efpga_mult_addc_rego', - 'efpga_acc']) - - for tool in ('vpr', 'yosys'): - fpga.set('fpga', part_name, 'var', f'{tool}_brams', - ['tdpram_2048x8', - 'spram_1024x16', - 'spram_4096x4', - 'spram_16384x1', - 'tdpram_4096x4', - 'spram_2048x8', - 'sdpram_2048x8', - 'sram_sp', - 'tdpram_1024x16', - 'tdpram_8192x2', - 'sdpram_8192x2', - 'sdpram_16384x1', - 'spram_512x32', - 'spram_8192x2', - 'sram_tdp', - 'tdpram_16384x1', - 'sdpram_1024x16', - 'sram_sdp', - 'sdpram_4096x4']) - - # Set the dsp options for the yosys built-in DSP correctly for this - # architecture - fpga.add('fpga', part_name, 'var', 'yosys_dsp_options', 'DSP_A_MAXWIDTH=18') - fpga.add('fpga', part_name, 'var', 'yosys_dsp_options', 'DSP_B_MAXWIDTH=18') - fpga.add('fpga', part_name, 'var', 'yosys_dsp_options', 'DSP_A_MINWIDTH=2') - fpga.add('fpga', part_name, 'var', 'yosys_dsp_options', 'DSP_B_MINWIDTH=2') - fpga.add('fpga', part_name, 'var', 'yosys_dsp_options', 'DSP_NAME=_dsp_block_') - - fpga.add('fpga', part_name, 'var', 'dsp_blackbox_options', 'BLACKBOX_MACROS') - - fpga.set('fpga', part_name, 'file', 'bitstream_map', 'cad/z1062_bitstream_map.json') - - fpga.set('fpga', part_name, 'file', 'constraints_map', 'cad/z1062_constraint_map.json') - - fpga.set('fpga', part_name, 'var', 'channelwidth', 150) - - # Add the liberty files to the fpga part. - fpga.set('fpga', part_name, 'file', 'vtr_primitives_lib', 'vtr_primitives.lib') - fpga.set('fpga', part_name, 'file', 'fpga_macros_libs', ['tech_flops.lib', 'tech_dsp.lib', 'tech_bram.lib']) - - return fpga + +class z1062(YosysFPGA, VPRFPGA, OpenSTAFPGA): + ''' + Logik driver for z1062 + ''' + + def __init__(self): + super().__init__() + self.set_name('z1062') + + self.define_tool_parameter('convert_bitstream', 'bitstream_map', 'file', + 'bitstream map') + + register_part_data(self, "logik-fpga-z1062", 'z1062') + + self.package.set_vendor("fpga_architect") + + self.set_vpr_devicecode("z1062") + + self.set_lutsize(6) + yosys_featureset = [] + yosys_featureset.append("async_reset") + yosys_featureset.append("enable") + + self.add_yosys_featureset(yosys_featureset) + self.set_vpr_clockmodel("route") + + with self.active_dataroot("logik-fpga-z1062"): + self.set_vpr_archfile('cad/z1062.xml') + self.set_vpr_graphfile('cad/z1062_rr_graph.xml') + self.set_yosys_config('cad/z1062_yosys_config.json') + self.set_yosys_flipfloptechmap('cad/tech_flops.v') + self.set_yosys_memorymap(techmap='cad/tech_bram.v') + self.set_yosys_memorymap(libmap='cad/bram_memory_map.txt') + self.set_yosys_dsptechmap('cad/tech_dsp.v', + options={'DSP_SIGNEDONLY': '1', + 'DSP_A_MAXWIDTH': '18', + 'DSP_B_MAXWIDTH': '18', + 'DSP_A_MINWIDTH': '2', + 'DSP_B_MINWIDTH': '2', + 'DSP_Y_MINWIDTH': '2', + 'DSP_NAME': '_dsp_block_'}) + self.add_yosys_macrolib('cad/tech_dsp_blackbox.v') + + # Define the macros that can be techmapped to based on the modes + # that exist in the design + self.add_yosys_registertype(['dff', + 'dffe', + 'dffeh', + 'dffehl', + 'dffehlr', + 'dffehr', + 'dffel', + 'dffelr', + 'dffer', + 'dffh', + 'dffhl', + 'dffhlr', + 'dffhr', + 'dffl', + 'dfflr', + 'dffr']) + self.add_vpr_registertype(['dff', + 'dffe', + 'dffeh', + 'dffehl', + 'dffehlr', + 'dffehr', + 'dffel', + 'dffelr', + 'dffer', + 'dffh', + 'dffhl', + 'dffhlr', + 'dffhr', + 'dffl', + 'dfflr', + 'dffr']) + + self.add_yosys_dsptype(['dsp_mult', + 'efpga_acc', + 'efpga_acc_regi', + 'efpga_adder', + 'efpga_adder_regi', + 'efpga_adder_regio', + 'efpga_adder_rego', + 'efpga_macc', + 'efpga_macc_pipe', + 'efpga_macc_pipe_regi', + 'efpga_macc_regi', + 'efpga_mult', + 'efpga_mult_addc', + 'efpga_mult_addc_regi', + 'efpga_mult_addc_regio', + 'efpga_mult_addc_rego', + 'efpga_mult_regi', + 'efpga_mult_regio', + 'efpga_mult_rego']) + self.add_vpr_dsptype(['dsp_mult', + 'efpga_acc', + 'efpga_acc_regi', + 'efpga_adder', + 'efpga_adder_regi', + 'efpga_adder_regio', + 'efpga_adder_rego', + 'efpga_macc', + 'efpga_macc_pipe', + 'efpga_macc_pipe_regi', + 'efpga_macc_regi', + 'efpga_mult', + 'efpga_mult_addc', + 'efpga_mult_addc_regi', + 'efpga_mult_addc_regio', + 'efpga_mult_addc_rego', + 'efpga_mult_regi', + 'efpga_mult_regio', + 'efpga_mult_rego']) + + self.add_yosys_bramtype(['sdpram_1024x16', + 'sdpram_16384x1', + 'sdpram_2048x8', + 'sdpram_4096x4', + 'sdpram_8192x2', + 'spram_1024x16', + 'spram_16384x1', + 'spram_2048x8', + 'spram_4096x4', + 'spram_512x32', + 'spram_8192x2', + 'sram_sdp', + 'sram_sp', + 'sram_tdp', + 'tdpram_1024x16', + 'tdpram_16384x1', + 'tdpram_2048x8', + 'tdpram_4096x4', + 'tdpram_8192x2']) + self.add_vpr_bramtype(['sdpram_1024x16', + 'sdpram_16384x1', + 'sdpram_2048x8', + 'sdpram_4096x4', + 'sdpram_8192x2', + 'spram_1024x16', + 'spram_16384x1', + 'spram_2048x8', + 'spram_4096x4', + 'spram_512x32', + 'spram_8192x2', + 'sram_sdp', + 'sram_sp', + 'sram_tdp', + 'tdpram_1024x16', + 'tdpram_16384x1', + 'tdpram_2048x8', + 'tdpram_4096x4', + 'tdpram_8192x2']) + + # TODO: blackbox_options + + with self.active_dataroot("logik-fpga-z1062"): + self.set("tool", "convert_bitstream", "bitstream_map", 'cad/z1062_bitstream_map.json') + self.set_vpr_constraintsmap('cad/z1062_constraint_map.json') + + self.set_vpr_channelwidth(150) + + with self.active_dataroot("logik-fpga-z1062"): + with self.active_fileset("z1062_opensta_liberty_files"): + self.add_file('cad/vtr_primitives.lib') + self.add_file(['cad/tech_flops.lib', 'cad/tech_dsp.lib', 'cad/tech_bram.lib']) + self.add_opensta_liberty_fileset() + + self.set_vpr_router_lookahead('classic') ######################### if __name__ == "__main__": - fpga = setup() + fpga = z1062 assert fpga.check_filepaths() fpga.write_manifest(f'{fpga.design}.json') diff --git a/pyproject.toml b/pyproject.toml index c5926aa..5fa824a 100644 --- a/pyproject.toml +++ b/pyproject.toml @@ -24,7 +24,7 @@ dynamic = [ "version" ] dependencies = [ - "siliconcompiler >= 0.32.1" + "siliconcompiler >= 0.35.1" ] [tool.setuptools.dynamic] @@ -32,7 +32,7 @@ version = {attr = "logiklib.__version__"} [project.optional-dependencies] test = [ - "pytest==8.4.1", + "pytest==8.4.2", "flake8==7.3.0", "codespell==2.4.1" ] diff --git a/tests/test_fpga_modules.py b/tests/test_fpga_modules.py index e3c5a78..4e28aa6 100644 --- a/tests/test_fpga_modules.py +++ b/tests/test_fpga_modules.py @@ -1,54 +1,24 @@ -import os import pytest -from siliconcompiler import Chip +from logiklib.zeroasic.z1000.z1000 import z1000 +from logiklib.zeroasic.z1002.z1002 import z1002 +from logiklib.zeroasic.z1010.z1010 import z1010 +from logiklib.zeroasic.z1012.z1012 import z1012 +from logiklib.zeroasic.z1060.z1060 import z1060 +from logiklib.zeroasic.z1062.z1062 import z1062 -import logiklib -from logiklib.demo.K6_N8_3x3 import K6_N8_3x3 -from logiklib.demo.K4_N8_6x6 import K4_N8_6x6 -from logiklib.demo.K6_N8_12x12_BD import K6_N8_12x12_BD -from logiklib.demo.K6_N8_28x28_BD import K6_N8_28x28_BD -from logiklib.zeroasic.z1000 import z1000 -from logiklib.zeroasic.z1002 import z1002 -from logiklib.zeroasic.z1010 import z1010 -from logiklib.zeroasic.z1012 import z1012 -from logiklib.zeroasic.z1060 import z1060 -from logiklib.zeroasic.z1062 import z1062 +all_parts = (z1000, + z1002, + z1010, + z1012, + z1060, + z1062 + ) -all_modules = (K6_N8_3x3, - K4_N8_6x6, - K6_N8_12x12_BD, - K6_N8_28x28_BD, - z1000, - z1002, - z1010, - z1012, - z1060, - z1062) +@pytest.mark.parametrize("part", all_parts) +def test_filepaths(part): + fpga = part() -def test_all_modules(): - ''' - Test to ensure all available modules are in the testing list - ''' - base_dir = os.path.abspath(os.path.dirname(logiklib.__file__)) - found_modules = [] - for pathdir, _, files in os.walk(base_dir): - if len(os.path.relpath(pathdir, base_dir).split("/")) == 2: - for f in files: - if f != "__init__.py" and f.endswith(".py"): - found_modules.append(os.path.join(pathdir, f)) - - assert set(found_modules) == set([mod.__file__ for mod in all_modules]) - - -@pytest.mark.parametrize("module", all_modules) -def test_filepaths(module): - ''' - Loads a module and ensures their filepaths are available - ''' - chip = Chip('') - chip.use(module) - - assert chip.check_filepaths() + assert fpga.name == fpga.__class__.__name__