Escaped Identifiers not conformed to IEEE 1800 #1273
Description
The IEEE 1800 Standard specifies:
escaped_identifier ::= \ { any_printable_ASCII_character_except_white_space } white_space
Meaning \!special!\ should be represented as !special!\ on the tooling side.
But right now, for Verilog:
// This file is public domain, it can be freely copied without restrictions.
// SPDX-License-Identifier: CC0-1.0
`timescale 1us/1us
module dff (
input logic clk, d,
input logic _reset_n, // starts with underscore hence needs __getitem__ access
output logic q,
output logic \!special!\ // escaped identifier hence needs __getitem__ access
);
always @(posedge clk) begin
if (!_reset_n) begin
q <= 1'b0;
\!special!\ <= 1'b0;
end else begin
q <= d;
\!special!\ <= ~d; // invert d for the special signal
end
end
endmodule
On Icarus Verilog:
-> import pdb; pdb.set_trace()
(Pdb) dir(dut)
['!special!\\\\', '__abstractmethods__', '__bool__', '__class__', '__class_getitem__', '__delattr__', '__dict__', '__dir__', '__doc__', '__eq__', '__firstlineno__', '__format__', '__ge__', '__getattr__', '__getattribute__', '__getitem__', '__getstate__', '__gt__', '__hash__', '__init__', '__init_subclass__', '__iter__', '__le__', '__len__', '__lt__', '__module__', '__ne__', '__new__', '__orig_bases__', '__parameters__', '__reduce__', '__reduce_ex__', '__repr__', '__setattr__', '__sizeof__', '__slots__', '__static_attributes__', '__str__', '__subclasshook__', '__weakref__', '_abc_impl', '_child_path', '_def_file', '_def_name', '_discover_all', '_discovered', '_get', '_get_handle_by_key', '_handle', '_id', '_items', '_keys', '_log', '_name', '_path', '_reset_n', '_sub_handle_key', '_sub_handles', '_type', '_values', 'clk', 'd', 'q']
which is wrong, so when I try to compare to verilator and other simulators, they also say something problematic.
On Verilator
-> import pdb; pdb.set_trace()
(Pdb) dir(dut)
['\\!special!\\ ', '__abstractmethods__', '__bool__', '__class__', '__class_getitem__', '__delattr__', '__dict__', '__dir__', '__doc__', '__eq__', '__firstlineno__', '__format__', '__ge__', '__getattr__', '__getattribute__', '__getitem__', '__getstate__', '__gt__', '__hash__', '__init__', '__init_subclass__', '__iter__', '__le__', '__len__', '__lt__', '__module__', '__ne__', '__new__', '__orig_bases__', '__parameters__', '__reduce__', '__reduce_ex__', '__repr__', '__setattr__', '__sizeof__', '__slots__', '__static_attributes__', '__str__', '__subclasshook__', '__weakref__', '_abc_impl', '_child_path', '_def_file', '_def_name', '_discover_all', '_discovered', '_get', '_get_handle_by_key', '_handle', '_id', '_items', '_keys', '_log', '_name', '_path', '_reset_n', '_sub_handle_key', '_sub_handles', '_type', '_values', 'clk', 'd', 'q']
The choice is either to follow the IEEE standard or to follow what other simulators do.