From 13ddfff073ab53f40a2dd414ffea9570a36fd257 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 10 Jul 2025 16:19:55 +0200 Subject: [PATCH 1/9] system(wba) update STM32WBAxx HAL Drivers to v1.7.0 Included in STM32CubeWBA FW v1.7.0 Signed-off-by: Frederic Pillon --- .../Inc/Legacy/stm32_hal_legacy.h | 38 +- .../Inc/stm32wbaxx_hal.h | 47 +- .../Inc/stm32wbaxx_hal_conf_template.h | 25 +- .../Inc/stm32wbaxx_hal_cortex.h | 11 + .../Inc/stm32wbaxx_hal_cryp.h | 28 +- .../Inc/stm32wbaxx_hal_dma.h | 107 +- .../Inc/stm32wbaxx_hal_dma_ex.h | 94 +- .../Inc/stm32wbaxx_hal_exti.h | 92 +- .../Inc/stm32wbaxx_hal_flash.h | 218 + .../Inc/stm32wbaxx_hal_flash_ex.h | 140 +- .../Inc/stm32wbaxx_hal_gpio.h | 4 + .../Inc/stm32wbaxx_hal_gpio_ex.h | 240 + .../Inc/stm32wbaxx_hal_gtzc.h | 53 +- .../Inc/stm32wbaxx_hal_hcd.h | 633 +++ .../Inc/stm32wbaxx_hal_hsem.h | 2 + .../Inc/stm32wbaxx_hal_i2c_ex.h | 48 +- .../Inc/stm32wbaxx_hal_icache.h | 14 +- .../Inc/stm32wbaxx_hal_irda_ex.h | 73 + .../Inc/stm32wbaxx_hal_pcd.h | 683 +++ .../Inc/stm32wbaxx_hal_pcd_ex.h | 91 + .../Inc/stm32wbaxx_hal_pwr.h | 334 +- .../Inc/stm32wbaxx_hal_pwr_ex.h | 202 + .../Inc/stm32wbaxx_hal_ramcfg.h | 7 +- .../Inc/stm32wbaxx_hal_rcc.h | 487 +- .../Inc/stm32wbaxx_hal_rcc_ex.h | 253 + .../Inc/stm32wbaxx_hal_rng.h | 1 + .../Inc/stm32wbaxx_hal_rtc_ex.h | 9 +- .../Inc/stm32wbaxx_hal_sai.h | 10 + .../Inc/stm32wbaxx_hal_sai_ex.h | 6 + .../Inc/stm32wbaxx_hal_smartcard.h | 79 +- .../Inc/stm32wbaxx_hal_smbus_ex.h | 48 +- .../Inc/stm32wbaxx_hal_spi_ex.h | 40 +- .../Inc/stm32wbaxx_hal_tim.h | 409 +- .../Inc/stm32wbaxx_hal_tim_ex.h | 278 +- .../Inc/stm32wbaxx_hal_uart.h | 9 +- .../Inc/stm32wbaxx_hal_uart_ex.h | 96 +- .../Inc/stm32wbaxx_hal_usart.h | 85 +- .../Inc/stm32wbaxx_ll_adc.h | 23 +- .../Inc/stm32wbaxx_ll_bus.h | 641 +++ .../Inc/stm32wbaxx_ll_comp.h | 4 +- .../Inc/stm32wbaxx_ll_cortex.h | 8 +- .../Inc/stm32wbaxx_ll_dma.h | 362 +- .../Inc/stm32wbaxx_ll_exti.h | 29 + .../Inc/stm32wbaxx_ll_gpio.h | 68 +- .../Inc/stm32wbaxx_ll_i2c.h | 10 +- .../Inc/stm32wbaxx_ll_lptim.h | 23 +- .../Inc/stm32wbaxx_ll_lpuart.h | 4 + .../Inc/stm32wbaxx_ll_pwr.h | 735 +++ .../Inc/stm32wbaxx_ll_rcc.h | 211 +- .../Inc/stm32wbaxx_ll_rng.h | 8 + .../Inc/stm32wbaxx_ll_rtc.h | 30 +- .../Inc/stm32wbaxx_ll_spi.h | 4 +- .../Inc/stm32wbaxx_ll_system.h | 156 +- .../Inc/stm32wbaxx_ll_tim.h | 227 +- .../Inc/stm32wbaxx_ll_usart.h | 8 +- .../Inc/stm32wbaxx_ll_usb.h | 1296 +++++ .../Inc/stm32wbaxx_ll_utils.h | 18 + .../Drivers/STM32WBAxx_HAL_Driver/README.md | 2 +- .../STM32WBAxx_HAL_Driver/Release_Notes.html | 905 ++- .../Src/stm32wbaxx_hal.c | 103 +- .../Src/stm32wbaxx_hal_adc.c | 43 +- .../Src/stm32wbaxx_hal_cortex.c | 19 + .../Src/stm32wbaxx_hal_cryp.c | 188 +- .../Src/stm32wbaxx_hal_cryp_ex.c | 70 +- .../Src/stm32wbaxx_hal_dma.c | 53 +- .../Src/stm32wbaxx_hal_dma_ex.c | 36 +- .../Src/stm32wbaxx_hal_exti.c | 12 +- .../Src/stm32wbaxx_hal_flash.c | 105 +- .../Src/stm32wbaxx_hal_flash_ex.c | 588 +- .../Src/stm32wbaxx_hal_gpio.c | 47 +- .../Src/stm32wbaxx_hal_gtzc.c | 46 +- .../Src/stm32wbaxx_hal_hash.c | 2 + .../Src/stm32wbaxx_hal_hcd.c | 4848 +++++++++++++++++ .../Src/stm32wbaxx_hal_hsem.c | 2 + .../Src/stm32wbaxx_hal_i2c.c | 4 + .../Src/stm32wbaxx_hal_pcd.c | 3042 +++++++++++ .../Src/stm32wbaxx_hal_pcd_ex.c | 530 ++ .../Src/stm32wbaxx_hal_pwr.c | 30 + .../Src/stm32wbaxx_hal_pwr_ex.c | 402 ++ .../Src/stm32wbaxx_hal_ramcfg.c | 9 +- .../Src/stm32wbaxx_hal_rcc_ex.c | 259 + .../Src/stm32wbaxx_hal_rng.c | 6 + .../Src/stm32wbaxx_hal_rng_ex.c | 13 + .../Src/stm32wbaxx_hal_rtc_ex.c | 10 +- .../Src/stm32wbaxx_hal_sai_ex.c | 2 +- .../Src/stm32wbaxx_hal_tim.c | 234 +- .../Src/stm32wbaxx_hal_tim_ex.c | 375 +- .../stm32wbaxx_hal_timebase_tim_template.c | 7 +- .../Src/stm32wbaxx_hal_uart.c | 129 +- .../Src/stm32wbaxx_hal_uart_ex.c | 49 +- .../Src/stm32wbaxx_ll_dma.c | 135 +- .../Src/stm32wbaxx_ll_gpio.c | 25 +- .../Src/stm32wbaxx_ll_i2c.c | 24 +- .../Src/stm32wbaxx_ll_rcc.c | 282 + .../Src/stm32wbaxx_ll_spi.c | 17 +- .../Src/stm32wbaxx_ll_tim.c | 49 +- .../Src/stm32wbaxx_ll_usart.c | 20 +- .../Src/stm32wbaxx_ll_usb.c | 3766 +++++++++++++ .../Drivers/STM32YYxx_HAL_Driver_version.md | 2 +- 99 files changed, 24543 insertions(+), 806 deletions(-) create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_hcd.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_pcd.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_pcd_ex.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_usb.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_hcd.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_pcd.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_pcd_ex.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_usb.c diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index 12ad24635c..da4d4112ab 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -472,9 +472,9 @@ extern "C" { #define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE #define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD #define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD -#if !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32H7) +#if !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32H7) && !defined(STM32H5) #define PAGESIZE FLASH_PAGE_SIZE -#endif /* STM32F2 && STM32F4 && STM32F7 && STM32H7 */ +#endif /* STM32F2 && STM32F4 && STM32F7 && STM32H7 && STM32H5 */ #define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE #define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD #define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD @@ -538,6 +538,10 @@ extern "C" { #define FLASH_FLAG_WDW FLASH_FLAG_WBNE #define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL #endif /* STM32H7 */ +#if defined(STM32H7RS) +#define FLASH_OPTKEY1 FLASH_OPT_KEY1 +#define FLASH_OPTKEY2 FLASH_OPT_KEY2 +#endif /* STM32H7RS */ #if defined(STM32U5) #define OB_USER_nRST_STOP OB_USER_NRST_STOP #define OB_USER_nRST_STDBY OB_USER_NRST_STDBY @@ -560,6 +564,9 @@ extern "C" { #define OB_nBOOT0_RESET OB_NBOOT0_RESET #define OB_nBOOT0_SET OB_NBOOT0_SET #endif /* STM32U0 */ +#if defined(STM32H5) +#define FLASH_ECC_AREA_EDATA FLASH_ECC_AREA_EDATA_BANK1 +#endif /* STM32H5 */ /** * @} @@ -1279,10 +1286,10 @@ extern "C" { #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 -#if defined(STM32H5) || defined(STM32H7RS) +#if defined(STM32H5) || defined(STM32H7RS) || defined(STM32N6) #define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE #define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM -#endif /* STM32H5 || STM32H7RS */ +#endif /* STM32H5 || STM32H7RS || STM32N6 */ #if defined(STM32WBA) #define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE @@ -1294,27 +1301,27 @@ extern "C" { #define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL #endif /* STM32WBA */ -#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6) #define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE #define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL -#endif /* STM32H5 || STM32WBA || STM32H7RS */ +#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ -#if defined(STM32F7) +#if defined(STM32F7) || defined(STM32WB) #define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK #define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK -#endif /* STM32F7 */ +#endif /* STM32F7 || STM32WB */ #if defined(STM32H7) #define RTC_TAMPCR_TAMPXE RTC_TAMPER_X #define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT #endif /* STM32H7 */ -#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0) +#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0) || defined(STM32WB) #define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1 #define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2 #define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3 #define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP -#endif /* STM32F7 || STM32H7 || STM32L0 */ +#endif /* STM32F7 || STM32H7 || STM32L0 || STM32WB */ /** * @} @@ -1481,7 +1488,7 @@ extern "C" { #define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 #endif -#if defined(STM32U5) +#if defined(STM32U5) || defined(STM32MP2) #define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS #define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK #endif @@ -2029,12 +2036,12 @@ extern "C" { /** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose * @{ */ -#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6) #define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey #define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock #define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock #define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets -#endif /* STM32H5 || STM32WBA || STM32H7RS */ +#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ /** * @} @@ -3695,7 +3702,7 @@ extern "C" { #endif #if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \ - defined(STM32WL) || defined(STM32C0) || defined(STM32H7RS) || defined(STM32U0) + defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || defined(STM32U0) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK @@ -3946,7 +3953,8 @@ extern "C" { */ #if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \ defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ - defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32H7RS) || defined (STM32U0) + defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32N6) || \ + defined (STM32H7RS) || defined (STM32U0) || defined (STM32U3) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal.h index ad03cc0417..f7d84b9398 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal.h @@ -78,10 +78,10 @@ extern HAL_TickFreqTypeDef uwTickFreq; /** * @brief STM32WBAxx HAL Driver version number */ -#define __STM32WBAxx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32WBAxx_HAL_VERSION_SUB1 (0x05U) /*!< [23:16] sub1 version */ -#define __STM32WBAxx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ -#define __STM32WBAxx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ +#define __STM32WBAxx_HAL_VERSION_MAIN (0x01UL) /*!< [31:24] main version */ +#define __STM32WBAxx_HAL_VERSION_SUB1 (0x07UL) /*!< [23:16] sub1 version */ +#define __STM32WBAxx_HAL_VERSION_SUB2 (0x00UL) /*!< [15:8] sub2 version */ +#define __STM32WBAxx_HAL_VERSION_RC (0x00UL) /*!< [7:0] release candidate */ #define __STM32WBAxx_HAL_VERSION ((__STM32WBAxx_HAL_VERSION_MAIN << 24U)\ |(__STM32WBAxx_HAL_VERSION_SUB1 << 16U)\ |(__STM32WBAxx_HAL_VERSION_SUB2 << 8U )\ @@ -150,6 +150,27 @@ extern HAL_TickFreqTypeDef uwTickFreq; * @} */ +#if defined(VREFBUF) +/** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale + * @{ + */ +#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_CSR_VRS_OUT1 /*!< Voltage reference scale 0 (VREF_OUT1) */ +#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_OUT2 /*!< Voltage reference scale 1 (VREF_OUT2) */ +#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_OUT3 /*!< Voltage reference scale 2 (VREF_OUT3) */ +#define SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_CSR_VRS_OUT4 /*!< Voltage reference scale 3 (VREF_OUT4) */ +/** + * @} + */ + +/** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance + * @{ + */ +#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE 0x00000000U /*!< VREF_plus pin is internally connected to Voltage reference buffer output */ +#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */ +/** + * @} + */ +#endif /* VREFBUF */ /** @defgroup SYSCFG_Flags_Definition Flags * @{ @@ -524,6 +545,17 @@ extern HAL_TickFreqTypeDef uwTickFreq; ((__CONFIG__) == SYSCFG_BREAK_SRAM2_PARITY) || \ ((__CONFIG__) == SYSCFG_BREAK_LOCKUP)) +#if defined(VREFBUF) +#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \ + ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1) || \ + ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE2) || \ + ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE3)) + +#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \ + ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE)) + +#define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM)) +#endif /* VREFBUF */ #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_ALL) != 0x00U) && \ (((__PIN__) & ~SYSCFG_FASTMODEPLUS_ALL) == 0x00U)) @@ -646,6 +678,13 @@ void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void); void HAL_SYSCFG_EnableIOAnalogSwitchVdd(void); void HAL_SYSCFG_DisableIOAnalogSwitchVdd(void); +#ifdef VREFBUF +void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling); +void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode); +void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue); +HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void); +void HAL_SYSCFG_DisableVREFBUF(void); +#endif /* VREFBUF */ #ifdef SYSCFG_OTGHSPHYCR_EN void HAL_SYSCFG_SetOTGPHYReferenceClockSelection(uint32_t RefClockSelection); diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_conf_template.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_conf_template.h index a9baaa8ba7..33429676bb 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_conf_template.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_conf_template.h @@ -45,12 +45,14 @@ extern "C" { #define HAL_GPIO_MODULE_ENABLED #define HAL_GTZC_MODULE_ENABLED #define HAL_HASH_MODULE_ENABLED +#define HAL_HCD_MODULE_ENABLED #define HAL_HSEM_MODULE_ENABLED #define HAL_I2C_MODULE_ENABLED #define HAL_ICACHE_MODULE_ENABLED #define HAL_IRDA_MODULE_ENABLED #define HAL_IWDG_MODULE_ENABLED #define HAL_LPTIM_MODULE_ENABLED +#define HAL_PCD_MODULE_ENABLED #define HAL_PKA_MODULE_ENABLED #define HAL_PWR_MODULE_ENABLED #define HAL_RAMCFG_MODULE_ENABLED @@ -66,6 +68,7 @@ extern "C" { #define HAL_UART_MODULE_ENABLED #define HAL_USART_MODULE_ENABLED #define HAL_WWDG_MODULE_ENABLED +#define HAL_XSPI_MODULE_ENABLED /* ########################## Oscillator Values adaptation ####################*/ /** @@ -159,10 +162,12 @@ extern "C" { #define USE_HAL_COMP_REGISTER_CALLBACKS 0U /* COMP register callback disabled */ #define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ #define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ +#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ #define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ #define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ #define USE_HAL_IWDG_REGISTER_CALLBACKS 0U /* IWDG register callback disabled */ #define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ #define USE_HAL_PKA_REGISTER_CALLBACKS 0U /* PKA register callback disabled */ #define USE_HAL_RAMCFG_REGISTER_CALLBACKS 0U /* RAMCFG register callback disabled */ #define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ @@ -176,6 +181,7 @@ extern "C" { #define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ #define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ #define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ +#define USE_HAL_XSPI_REGISTER_CALLBACKS 0U /* XSPI register callback disabled */ /* ################## SPI peripheral configuration ########################## */ @@ -201,6 +207,10 @@ extern "C" { #include "stm32wbaxx_hal_dma.h" #endif /* HAL_DMA_MODULE_ENABLED */ +#ifdef HAL_RCC_MODULE_ENABLED +#include "stm32wbaxx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + #ifdef HAL_ADC_MODULE_ENABLED #include "stm32wbaxx_hal_adc.h" #endif /* HAL_ADC_MODULE_ENABLED */ @@ -241,6 +251,10 @@ extern "C" { #include "stm32wbaxx_hal_hash.h" #endif /* HAL_HASH_MODULE_ENABLED */ +#ifdef HAL_HCD_MODULE_ENABLED +#include "stm32wbaxx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + #ifdef HAL_HSEM_MODULE_ENABLED #include "stm32wbaxx_hal_hsem.h" #endif /* HAL_HSEM_MODULE_ENABLED */ @@ -265,6 +279,10 @@ extern "C" { #include "stm32wbaxx_hal_lptim.h" #endif /* HAL_LPTIM_MODULE_ENABLED */ +#ifdef HAL_PCD_MODULE_ENABLED +#include "stm32wbaxx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + #ifdef HAL_PKA_MODULE_ENABLED #include "stm32wbaxx_hal_pka.h" #endif /* HAL_PKA_MODULE_ENABLED */ @@ -277,10 +295,6 @@ extern "C" { #include "stm32wbaxx_hal_ramcfg.h" #endif /* HAL_RAMCFG_MODULE_ENABLED */ -#ifdef HAL_RCC_MODULE_ENABLED -#include "stm32wbaxx_hal_rcc.h" -#endif /* HAL_RCC_MODULE_ENABLED */ - #ifdef HAL_RNG_MODULE_ENABLED #include "stm32wbaxx_hal_rng.h" #endif /* HAL_RNG_MODULE_ENABLED */ @@ -325,6 +339,9 @@ extern "C" { #include "stm32wbaxx_hal_wwdg.h" #endif /* HAL_WWDG_MODULE_ENABLED */ +#ifdef HAL_XSPI_MODULE_ENABLED +#include "stm32wbaxx_hal_xspi.h" +#endif /* HAL_XSPI_MODULE_ENABLED */ /* Exported macro ------------------------------------------------------------*/ #ifdef USE_FULL_ASSERT diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_cortex.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_cortex.h index 2c6ff05071..504a1aa8b8 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_cortex.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_cortex.h @@ -114,6 +114,9 @@ typedef struct #define SYSTICK_CLKSOURCE_LSI 0x00000001U /*!< LSI clock selected as SysTick clock source */ #define SYSTICK_CLKSOURCE_LSE 0x00000002U /*!< LSE clock selected as SysTick clock source */ #define SYSTICK_CLKSOURCE_HCLK 0x00000004U /*!< AHB clock selected as SysTick clock source */ +#if !defined (STM32WBA50xx) && !defined (STM32WBA52xx) && !defined (STM32WBA54xx) && !defined (STM32WBA55xx) && !defined (STM32WBA5Mxx) +#define SYSTICK_CLKSOURCE_HSI_DIV4 0x00000008U /*!< HSI clock divided by 4 selected as SysTick clock source */ +#endif /** * @} */ @@ -333,10 +336,18 @@ void HAL_MPU_ConfigMemoryAttributes_NS(MPU_Attributes_InitTypeDef *MPU_Attribute #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) > SysTick_IRQn) +#if !defined (STM32WBA50xx) && !defined (STM32WBA52xx) && !defined (STM32WBA54xx) && !defined (STM32WBA55xx) && !defined (STM32WBA5Mxx) +#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_LSI) || \ + ((SOURCE) == SYSTICK_CLKSOURCE_LSE) || \ + ((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ + ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)|| \ + ((SOURCE) == SYSTICK_CLKSOURCE_HSI_DIV4)) +#else #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_LSI) || \ ((SOURCE) == SYSTICK_CLKSOURCE_LSE) || \ ((SOURCE) == SYSTICK_CLKSOURCE_HCLK)|| \ ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) +#endif #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ ((STATE) == MPU_REGION_DISABLE)) diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_cryp.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_cryp.h index b862c06d5c..6288f6089b 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_cryp.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_cryp.h @@ -484,25 +484,25 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< point * @arg @ref CRYP_FLAG_KEIF Key error flag * @arg @ref CRYP_FLAG_RWEIF Read/write Error flag - * @retval The state of __FLAG__ (TRUE or FALSE). + * @retval The state of __FLAG__ (FlagStatus). */ #define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) (\ - ((__FLAG__) == CRYP_FLAG_KEYVALID )?(((__HANDLE__)->Instance->SR \ - & (CRYP_FLAG_KEYVALID)) == (CRYP_FLAG_KEYVALID)) : \ - ((__FLAG__) == CRYP_FLAG_BUSY )?(((__HANDLE__)->Instance->SR \ - & (CRYP_FLAG_BUSY)) == (CRYP_FLAG_BUSY)) : \ - ((__FLAG__) == CRYP_FLAG_WRERR )?(((__HANDLE__)->Instance->SR \ + ((__FLAG__) == CRYP_FLAG_KEYVALID )?((((__HANDLE__)->Instance->SR \ + & (CRYP_FLAG_KEYVALID)) == (CRYP_FLAG_KEYVALID))?SET:RESET) : \ + ((__FLAG__) == CRYP_FLAG_BUSY )?((((__HANDLE__)->Instance->SR \ + & (CRYP_FLAG_BUSY)) == (CRYP_FLAG_BUSY))?SET:RESET) : \ + ((__FLAG__) == CRYP_FLAG_WRERR )?((((__HANDLE__)->Instance->SR \ & (CRYP_FLAG_WRERR & 0x7FFFFFFFU)) == \ - (CRYP_FLAG_WRERR & 0x7FFFFFFFU)) : \ - ((__FLAG__) == CRYP_FLAG_RDERR )?(((__HANDLE__)->Instance->SR \ + (CRYP_FLAG_WRERR & 0x7FFFFFFFU))?SET:RESET) : \ + ((__FLAG__) == CRYP_FLAG_RDERR )?((((__HANDLE__)->Instance->SR \ & (CRYP_FLAG_RDERR & 0x7FFFFFFFU)) == \ - (CRYP_FLAG_RDERR & 0x7FFFFFFFU)) : \ - ((__FLAG__) == CRYP_FLAG_KEIF )?(((__HANDLE__)->Instance->ISR \ - & (CRYP_FLAG_KEIF)) == (CRYP_FLAG_KEIF)) : \ - ((__FLAG__) == CRYP_FLAG_RWEIF )?(((__HANDLE__)->Instance->ISR \ - & (CRYP_FLAG_RWEIF)) == (CRYP_FLAG_RWEIF)) : \ - (((__HANDLE__)->Instance->ISR & (CRYP_FLAG_CCF)) == (CRYP_FLAG_CCF))) + (CRYP_FLAG_RDERR & 0x7FFFFFFFU))?SET:RESET) : \ + ((__FLAG__) == CRYP_FLAG_KEIF )?((((__HANDLE__)->Instance->ISR \ + & (CRYP_FLAG_KEIF)) == (CRYP_FLAG_KEIF))?SET:RESET) : \ + ((__FLAG__) == CRYP_FLAG_RWEIF )?((((__HANDLE__)->Instance->ISR \ + & (CRYP_FLAG_RWEIF)) == (CRYP_FLAG_RWEIF))?SET:RESET) : \ + ((((__HANDLE__)->Instance->ISR & (CRYP_FLAG_CCF)) == (CRYP_FLAG_CCF)))?SET:RESET) /** @brief Clear the CRYP pending status flag. * @param __HANDLE__ specifies the CRYP handle. diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_dma.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_dma.h index 58b3d100bf..7c8067dd8c 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_dma.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_dma.h @@ -250,6 +250,48 @@ typedef struct __DMA_HandleTypeDef * @brief DMA Request Selection * @{ */ +#if defined (LPDMA1) +/* LPDMA1 requests */ +#define LPDMA1_REQUEST_ADC4 0U /*!< LPDMA1 HW request is ADC4 */ + +#define LPDMA1_REQUEST_SPI3_RX 3U /*!< LPDMA1 HW request is SPI3_RX */ +#define LPDMA1_REQUEST_SPI3_TX 4U /*!< LPDMA1 HW request is SPI3_TX */ +#define LPDMA1_REQUEST_I2C1_RX 5U /*!< LPDMA1 HW request is I2C1_RX */ +#define LPDMA1_REQUEST_I2C1_TX 6U /*!< LPDMA1 HW request is I2C1_TX */ +#define LPDMA1_REQUEST_I2C1_EVC 7U /*!< LPDMA1 HW request is I2C1_EVC */ +#define LPDMA1_REQUEST_I2C3_RX 8U /*!< LPDMA1 HW request is I2C3_RX */ +#define LPDMA1_REQUEST_I2C3_TX 9U /*!< LPDMA1 HW request is I2C3_TX */ +#define LPDMA1_REQUEST_I2C3_EVC 10U /*!< LPDMA1 HW request is I2C3_EVC */ +#define LPDMA1_REQUEST_USART1_RX 11U /*!< LPDMA1 HW request is USART1_RX */ +#define LPDMA1_REQUEST_USART1_TX 12U /*!< LPDMA1 HW request is USART1_TX */ + +#define LPDMA1_REQUEST_LPUART1_RX 15U /*!< LPDMA1 HW request is LPUART1_RX */ +#define LPDMA1_REQUEST_LPUART1_TX 16U /*!< LPDMA1 HW request is LPUART1_TX */ +#define LPDMA1_REQUEST_SAI1_A 17U /*!< LPDMA1 HW request is SAI1_A */ +#define LPDMA1_REQUEST_SAI1_B 18U /*!< LPDMA1 HW request is SAI1_B */ + +#define LPDMA1_REQUEST_TIM2_CH1 26U /*!< LPDMA1 HW request is TIM2_CH1 */ +#define LPDMA1_REQUEST_TIM2_CH2 27U /*!< LPDMA1 HW request is TIM2_CH2 */ +#define LPDMA1_REQUEST_TIM2_CH3 28U /*!< LPDMA1 HW request is TIM2_CH3 */ +#define LPDMA1_REQUEST_TIM2_CH4 29U /*!< LPDMA1 HW request is TIM2_CH4 */ +#define LPDMA1_REQUEST_TIM2_UP 30U /*!< LPDMA1 HW request is TIM2_UP */ +#define LPDMA1_REQUEST_TIM16_CH1 31U /*!< LPDMA1 HW request is TIM16_CH1 */ +#define LPDMA1_REQUEST_TIM16_UP 32U /*!< LPDMA1 HW request is TIM16_UP */ +#define LPDMA1_REQUEST_TIM17_CH1 33U /*!< LPDMA1 HW request is TIM17_CH1 */ +#define LPDMA1_REQUEST_TIM17_UP 34U /*!< LPDMA1 HW request is TIM17_UP */ + +#define LPDMA1_REQUEST_AES_IN 35U /*!< LPDMA1 HW request is AES_IN */ +#define LPDMA1_REQUEST_AES_OUT 36U /*!< LPDMA1 HW request is AES_OUT */ +#define LPDMA1_REQUEST_HASH_IN 37U /*!< LPDMA1 HW request is HASH_IN */ +#define LPDMA1_REQUEST_LPTIM1_IC1 38U /*!< LPDMA1 HW request is LPTIM1_IC1 */ +#define LPDMA1_REQUEST_LPTIM1_IC2 39U /*!< LPDMA1 HW request is LPTIM1_IC2 */ +#define LPDMA1_REQUEST_LPTIM1_UE 40U /*!< LPDMA1 HW request is LPTIM1_UE */ +#define LPDMA1_REQUEST_LPTIM2_IC1 41U /*!< LPDMA1 HW request is LPTIM2_IC1 */ +#define LPDMA1_REQUEST_LPTIM2_IC2 42U /*!< LPDMA1 HW request is LPTIM2_IC2 */ +#define LPDMA1_REQUEST_LPTIM2_UE 46U /*!< LPDMA1 HW request is LPTIM2_UE */ + +#define LPDMA1_REQUEST_XSPI1 44U /*!< LPDMA1 HW request is XSPI1 */ +#else /* GPDMA1 requests */ #define GPDMA1_REQUEST_ADC4 0U /*!< GPDMA1 HW request is ADC4 */ #if defined (SPI1) @@ -321,6 +363,32 @@ typedef struct __DMA_HandleTypeDef #define GPDMA1_REQUEST_LPTIM2_IC2 50U /*!< GPDMA1 HW request is LPTIM2_IC2 */ #define GPDMA1_REQUEST_LPTIM2_UE 51U /*!< GPDMA1 HW request is LPTIM2_UE */ #endif /* LPTIM2 */ +#if defined (SPI2) +#define GPDMA1_REQUEST_SPI2_RX 52U /*!< GPDMA1 HW request is SPI2_RX */ +#define GPDMA1_REQUEST_SPI2_TX 53U /*!< GPDMA1 HW request is SPI2_TX */ +#endif /* SPI2 */ +#if defined (I2C2) +#define GPDMA1_REQUEST_I2C2_RX 54U /*!< GPDMA1 HW request is I2C2_RX */ +#define GPDMA1_REQUEST_I2C2_TX 55U /*!< GPDMA1 HW request is I2C2_TX */ +#define GPDMA1_REQUEST_I2C2_EVC 56U /*!< GPDMA1 HW request is I2C2_EVC */ +#endif /* I2C2 */ +#if defined (I2C4) +#define GPDMA1_REQUEST_I2C4_RX 57U /*!< GPDMA1 HW request is I2C4_RX */ +#define GPDMA1_REQUEST_I2C4_TX 58U /*!< GPDMA1 HW request is I2C4_TX */ +#define GPDMA1_REQUEST_I2C4_EVC 59U /*!< GPDMA1 HW request is I2C4_EVC */ +#endif /* I2C4 */ +#if defined (TIM4) +#define GPDMA1_REQUEST_TIM4_CH1 60U /*!< GPDMA1 HW request is TIM4_CH1 */ +#define GPDMA1_REQUEST_TIM4_CH2 61U /*!< GPDMA1 HW request is TIM4_CH2 */ +#define GPDMA1_REQUEST_TIM4_CH3 62U /*!< GPDMA1 HW request is TIM4_CH3 */ +#define GPDMA1_REQUEST_TIM4_CH4 63U /*!< GPDMA1 HW request is TIM4_CH4 */ +#define GPDMA1_REQUEST_TIM4_UP 64U /*!< GPDMA1 HW request is TIM4_UP */ +#endif /* TIM4 */ +#if defined (USART3) +#define GPDMA1_REQUEST_USART3_RX 65U /*!< GPDMA1 HW request is USART3_RX */ +#define GPDMA1_REQUEST_USART3_TX 66U /*!< GPDMA1 HW request is USART3_TX */ +#endif /* USART3 */ +#endif /* LPDMA1 */ /* Software request */ #define DMA_REQUEST_SW DMA_CTR2_SWREQ /*!< DMA SW request */ @@ -342,9 +410,16 @@ typedef struct __DMA_HandleTypeDef * @brief DMA transfer direction * @{ */ +#if defined(GPDMA1) #define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ #define DMA_MEMORY_TO_PERIPH DMA_CTR2_DREQ /*!< Memory to peripheral direction */ #define DMA_MEMORY_TO_MEMORY DMA_CTR2_SWREQ /*!< Memory to memory direction */ +#endif /* GPDMA1 */ +#if defined(LPDMA1) +#define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Kept for porting purpose */ +#define DMA_MEMORY_TO_PERIPH DMA_PERIPH_TO_MEMORY /*!< Kept for porting purpose */ +#define DMA_MEMORY_TO_MEMORY DMA_CTR2_SWREQ /*!< Memory to memory direction */ +#endif /* LPDMA1 */ /** * @} */ @@ -408,10 +483,18 @@ typedef struct __DMA_HandleTypeDef * @brief DMA Transfer Allocated Port * @{ */ +#if defined(GPDMA1) #define DMA_SRC_ALLOCATED_PORT0 0x00000000U /*!< Source allocated Port 0 */ #define DMA_SRC_ALLOCATED_PORT1 DMA_CTR1_SAP /*!< Source allocated Port 1 */ #define DMA_DEST_ALLOCATED_PORT0 0x00000000U /*!< Destination allocated Port 0 */ #define DMA_DEST_ALLOCATED_PORT1 DMA_CTR1_DAP /*!< Destination allocated Port 1 */ +#endif /* GPDMA1 */ +#if defined(LPDMA1) +#define DMA_SRC_ALLOCATED_PORT0 0x00000000U /*!< Kept for porting purpose */ +#define DMA_SRC_ALLOCATED_PORT1 DMA_SRC_ALLOCATED_PORT0 /*!< Kept for porting purpose */ +#define DMA_DEST_ALLOCATED_PORT0 0x00000000U /*!< Kept for porting purpose */ +#define DMA_DEST_ALLOCATED_PORT1 DMA_DEST_ALLOCATED_PORT0 /*!< Kept for porting purpose */ +#endif /* LPDMA1 */ /** * @} @@ -660,11 +743,11 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef const *const hdma); * @} */ +#if defined (DMA_PRIVCFGR_PRIV0) /** @defgroup DMA_Exported_Functions_Group4 DMA Attributes Functions * @brief DMA Attributes Functions * @{ */ -#if defined (DMA_PRIVCFGR_PRIV0) HAL_StatusTypeDef HAL_DMA_ConfigChannelAttributes(DMA_HandleTypeDef *const hdma, uint32_t ChannelAttributes); HAL_StatusTypeDef HAL_DMA_GetConfigChannelAttributes(DMA_HandleTypeDef const *const hdma, @@ -677,10 +760,10 @@ HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *cons uint32_t *const pLockState); #endif /* DMA_RCFGLOCKR_LOCK0 */ -#endif /* DMA_PRIVCFGR_PRIV0 */ /** * @} */ +#endif /* DMA_PRIVCFGR_PRIV0 */ /** * @} @@ -723,10 +806,17 @@ HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *cons #define IS_DMA_MODE(MODE) \ ((MODE) == DMA_NORMAL) +#if defined(GPDMA1) #define IS_DMA_DIRECTION(DIRECTION) \ (((DIRECTION) == DMA_PERIPH_TO_MEMORY) || \ ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) +#endif /* GPDMA1 */ +#if defined(LPDMA1) +#define IS_DMA_DIRECTION(DIRECTION) \ + (((DIRECTION) == DMA_PERIPH_TO_MEMORY) || \ + ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) +#endif /* LPDMA1 */ #define IS_DMA_LEVEL_COMPLETE(LEVEL) \ (((LEVEL) == HAL_DMA_FULL_TRANSFER) || \ @@ -763,6 +853,12 @@ HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *cons #define IS_DMA_TRANSFER_ALLOCATED_PORT(ALLOCATED_PORT) \ (((ALLOCATED_PORT) & (~(DMA_CTR1_SAP | DMA_CTR1_DAP))) == 0U) +#if defined (GPDMA1) +#if defined (USART3) +#define IS_DMA_REQUEST(REQUEST) \ + (((REQUEST) == DMA_REQUEST_SW) || \ + ((REQUEST) <= GPDMA1_REQUEST_USART3_TX)) +#else #if defined (LPTIM2) #define IS_DMA_REQUEST(REQUEST) \ (((REQUEST) == DMA_REQUEST_SW) || \ @@ -772,6 +868,13 @@ HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *cons (((REQUEST) == DMA_REQUEST_SW) || \ ((REQUEST) <= GPDMA1_REQUEST_LPTIM1_UE)) #endif /* LPTIM2 */ +#endif /* USART3 */ +#endif /* GPDMA1 */ +#if defined (LPDMA1) +#define IS_DMA_REQUEST(REQUEST) \ + (((REQUEST) == DMA_REQUEST_SW) || \ + ((REQUEST) <= LPDMA1_REQUEST_XSPI1)) +#endif /* LPDMA1 */ #define IS_DMA_BLOCK_HW_REQUEST(MODE) \ (((MODE) == DMA_BREQ_SINGLE_BURST) || \ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_dma_ex.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_dma_ex.h index 2d0832faba..c26656a2a5 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_dma_ex.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_dma_ex.h @@ -186,10 +186,12 @@ typedef struct __DMA_QListTypeDef #define DMA_DATA_LEFTALIGN_RIGHTTRUNC DMA_CTR1_PAM_0 /*!< If source data width > destination data width => Left Aligned Right Truncated down to the destination data width */ +#if defined(GPDMA1) #define DMA_DATA_PACK DMA_CTR1_PAM_1 /*!< If source data width < destination data width => Packed at the destination data width */ #define DMA_DATA_UNPACK DMA_CTR1_PAM_1 /*!< If source data width > destination data width => Unpacked at the destination data width */ +#endif /* GPDMA1 */ /** * @} @@ -233,6 +235,37 @@ typedef struct __DMA_QListTypeDef * @brief DMAEx Trigger Selection * @{ */ +#if defined (LPDMA1) +/* LPDMA1 triggers */ +#define LPDMA1_TRIGGER_EXTI_LINE0 0U /*!< LPDMA1 HW Trigger signal is EXTI_LINE0 */ +#define LPDMA1_TRIGGER_EXTI_LINE1 1U /*!< LPDMA1 HW Trigger signal is EXTI_LINE1 */ +#define LPDMA1_TRIGGER_EXTI_LINE2 2U /*!< LPDMA1 HW Trigger signal is EXTI_LINE2 */ +#define LPDMA1_TRIGGER_EXTI_LINE3 3U /*!< LPDMA1 HW Trigger signal is EXTI_LINE3 */ +#define LPDMA1_TRIGGER_EXTI_LINE4 4U /*!< LPDMA1 HW Trigger signal is EXTI_LINE4 */ +#define LPDMA1_TRIGGER_EXTI_LINE5 5U /*!< LPDMA1 HW Trigger signal is EXTI_LINE5 */ +#define LPDMA1_TRIGGER_EXTI_LINE6 6U /*!< LPDMA1 HW Trigger signal is EXTI_LINE6 */ +#define LPDMA1_TRIGGER_EXTI_LINE7 7U /*!< LPDMA1 HW Trigger signal is EXTI_LINE7 */ +#define LPDMA1_TRIGGER_TAMP_TRG1 8U /*!< LPDMA1 HW Trigger signal is TAMP_TRG1 */ +#define LPDMA1_TRIGGER_TAMP_TRG2 9U /*!< LPDMA1 HW Trigger signal is TAMP_TRG2 */ +#define LPDMA1_TRIGGER_TAMP_TRG3 10U /*!< LPDMA1 HW Trigger signal is TAMP_TRG3 */ +#define LPDMA1_TRIGGER_LPTIM1_CH1 11U /*!< LPDMA1 HW Trigger signal is LPTIM1_CH1 */ +#define LPDMA1_TRIGGER_LPTIM1_CH2 12U /*!< LPDMA1 HW Trigger signal is LPTIM1_CH2 */ +#define LPDMA1_TRIGGER_LPTIM2_CH1 13U /*!< LPDMA1 HW Trigger signal is LPTIM2_CH1 */ +#define LPDMA1_TRIGGER_LPTIM2_CH2 14U /*!< LPDMA1 HW Trigger signal is LPTIM2_CH2 */ +#define LPDMA1_TRIGGER_RTC_ALRA_TRG 15U /*!< LPDMA1 HW Trigger signal is RTC_ALRA_TRG */ +#define LPDMA1_TRIGGER_RTC_ALRB_TRG 16U /*!< LPDMA1 HW Trigger signal is RTC_ALRB_TRG */ +#define LPDMA1_TRIGGER_RTC_WUT_TRG 17U /*!< LPDMA1 HW Trigger signal is RTC_WUT_TRG */ +#define LPDMA1_TRIGGER_LPDMA1_CH0_TCF 18U /*!< LPDMA1 HW Trigger signal is LPDMA1_CH0_TCF */ +#define LPDMA1_TRIGGER_LPDMA1_CH1_TCF 19U /*!< LPDMA1 HW Trigger signal is LPDMA1_CH1_TCF */ +#define LPDMA1_TRIGGER_LPDMA1_CH2_TCF 20U /*!< LPDMA1 HW Trigger signal is LPDMA1_CH2_TCF */ +#define LPDMA1_TRIGGER_LPDMA1_CH3_TCF 21U /*!< LPDMA1 HW Trigger signal is LPDMA1_CH3_TCF */ +#define LPDMA1_TRIGGER_LPDMA1_CH4_TCF 22U /*!< LPDMA1 HW Trigger signal is LPDMA1_CH4_TCF */ +#define LPDMA1_TRIGGER_LPDMA1_CH5_TCF 23U /*!< LPDMA1 HW Trigger signal is LPDMA1_CH5_TCF */ +#define LPDMA1_TRIGGER_LPDMA1_CH6_TCF 24U /*!< LPDMA1 HW Trigger signal is LPDMA1_CH6_TCF */ +#define LPDMA1_TRIGGER_LPDMA1_CH7_TCF 25U /*!< LPDMA1 HW Trigger signal is LPDMA1_CH7_TCF */ +#define LPDMA1_TRIGGER_TIM2_TRGO 26U /*!< LPDMA1 HW Trigger signal is TIM2_TRGO */ +#define LPDMA1_TRIGGER_ADC4_AWD1 27U /*!< LPDMA1 HW Trigger signal is ADC4_ADW1 */ +#else /* GPDMA1 triggers */ #define GPDMA1_TRIGGER_EXTI_LINE0 0U /*!< GPDMA1 HW Trigger signal is EXTI_LINE0 */ #define GPDMA1_TRIGGER_EXTI_LINE1 1U /*!< GPDMA1 HW Trigger signal is EXTI_LINE1 */ @@ -273,6 +306,10 @@ typedef struct __DMA_QListTypeDef #if defined (TIM3) #define GPDMA1_TRIGGER_TIM3_TRGO 30U /*!< GPDMA1 HW Trigger signal is TIM3_TRGO */ #endif /* TIM3 */ +#if defined (TIM4) +#define GPDMA1_TRIGGER_TIM4_TRGO 31U /*!< GPDMA1 HW Trigger signal is TIM4_TRGO */ +#endif /* TIM4 */ +#endif /* LPDMA1 */ /** * @} */ @@ -281,7 +318,12 @@ typedef struct __DMA_QListTypeDef * @brief DMAEx Node Type * @{ */ +#if defined(LPDMA1) +#define DMA_LPDMA_LINEAR_NODE (DMA_CHANNEL_TYPE_LPDMA | DMA_CHANNEL_TYPE_LINEAR_ADDR) /*!< Defines the LPDMA linear addressing node type */ +#endif /* LPDMA1 */ +#if defined(GPDMA1) #define DMA_GPDMA_LINEAR_NODE (DMA_CHANNEL_TYPE_GPDMA | DMA_CHANNEL_TYPE_LINEAR_ADDR) /*!< Defines the GPDMA linear addressing node type */ +#endif /* GPDMA1 */ /** * @} @@ -291,8 +333,13 @@ typedef struct __DMA_QListTypeDef * @brief DMAEx Linked-List Allocated Port * @{ */ +#if defined(GPDMA1) #define DMA_LINK_ALLOCATED_PORT0 0x00000000U /*!< Link allocated port 0 */ #define DMA_LINK_ALLOCATED_PORT1 DMA_CCR_LAP /*!< Link allocated port 1 */ +#else +#define DMA_LINK_ALLOCATED_PORT0 0x00000000U /*!< Kept for porting purpose */ +#define DMA_LINK_ALLOCATED_PORT1 DMA_LINK_ALLOCATED_PORT0 /*!< Kept for porting purpose */ +#endif /* GPDMA1 */ /** * @} */ @@ -415,11 +462,13 @@ HAL_StatusTypeDef HAL_DMAEx_Resume(DMA_HandleTypeDef *const hdma); * @} */ +#if defined(GPDMA1) /** @defgroup DMAEx_Exported_Functions_Group6 FIFO Status Function * @brief FIFO Status Function * @{ */ uint32_t HAL_DMAEx_GetFifoLevel(DMA_HandleTypeDef const *const hdma); +#endif /* GPDMA1 */ /** * @} @@ -463,8 +512,15 @@ typedef struct #define DMA_LINKEDLIST (0x0080U ) /* DMA channel linked-list mode */ #define DMA_CHANNEL_TYPE_LINEAR_ADDR (0x0001U) /* DMA channel linear addressing mode */ +#if defined(GPDMA1) #define DMA_CHANNEL_TYPE_2D_ADDR (0x0002U) /* DMA channel 2D addressing mode */ +#endif /* GPDMA1 */ +#if defined(LPDMA1) +#define DMA_CHANNEL_TYPE_LPDMA (0x0010U) /* LPDMA channel node */ +#endif /* LPDMA1 */ +#if defined(GPDMA1) #define DMA_CHANNEL_TYPE_GPDMA (0x0020U) /* GPDMA channel node */ +#endif /* GPDMA1 */ #define NODE_TYPE_MASK (0x00FFU) /* DMA channel node type */ #define NODE_CLLR_IDX (0x0700U) /* DMA channel node CLLR index mask */ @@ -484,12 +540,12 @@ typedef struct #define QUEUE_TYPE_STATIC (0x0000U) /* DMA channel static queue */ #define QUEUE_TYPE_DYNAMIC (0x0001U) /* DMA channel dynamic queue */ -#define NODE_CTR1_DEFAULT_OFFSET (0x0000U) /* CTR1 default offset */ -#define NODE_CTR2_DEFAULT_OFFSET (0x0001U) /* CTR2 default offset */ -#define NODE_CBR1_DEFAULT_OFFSET (0x0002U) /* CBR1 default offset */ -#define NODE_CSAR_DEFAULT_OFFSET (0x0003U) /* CSAR default offset */ -#define NODE_CDAR_DEFAULT_OFFSET (0x0004U) /* CDAR default offset */ -#define NODE_CLLR_LINEAR_DEFAULT_OFFSET (0x0005U) /* CLLR linear addressing default offset */ +#define NODE_CTR1_DEFAULT_OFFSET (0x0000UL) /* CTR1 default offset */ +#define NODE_CTR2_DEFAULT_OFFSET (0x0001UL) /* CTR2 default offset */ +#define NODE_CBR1_DEFAULT_OFFSET (0x0002UL) /* CBR1 default offset */ +#define NODE_CSAR_DEFAULT_OFFSET (0x0003UL) /* CSAR default offset */ +#define NODE_CDAR_DEFAULT_OFFSET (0x0004UL) /* CDAR default offset */ +#define NODE_CLLR_LINEAR_DEFAULT_OFFSET (0x0005UL) /* CLLR linear addressing default offset */ #define DMA_BURST_ADDR_OFFSET_MIN (-8192L) /* DMA burst minimum address offset */ #define DMA_BURST_ADDR_OFFSET_MAX (8192L) /* DMA burst maximum address offset */ @@ -504,13 +560,22 @@ typedef struct * @brief DMAEx Private Macros * @{ */ +#if defined(GPDMA1) #define IS_DMA_DATA_ALIGNMENT(ALIGNMENT) \ (((ALIGNMENT) == DMA_DATA_RIGHTALIGN_ZEROPADDED) || \ ((ALIGNMENT) == DMA_DATA_RIGHTALIGN_SIGNEXT) || \ ((ALIGNMENT) == DMA_DATA_PACK)) +#endif /* GPDMA1 */ +#if defined(LPDMA1) +#define IS_DMA_DATA_ALIGNMENT(ALIGNMENT) \ + (((ALIGNMENT) == DMA_DATA_RIGHTALIGN_ZEROPADDED) || \ + ((ALIGNMENT) == DMA_DATA_RIGHTALIGN_SIGNEXT)) +#endif /* LPDMA1 */ +#if defined(GPDMA1) #define IS_DMA_DATA_EXCHANGE(EXCHANGE) \ (((EXCHANGE) & (~(DMA_EXCHANGE_SRC_BYTE | DMA_EXCHANGE_DEST_BYTE | DMA_EXCHANGE_DEST_HALFWORD))) == 0U) +#endif /* GPDMA1 */ #define IS_DMA_REPEAT_COUNT(COUNT) \ (((COUNT) > 0U) && ((COUNT) <= (DMA_CBR1_BRC >> DMA_CBR1_BRC_Pos))) @@ -541,6 +606,11 @@ typedef struct ((POLARITY) == DMA_TRIG_POLARITY_RISING) || \ ((POLARITY) == DMA_TRIG_POLARITY_FALLING)) +#if defined (GPDMA1) +#if defined (TIM4) +#define IS_DMA_TRIGGER_SELECTION(TRIGGER) \ + ((TRIGGER) <= GPDMA1_TRIGGER_TIM4_TRGO) +#else #if defined (TIM3) #define IS_DMA_TRIGGER_SELECTION(TRIGGER) \ ((TRIGGER) <= GPDMA1_TRIGGER_TIM3_TRGO) @@ -548,9 +618,21 @@ typedef struct #define IS_DMA_TRIGGER_SELECTION(TRIGGER) \ ((TRIGGER) <= GPDMA1_TRIGGER_ADC4_AWD1) #endif /* TIM3 */ +#endif /* TIM4 */ +#endif /* GPDMA1 */ +#if defined (LPDMA1) +#define IS_DMA_TRIGGER_SELECTION(TRIGGER) \ + ((TRIGGER) <= LPDMA1_TRIGGER_ADC4_AWD1) +#endif /* LPDMA1 */ +#if defined (GPDMA1) #define IS_DMA_NODE_TYPE(TYPE) \ ((TYPE) == DMA_GPDMA_LINEAR_NODE) +#endif /* GPDMA1 */ +#if defined (LPDMA1) +#define IS_DMA_NODE_TYPE(TYPE) \ + ((TYPE) == DMA_LPDMA_LINEAR_NODE) +#endif /* LPDMA1 */ /** * @} */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_exti.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_exti.h index 4f57a58a77..c72f4c2161 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_exti.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_exti.h @@ -110,6 +110,12 @@ typedef struct #if defined(COMP2) #define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | 0x12U) #endif /* COMP2 */ +#if defined (EXTI_IMR1_IM19) +#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | 0x13U) +#endif /* EXTI_IMR1_IM19 */ +#if defined (EXTI_IMR1_IM20) +#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | 0x14U) +#endif /* EXTI_IMR1_IM20 */ /** * @} */ @@ -142,6 +148,15 @@ typedef struct #define EXTI_GPIOA 0x00000000U #define EXTI_GPIOB 0x00000001U #define EXTI_GPIOC 0x00000002U +#if defined(GPIOD) +#define EXTI_GPIOD 0x00000002U +#endif /* GPIOD */ +#if defined(GPIOE) +#define EXTI_GPIOE 0x00000004U +#endif /* GPIOE */ +#if defined(GPIOG) +#define EXTI_GPIOG 0x00000006U +#endif /* GPIOG */ #define EXTI_GPIOH 0x00000007U /** * @} @@ -177,19 +192,19 @@ typedef struct /** * @brief EXTI Line property definition */ -#define EXTI_PROPERTY_SHIFT 24U -#define EXTI_DIRECT (0x01U << EXTI_PROPERTY_SHIFT) -#define EXTI_CONFIG (0x02U << EXTI_PROPERTY_SHIFT) -#define EXTI_GPIO ((0x04U << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG) -#define EXTI_RESERVED (0x08U << EXTI_PROPERTY_SHIFT) +#define EXTI_PROPERTY_SHIFT 24U +#define EXTI_DIRECT (0x01UL << EXTI_PROPERTY_SHIFT) +#define EXTI_CONFIG (0x02UL << EXTI_PROPERTY_SHIFT) +#define EXTI_GPIO ((0x04UL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG) +#define EXTI_RESERVED (0x08UL << EXTI_PROPERTY_SHIFT) #define EXTI_PROPERTY_MASK (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO) /** * @brief EXTI Register and bit usage */ #define EXTI_REG_SHIFT 16U -#define EXTI_REG1 (0x00U << EXTI_REG_SHIFT) -#define EXTI_REG2 (0x01U << EXTI_REG_SHIFT) +#define EXTI_REG1 (0x00UL << EXTI_REG_SHIFT) +#define EXTI_REG2 (0x01UL << EXTI_REG_SHIFT) #define EXTI_REG_MASK (EXTI_REG1 | EXTI_REG2) #define EXTI_PIN_MASK 0x0000001FU @@ -206,7 +221,13 @@ typedef struct /** * @brief EXTI Line number */ +#if defined (EXTI_IMR1_IM20) +#define EXTI_LINE_NB 20U +#elif defined (EXTI_IMR1_IM19) +#define EXTI_LINE_NB 19U +#else /* EXTI_IMR1_IM20 */ #define EXTI_LINE_NB 18U +#endif /* EXTI_IMR1_IM20 */ #if defined(EXTI_SECCFGR1_SEC0) /** @@ -240,10 +261,63 @@ typedef struct #define IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__) & EXTI_CONFIG) != 0x00U) +#if defined(GPIOD) +#if defined(GPIOE) && defined(GPIOG) #define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ ((__PORT__) == EXTI_GPIOB) || \ ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOE) || \ + ((__PORT__) == EXTI_GPIOG) || \ ((__PORT__) == EXTI_GPIOH)) +#elif defined(GPIOE) +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOE) || \ + ((__PORT__) == EXTI_GPIOH)) +#elif defined(GPIOG) +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOG) || \ + ((__PORT__) == EXTI_GPIOH)) +#else /* No GPIOE and GPIOG */ +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOH)) +#endif /* defined(GPIOE) && defined(GPIOG) */ +#else /* No GPIOD */ +#if defined(GPIOE) && defined(GPIOG) +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOE) || \ + ((__PORT__) == EXTI_GPIOG) || \ + ((__PORT__) == EXTI_GPIOH)) +#elif defined(GPIOE) +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOE) || \ + ((__PORT__) == EXTI_GPIOH)) +#elif defined(GPIOG) +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOG) || \ + ((__PORT__) == EXTI_GPIOH)) +#else /* No GPIOE and GPIOG */ +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOH)) +#endif /* defined(GPIOE) && defined(GPIOG) */ +#endif /* defined(GPIOD) */ #define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16U) @@ -281,8 +355,8 @@ typedef struct * @{ */ /* Configuration functions ****************************************************/ -HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); -HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); +HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, const EXTI_ConfigTypeDef *pExtiConfig); +HAL_StatusTypeDef HAL_EXTI_GetConfigLine(const EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(const EXTI_HandleTypeDef *hexti); HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)); HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine); diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_flash.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_flash.h index d5615283bd..a6d69a7910 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_flash.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_flash.h @@ -47,6 +47,11 @@ typedef struct { uint32_t TypeErase; /*!< Mass erase or page erase. This parameter can be a value of @ref FLASH_Type_Erase */ +#if defined(FLASH_DBANK_SUPPORT) + uint32_t Banks; /*!< Select bank to erase. + This parameter must be a value of @ref FLASH_Banks + (FLASH_BANK_BOTH should be used only for mass erase) */ +#endif /* FLASH_DBANK_SUPPORT */ uint32_t Page; /*!< Initial Flash page to erase when page erase is enabled This parameter must be a value between 0 and (max number of pages - 1) */ uint32_t NbPages; /*!< Number of pages to be erased. @@ -101,6 +106,10 @@ typedef struct This parameter can be a value of @ref FLASH_OB_RDP_Key_Type */ uint32_t RDPKey1; /*!< Value of the RDP OEM key - bits[0:31] (used for OPTIONBYTE_RDPKEY) */ uint32_t RDPKey2; /*!< Value of the RDP OEM key - bits[32:63] (used for OPTIONBYTE_RDPKEY) */ +#if defined(FLASH_OEM1KEYR3_OEM1KEY) + uint32_t RDPKey3; /*!< Value of the RDP OEM key - bits[64:95] (used for @ref OPTIONBYTE_RDPKEY) */ + uint32_t RDPKey4; /*!< Value of the RDP OEM key - bits[96:127] (used for @ref OPTIONBYTE_RDPKEY) */ +#endif /* FLASH_OEM1KEYR3_OEM1KEY */ } FLASH_OBProgramInitTypeDef; /** @@ -112,6 +121,9 @@ typedef struct uint32_t ErrorCode; /*!< FLASH error code */ uint32_t ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */ uint32_t Address; /*!< Internal variable to save address selected for program in IT context */ +#if defined(FLASH_DBANK_SUPPORT) + uint32_t Bank; /*!< Internal variable to save current bank selected during erase in IT context */ +#endif /* FLASH_DBANK_SUPPORT */ uint32_t Page; /*!< Internal variable to define the current page which is erasing in IT context */ uint32_t NbPagesToErase; /*!< Internal variable to save the remaining pages to erase in IT context */ } FLASH_ProcessTypeDef; @@ -159,7 +171,12 @@ typedef struct #define FLASH_FLAG_WDW FLASH_NSSR_WDW /*!< FLASH Wait Data to Write flag */ #define FLASH_FLAG_OEM1LOCK FLASH_NSSR_OEM1LOCK /*!< FLASH OEM1 key RDP lock flag */ #define FLASH_FLAG_OEM2LOCK FLASH_NSSR_OEM2LOCK /*!< FLASH OEM2 key RDP lock flag */ +#if defined(FLASH_DBANK_SUPPORT) +#define FLASH_FLAG_PD1 FLASH_NSSR_PD1 /*!< FLASH Bank1 in power-down mode flag */ +#define FLASH_FLAG_PD2 FLASH_NNSR_PD2 /*!< FLASH Bank2 in power-down mode flag */ +#else /* FLASH_DBANK_SUPPORT */ #define FLASH_FLAG_PD FLASH_NSSR_PD /*!< FLASH in power-down lock flag */ +#endif /* FLASH_DBANK_SUPPORT */ #define FLASH_FLAG_ECCC FLASH_ECCR_ECCC /*!< FLASH ECC correction */ #define FLASH_FLAG_ECCD FLASH_ECCR_ECCD /*!< FLASH ECC detection */ @@ -213,11 +230,20 @@ typedef struct #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define FLASH_TYPEERASE_PAGES FLASH_SECCR1_PER /*!< Secure pages erase activation */ #define FLASH_TYPEERASE_PAGES_NS (FLASH_NSCR1_PER | FLASH_NON_SECURE_MASK) /*!< Non-secure pages erase activation */ +#if defined(FLASH_DBANK_SUPPORT) +#define FLASH_TYPEERASE_MASSERASE (FLASH_SECCR1_MER1 | FLASH_SECCR1_MER2) /*!< Secure flash mass erase activation */ +#define FLASH_TYPEERASE_MASSERASE_NS (FLASH_NSCR1_MER1 | FLASH_NSCR1_MER2 | FLASH_NON_SECURE_MASK) /*!< Non-secure flash mass erase activation */ +#else /* FLASH_DBANK_SUPPORT */ #define FLASH_TYPEERASE_MASSERASE FLASH_SECCR1_MER /*!< Secure flash mass erase activation */ #define FLASH_TYPEERASE_MASSERASE_NS (FLASH_NSCR1_MER | FLASH_NON_SECURE_MASK) /*!< Non-secure flash mass erase activation */ +#endif /* FLASH_DBANK_SUPPORT */ #else #define FLASH_TYPEERASE_PAGES FLASH_NSCR1_PER /*!< Pages erase activation */ +#if defined(FLASH_DBANK_SUPPORT) +#define FLASH_TYPEERASE_MASSERASE (FLASH_NSCR1_MER1 | FLASH_NSCR1_MER2) /*!< Flash mass erase activation */ +#else /* FLASH_DBANK_SUPPORT */ #define FLASH_TYPEERASE_MASSERASE FLASH_NSCR1_MER /*!< Flash mass erase activation */ +#endif /* FLASH_DBANK_SUPPORT */ #endif /* __ARM_FEATURE_CMSE */ /** * @} @@ -226,8 +252,14 @@ typedef struct /** @defgroup FLASH_Banks FLASH Banks * @{ */ +#if defined(FLASH_DBANK_SUPPORT) +#define FLASH_BANK_1 FLASH_NSCR1_MER1 /*!< Bank 1 */ +#define FLASH_BANK_2 FLASH_NSCR1_MER2 /*!< Bank 2 */ +#define FLASH_BANK_BOTH (FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank 1 and Bank 2 */ +#else /* FLASH_DBANK_SUPPORT */ #define FLASH_BANK_1 FLASH_NSCR1_MER /*!< Bank 1 */ #define FLASH_BANK_BOTH FLASH_BANK_1 /*!< Bank 1 */ +#endif /* FLASH_DBANK_SUPPORT */ /** * @} */ @@ -235,6 +267,17 @@ typedef struct /** @defgroup FLASH_TYPE_PROGRAM FLASH Program Type * @{ */ +#if defined(FLASH_DOUBLEWORD_SUPPORT) +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define FLASH_TYPEPROGRAM_DOUBLEWORD FLASH_SECCR1_PG /*!< Program a double-word (64-bit) at a specified secure address */ +#define FLASH_TYPEPROGRAM_DOUBLEWORD_NS (FLASH_NSCR1_PG | FLASH_NON_SECURE_MASK) /*!< Program a double-word (64-bit) at a specified non-secure address */ +#define FLASH_TYPEPROGRAM_BURST (FLASH_SECCR1_PG | FLASH_SECCR1_BWR) /*!< Program a burst (16xdouble-word) at a specified secure address */ +#define FLASH_TYPEPROGRAM_BURST_NS (FLASH_NSCR1_PG | FLASH_NSCR1_BWR | FLASH_NON_SECURE_MASK) /*!< Program a burst (16xdouble-word) at a specified non-secure address */ +#else +#define FLASH_TYPEPROGRAM_DOUBLEWORD FLASH_NSCR1_PG /*!< Program a double-word (64-bit) at a specified address */ +#define FLASH_TYPEPROGRAM_BURST (FLASH_NSCR1_PG | FLASH_NSCR1_BWR) /*!< Program a burst (16xdouble-word) at a specified address */ +#endif /* __ARM_FEATURE_CMSE */ +#else /* FLASH_DOUBLEWORD_SUPPORT */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define FLASH_TYPEPROGRAM_QUADWORD FLASH_SECCR1_PG /*!< Program a quad-word (128-bit) at a specified secure address */ #define FLASH_TYPEPROGRAM_QUADWORD_NS (FLASH_NSCR1_PG | FLASH_NON_SECURE_MASK) /*!< Program a quad-word (128-bit) at a specified non-secure address */ @@ -244,6 +287,7 @@ typedef struct #define FLASH_TYPEPROGRAM_QUADWORD FLASH_NSCR1_PG /*!< Program a quad-word (128-bit) at a specified address */ #define FLASH_TYPEPROGRAM_BURST (FLASH_NSCR1_PG | FLASH_NSCR1_BWR) /*!< Program a burst (8xquad-word) at a specified address */ #endif /* __ARM_FEATURE_CMSE */ +#endif /* FLASH_DOUBLEWORD_SUPPORT */ /** * @} */ @@ -267,8 +311,15 @@ typedef struct /** @defgroup FLASH_OB_WRP_Area FLASH WRP Area * @{ */ +#if defined(FLASH_DBANK_SUPPORT) +#define OB_WRPAREA_BANK1_AREAA 0x00000001U /*!< Flash Bank 1 Area A */ +#define OB_WRPAREA_BANK1_AREAB 0x00000002U /*!< Flash Bank 1 Area B */ +#define OB_WRPAREA_BANK2_AREAA 0x00000004U /*!< Flash Bank 2 Area A */ +#define OB_WRPAREA_BANK2_AREAB 0x00000008U /*!< Flash Bank 2 Area B */ +#else /* FLASH_DBANK_SUPPORT */ #define OB_WRPAREA_BANK1_AREAA 0x00000001U /*!< Flash Area A */ #define OB_WRPAREA_BANK1_AREAB 0x00000002U /*!< Flash Area B */ +#endif /* FLASH_DBANK_SUPPORT */ /** * @} */ @@ -305,27 +356,84 @@ typedef struct #define OB_USER_IWDG_SW FLASH_OPTR_IWDG_SW /*!< Independent watchdog selection */ #define OB_USER_IWDG_STOP FLASH_OPTR_IWDG_STOP /*!< Independent watchdog counter freeze in stop mode */ #define OB_USER_IWDG_STDBY FLASH_OPTR_IWDG_STDBY /*!< Independent watchdog counter freeze in standby mode */ +#if defined(FLASH_OPTR_WWDG_SW) #define OB_USER_WWDG_SW FLASH_OPTR_WWDG_SW /*!< Window watchdog selection */ +#endif /* FLASH_OPTR_WWDG_SW */ +#if defined(FLASH_DBANK_SUPPORT) +#define OB_USER_SWAP_BANK FLASH_OPTR_SWAP_BANK /*!< Swap banks */ +#define OB_USER_DUALBANK FLASH_OPTR_DUAL_BANK /*!< Dual-Bank */ +#endif /* FLASH_DBANK_SUPPORT */ #define OB_USER_SRAM2_PE FLASH_OPTR_SRAM2_PE /*!< SRAM2 parity error enable */ #define OB_USER_SRAM2_RST FLASH_OPTR_SRAM2_RST /*!< SRAM2 Erase when system reset */ #define OB_USER_nSWBOOT0 FLASH_OPTR_nSWBOOT0 /*!< Software BOOT0 */ #define OB_USER_nBOOT0 FLASH_OPTR_nBOOT0 /*!< nBOOT0 option bit */ +#if defined(FLASH_OPTR_IO_VDD_HSLV) +#define OB_USER_IO_VDD_HSLV FLASH_OPTR_IO_VDD_HSLV /*!< High speed IO at low VDD voltage configuration bit */ +#endif /* FLASH_OPTR_IO_VDD_HSLV */ +#if defined(FLASH_OPTR_IO_VDDIO2_HSLV) +#define OB_USER_IO_VDDIO2_HSLV FLASH_OPTR_IO_VDDIO2_HSLV /*!< High speed IO at low VDDIO2 voltage configuration bit */ +#endif /* FLASH_OPTR_IO_VDDIO2_HSLV */ #if defined(FLASH_OPTR_TZEN) #define OB_USER_TZEN FLASH_OPTR_TZEN /*!< Global TrustZone enable */ #endif /* FLASH_OPTR_TZEN */ +#if defined(FLASH_DBANK_SUPPORT) +#if defined(FLASH_OPTR_IO_VDD_HSLV) && defined(FLASH_OPTR_IO_VDDIO2_HSLV) +#define OB_USER_ALL (OB_USER_BOR_LEV | OB_USER_nRST_STOP | OB_USER_nRST_STDBY | \ + OB_USER_SRAM1_RST | OB_USER_IWDG_SW | OB_USER_IWDG_STOP | \ + OB_USER_IWDG_STDBY | OB_USER_WWDG_SW | OB_USER_SWAP_BANK | \ + OB_USER_DUALBANK | OB_USER_SRAM2_PE | OB_USER_SRAM2_RST | \ + OB_USER_nSWBOOT0 | OB_USER_nBOOT0 | OB_USER_IO_VDD_HSLV | \ + OB_USER_IO_VDDIO2_HSLV | OB_USER_TZEN) /*!< All User option bits */ +#elif defined(FLASH_OPTR_IO_VDD_HSLV) +#define OB_USER_ALL (OB_USER_BOR_LEV | OB_USER_nRST_STOP | OB_USER_nRST_STDBY | \ + OB_USER_SRAM1_RST | OB_USER_IWDG_SW | OB_USER_IWDG_STOP | \ + OB_USER_IWDG_STDBY | OB_USER_WWDG_SW | OB_USER_SWAP_BANK | \ + OB_USER_DUALBANK | OB_USER_SRAM2_PE | OB_USER_SRAM2_RST | \ + OB_USER_nSWBOOT0 | OB_USER_nBOOT0 | OB_USER_IO_VDD_HSLV | \ + OB_USER_TZEN) /*!< All User option bits */ +#elif defined(FLASH_OPTR_IO_VDDIO2_HSLV) +#define OB_USER_ALL (OB_USER_BOR_LEV | OB_USER_nRST_STOP | OB_USER_nRST_STDBY | \ + OB_USER_SRAM1_RST | OB_USER_IWDG_SW | OB_USER_IWDG_STOP | \ + OB_USER_IWDG_STDBY | OB_USER_WWDG_SW | OB_USER_SWAP_BANK | \ + OB_USER_DUALBANK | OB_USER_SRAM2_PE | OB_USER_SRAM2_RST | \ + OB_USER_nSWBOOT0 | OB_USER_nBOOT0 | OB_USER_IO_VDDIO2_HSLV | \ + OB_USER_TZEN) /*!< All User option bits */ +#else +#define OB_USER_ALL (OB_USER_BOR_LEV | OB_USER_nRST_STOP | OB_USER_nRST_STDBY | \ + OB_USER_SRAM1_RST | OB_USER_IWDG_SW | OB_USER_IWDG_STOP | \ + OB_USER_IWDG_STDBY | OB_USER_WWDG_SW | OB_USER_SWAP_BANK | \ + OB_USER_DUALBANK | OB_USER_SRAM2_PE | OB_USER_SRAM2_RST | \ + OB_USER_nSWBOOT0 | OB_USER_nBOOT0 | OB_USER_TZEN) /*!< All User option bits */ +#endif /* FLASH_OPTR_IO_VDD_HSLV && FLASH_OPTR_IO_VDDIO2_HSLV */ +#else /* FLASH_DBANK_SUPPORT */ #if defined(FLASH_OPTR_TZEN) +#if defined(FLASH_OPTR_WWDG_SW) #define OB_USER_ALL (OB_USER_BOR_LEV | OB_USER_nRST_STOP | OB_USER_nRST_STDBY | \ OB_USER_SRAM1_RST | OB_USER_IWDG_SW | OB_USER_IWDG_STOP | \ OB_USER_IWDG_STDBY | OB_USER_WWDG_SW | OB_USER_SRAM2_PE | \ OB_USER_SRAM2_RST | OB_USER_nSWBOOT0 | OB_USER_nBOOT0 | \ OB_USER_TZEN) /*!< All User option bits */ +#else /* FLASH_OPTR_WWDG_SW */ +#define OB_USER_ALL (OB_USER_BOR_LEV | OB_USER_nRST_STOP | OB_USER_nRST_STDBY | \ + OB_USER_SRAM1_RST | OB_USER_IWDG_SW | OB_USER_IWDG_STOP | \ + OB_USER_IWDG_STDBY | OB_USER_SRAM2_PE | OB_USER_SRAM2_RST | \ + OB_USER_nSWBOOT0 | OB_USER_nBOOT0 | OB_USER_TZEN) /*!< All User option bits */ +#endif /* FLASH_OPTR_WWDG_SW */ #else +#if defined(FLASH_OPTR_WWDG_SW) #define OB_USER_ALL (OB_USER_BOR_LEV | OB_USER_nRST_STOP | OB_USER_nRST_STDBY | \ OB_USER_SRAM1_RST | OB_USER_IWDG_SW | OB_USER_IWDG_STOP | \ OB_USER_IWDG_STDBY | OB_USER_WWDG_SW | OB_USER_SRAM2_PE | \ OB_USER_SRAM2_RST | OB_USER_nSWBOOT0 | OB_USER_nBOOT0) /*!< All User option bits */ +#else /* FLASH_OPTR_WWDG_SW */ +#define OB_USER_ALL (OB_USER_BOR_LEV | OB_USER_nRST_STOP | OB_USER_nRST_STDBY | \ + OB_USER_SRAM1_RST | OB_USER_IWDG_SW | OB_USER_IWDG_STOP | \ + OB_USER_IWDG_STDBY | OB_USER_SRAM2_PE | OB_USER_SRAM2_RST | \ + OB_USER_nSWBOOT0 | OB_USER_nBOOT0) /*!< All User option bits */ +#endif /* FLASH_OPTR_WWDG_SW */ #endif /* FLASH_OPTR_TZEN */ +#endif /* FLASH_DBANK_SUPPORT */ /** * @} */ @@ -396,15 +504,36 @@ typedef struct * @} */ +#if defined(FLASH_OPTR_WWDG_SW) /** @defgroup FLASH_OB_USER_WWDG_SW FLASH Option Bytes User WWDG Type * @{ */ #define OB_WWDG_HW 0x00000000U /*!< Hardware window watchdog */ #define OB_WWDG_SW FLASH_OPTR_WWDG_SW /*!< Software window watchdog */ +/** + * @} + */ +#endif /* FLASH_OPTR_WWDG_SW */ + +#if defined(FLASH_DBANK_SUPPORT) +/** @defgroup FLASH_OB_USER_SWAP_BANK FLASH Option Bytes User Swap banks + * @{ + */ +#define OB_SWAP_BANK_DISABLE 0x00000000U /*!< Bank 1 and Bank 2 addresses not swapped */ +#define OB_SWAP_BANK_ENABLE FLASH_OPTR_SWAP_BANK /*!< Bank 1 and Bank 2 addresses swapped */ /** * @} */ +/** @defgroup FLASH_OB_USER_DUALBANK FLASH Option Bytes User Dual-bank Type + * @{ + */ +#define OB_DUALBANK_SINGLE 0x00000000U /*!< Single-bank Flash with contiguous addresses in Bank 1 */ +#define OB_DUALBANK_DUAL FLASH_OPTR_DUAL_BANK /*!< Dual-bank Flash with contiguous addresses */ +/** + * @} + */ +#endif /* FLASH_DBANK_SUPPORT */ /** @defgroup FLASH_OB_USER_SRAM2_PAR FLASH Option Bytes User SRAM2 Parity error enable * @{ @@ -442,7 +571,27 @@ typedef struct * @} */ +#if defined(FLASH_OPTR_IO_VDD_HSLV) +/** @defgroup FLASH_OB_USER_IO_VDD_HSLV FLASH Option Bytes User High speed IO at low voltage configuration bit + * @{ + */ +#define OB_IO_VDD_HSLV_DISABLE 0x00000000U /*!< High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.5 V) */ +#define OB_IO_VDD_HSLV_ENABLE FLASH_OPTR_IO_VDD_HSLV /*!< High-speed IO at low VDD voltage feature enabled (VDD remains below 2.5 V) */ +/** + * @} + */ +#endif /* FLASH_OPTR_IO_VDD_HSLV */ +#if defined(FLASH_OPTR_IO_VDDIO2_HSLV) +/** @defgroup FLASH_OB_USER_IO_VDDIO2_HSLV FLASH Option Bytes User High speed IO at low voltage configuration bit for Vddio2 + * @{ + */ +#define OB_IO_VDDIO2_HSLV_DISABLE 0x00000000U /*!< High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.5 V) */ +#define OB_IO_VDDIO2_HSLV_ENABLE FLASH_OPTR_IO_VDDIO2_HSLV /*!< High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.5 V) */ +/** + * @} + */ +#endif /* FLASH_OPTR_IO_VDDIO2_HSLV */ #if defined(FLASH_OPTR_TZEN) /** @defgroup FLASH_OB_USER_TZEN FLASH Option Bytes User Global TrustZone @@ -469,6 +618,9 @@ typedef struct * @{ */ #define OB_WMSEC_AREA1 FLASH_BANK_1 /*!< Watermarked-based security area for bank 1 */ +#if defined(FLASH_DBANK_SUPPORT) +#define OB_WMSEC_AREA2 FLASH_BANK_2 /*!< Watermarked-based security area for bank 2 */ +#endif /* FLASH_DBANK_SUPPORT */ #define OB_WMSEC_SECURE_AREA_CONFIG 0x00000010U /*!< Configure Watermarked-based security area */ #define OB_WMSEC_HDP_AREA_CONFIG 0x00000020U /*!< Configure Watermarked-based secure hide area */ @@ -521,9 +673,19 @@ typedef struct #define FLASH_KEY2 0xCDEF89ABU /*!< Flash key2: used with FLASH_KEY1 to unlock the FLASH registers access */ +#if defined(FLASH_DBANK_SUPPORT) +#define FLASH_PDKEY1_1 0x04152637U /*!< Flash Bank 1 power down key1 */ +#define FLASH_PDKEY1_2 0xFAFBFCFDU /*!< Flash Bank 1 power down key2: used with FLASH_PDKEY1_1 + to unlock the PDREQ1 bit in FLASH_ACR */ + +#define FLASH_PDKEY2_1 0x40516273U /*!< Flash Bank 2 power down key1 */ +#define FLASH_PDKEY2_2 0xAFBFCFDFU /*!< Flash Bank 2 power down key2: used with FLASH_PDKEY2_1 + to unlock the PDREQ2 bit in FLASH_ACR */ +#else /* FLASH_DBANK_SUPPORT */ #define FLASH_PDKEY1 0x04152637U /*!< Flash power down key1 */ #define FLASH_PDKEY2 0xFAFBFCFDU /*!< Flash power down key2: used with FLASH_PDKEY1 to unlock the PDREQ bit in FLASH_ACR */ +#endif /* FLASH_DBANK_SUPPORT */ #define FLASH_OPTKEY1 0x08192A3BU /*!< Flash option byte key1 */ #define FLASH_OPTKEY2 0x4C5D6E7FU /*!< Flash option byte key2: used with FLASH_OPTKEY1 @@ -914,10 +1076,22 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); /** @defgroup FLASH_Private_Constants FLASH Private Constants * @{ */ +#if defined(FLASH_DBANK_SUPPORT) +#define FLASH_BANK_SIZE (FLASH_SIZE / 2) +#else /* FLASH_DBANK_SUPPORT */ #define FLASH_BANK_SIZE FLASH_SIZE +#endif /* FLASH_DBANK_SUPPORT */ +#if defined(FLASH_DOUBLEWORD_SUPPORT) +#define FLASH_PAGE_SIZE 0x1000U /* 4 KB */ +#else /* FLASH_DOUBLEWORD_SUPPORT */ #define FLASH_PAGE_SIZE 0x2000U /* 8 KB */ +#endif /* FLASH_DOUBLEWORD_SUPPORT */ +#if defined(FLASH_DBANK_SUPPORT) +#define FLASH_PAGE_NB (FLASH_BANK_SIZE / FLASH_PAGE_SIZE) +#else /* FLASH_DBANK_SUPPORT */ #define FLASH_PAGE_NB (FLASH_SIZE / FLASH_PAGE_SIZE) +#endif /* FLASH_DBANK_SUPPORT */ #define FLASH_TIMEOUT_VALUE 1000U /* 1 s */ @@ -940,10 +1114,30 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); ((VALUE) == FLASH_TYPEERASE_MASSERASE)) #endif /* __ARM_FEATURE_CMSE */ +#if defined(FLASH_DBANK_SUPPORT) +#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \ + ((BANK) == FLASH_BANK_2) || \ + ((BANK) == FLASH_BANK_BOTH)) + +#define IS_FLASH_BANK_EXCLUSIVE(BANK) (((BANK) == FLASH_BANK_1) || \ + ((BANK) == FLASH_BANK_2)) +#else /* FLASH_DBANK_SUPPORT */ #define IS_FLASH_BANK(BANK) ((BANK) == FLASH_BANK_1) #define IS_FLASH_BANK_EXCLUSIVE(BANK) ((BANK) == FLASH_BANK_1) +#endif /* FLASH_DBANK_SUPPORT */ +#if defined(FLASH_DOUBLEWORD_SUPPORT) +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD) || \ + ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD_NS) || \ + ((VALUE) == FLASH_TYPEPROGRAM_BURST) || \ + ((VALUE) == FLASH_TYPEPROGRAM_BURST_NS)) +#else +#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD) || \ + ((VALUE) == FLASH_TYPEPROGRAM_BURST)) +#endif /* __ARM_FEATURE_CMSE */ +#else /* FLASH_DOUBLEWORD_SUPPORT */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_QUADWORD) || \ ((VALUE) == FLASH_TYPEPROGRAM_QUADWORD_NS) || \ @@ -953,6 +1147,7 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); #define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_QUADWORD) || \ ((VALUE) == FLASH_TYPEPROGRAM_BURST)) #endif /* __ARM_FEATURE_CMSE */ +#endif /* FLASH_DOUBLEWORD_SUPPORT */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) ((((ADDRESS) >= FLASH_BASE) && ((ADDRESS) < (FLASH_BASE+FLASH_SIZE))) || \ @@ -976,7 +1171,12 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); OPTIONBYTE_BOOTADDR | OPTIONBYTE_RDPKEY))) #endif /* __ARM_FEATURE_CMSE */ +#if defined(FLASH_DBANK_SUPPORT) +#define IS_OB_WRPAREA(VALUE) (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB) || \ + ((VALUE) == OB_WRPAREA_BANK2_AREAA) || ((VALUE) == OB_WRPAREA_BANK2_AREAB)) +#else /* FLASH_DBANK_SUPPORT */ #define IS_OB_WRPAREA(VALUE) (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB)) +#endif /* FLASH_DBANK_SUPPORT */ #define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\ ((LEVEL) == OB_RDP_LEVEL_0_5) ||\ @@ -1003,6 +1203,11 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); #define IS_OB_USER_WWDG(VALUE) (((VALUE) == OB_WWDG_HW) || ((VALUE) == OB_WWDG_SW)) +#if defined(FLASH_DBANK_SUPPORT) +#define IS_OB_USER_SWAP_BANK(VALUE) (((VALUE) == OB_SWAP_BANK_DISABLE) || ((VALUE) == OB_SWAP_BANK_ENABLE)) + +#define IS_OB_USER_DUALBANK(VALUE) (((VALUE) == OB_DUALBANK_SINGLE) || ((VALUE) == OB_DUALBANK_DUAL)) +#endif /* FLASH_DBANK_SUPPORT */ #define IS_OB_USER_SRAM2_PARITY(VALUE) (((VALUE) == OB_SRAM2_PARITY_ENABLE) || ((VALUE) == OB_SRAM2_PARITY_DISABLE)) @@ -1012,16 +1217,29 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); #define IS_OB_USER_BOOT0(VALUE) (((VALUE) == OB_nBOOT0_RESET) || ((VALUE) == OB_nBOOT0_SET)) +#if defined(FLASH_OPTR_IO_VDD_HSLV) +#define IS_OB_USER_IO_VDD_HSLV(VALUE) (((VALUE) == OB_IO_VDD_HSLV_DISABLE) || ((VALUE) == OB_IO_VDD_HSLV_ENABLE)) +#endif /* FLASH_OPTR_IO_VDD_HSLV */ +#if defined(FLASH_OPTR_IO_VDDIO2_HSLV) +#define IS_OB_USER_IO_VDDIO2_HSLV(VALUE) (((VALUE) == OB_IO_VDDIO2_HSLV_DISABLE) || ((VALUE) == OB_IO_VDDIO2_HSLV_ENABLE)) +#endif /* FLASH_OPTR_IO_VDDIO2_HSLV */ #define IS_OB_USER_TZEN(VALUE) (((VALUE) == OB_TZEN_DISABLE) || ((VALUE) == OB_TZEN_ENABLE)) #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define IS_OB_BOOT_LOCK(VALUE) (((VALUE) == OB_BOOT_LOCK_DISABLE) || ((VALUE) == OB_BOOT_LOCK_ENABLE)) +#if defined(FLASH_DBANK_SUPPORT) +#define IS_OB_WMSEC_CONFIG(CFG) ((((CFG) & 0x81B4U) != 0U) && (((CFG) & 0x8004U) != 0U) && (((CFG) & 0xFFFF7E4BU) == 0U)) + +#define IS_OB_WMSEC_AREA_EXCLUSIVE(WMSEC) (((((WMSEC) & OB_WMSEC_AREA1) != 0U) && (((WMSEC) & OB_WMSEC_AREA2) == 0U)) || \ + ((((WMSEC) & OB_WMSEC_AREA2) != 0U) && (((WMSEC) & OB_WMSEC_AREA1) == 0U))) +#else /* FLASH_DBANK_SUPPORT */ #define IS_OB_WMSEC_CONFIG(CFG) ((((CFG) & 0x1B4U) != 0U) && (((CFG) & 0x4U) != 0U) && (((CFG) & 0xFFFFFE4BU) == 0U)) #define IS_OB_WMSEC_AREA_EXCLUSIVE(WMSEC) (((WMSEC) & OB_WMSEC_AREA1) != 0U) +#endif /* FLASH_DBANK_SUPPORT */ #endif /* __ARM_FEATURE_CMSE */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_flash_ex.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_flash_ex.h index 62afed2492..149fd2c8ed 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_flash_ex.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_flash_ex.h @@ -57,6 +57,10 @@ extern "C" { */ typedef struct { +#if defined(FLASH_DBANK_SUPPORT) + uint32_t Bank; /*!< Selection of the associated bank of Block-based Area. + This parameter must be a value of @ref FLASH_Banks */ +#endif /* FLASH_DBANK_SUPPORT */ uint32_t BBAttributesType; /*!< Block-Based Attributes type. This parameter must be a value of @ref FLASHEx_BB_Attributes */ uint32_t BBAttributes_array[FLASH_BLOCKBASED_NB_REG]; /*!< Each bit specifies the block-based attribute configuration of a page: @@ -65,6 +69,21 @@ typedef struct } FLASH_BBAttributesTypeDef; #endif /* FLASH_SECBBR1_SECBB0 || FLASH_PRIVBBR1_PRIVBB0 */ +#if defined(FLASH_SECHDPEXTR_HDP_PEXT) +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief FLASHEx Extended secure hide area structure definition + */ +typedef struct +{ + uint32_t Bank; /*!< Selection of the associated bank of extended secure hide area. + This parameter must be a value of @ref FLASH_Banks */ + uint32_t NbPages; /*!< Number of pages of the extended secure hide area. + This parameter must be a value between 0 and (WM end page - WM start page) if no HDP, + or between 0 and (WM end page - HDP end page) if HDP enabled */ +} FLASH_HDPExtensionTypeDef; +#endif /* __ARM_FEATURE_CMSE */ +#endif /* FLASH_SECHDPEXTR_HDP_PEXT */ /** * @brief FLASHEx Operation structure definition @@ -150,20 +169,41 @@ typedef struct * @{ */ #define FLASH_OPERATION_TYPE_NONE 00000000U /*!< No Flash operation */ +#if defined(FLASH_DOUBLEWORD_SUPPORT) +#define FLASH_OPERATION_TYPE_DOUBLEWORD FLASH_OPSR_CODE_OP_0 /*!< Single write operation */ +#else /* FLASH_DOUBLEWORD_SUPPORT */ #define FLASH_OPERATION_TYPE_QUADWORD FLASH_OPSR_CODE_OP_0 /*!< Single write operation */ +#endif /* FLASH_DOUBLEWORD_SUPPORT */ #define FLASH_OPERATION_TYPE_BURST FLASH_OPSR_CODE_OP_1 /*!< Burst write operation */ #define FLASH_OPERATION_TYPE_PAGEERASE (FLASH_OPSR_CODE_OP_1 | FLASH_OPSR_CODE_OP_0) /*!< Page erase operation */ +#if defined(FLASH_DBANK_SUPPORT) +#define FLASH_OPERATION_TYPE_BANKERASE FLASH_OPSR_CODE_OP_2 /*!< Bank erase operation */ +#endif /* FLASH_DBANK_SUPPORT */ #define FLASH_OPERATION_TYPE_MASSERASE (FLASH_OPSR_CODE_OP_2 | FLASH_OPSR_CODE_OP_0) /*!< Mass erase operation */ #define FLASH_OPERATION_TYPE_OPTIONCHANGE (FLASH_OPSR_CODE_OP_2 | FLASH_OPSR_CODE_OP_1) /*!< Option change operation */ /** * @} */ +#if defined(FLASH_SECHDPEXTR_HDP_PEXT) +/** @defgroup FLASH_ExtHDP_Protection FLASH Extended HDP Area protection type + * @{ + */ +#define FLASH_EXTHDP_NO_PROTECTION 0xA3U /*!< Access to bits configuration and area allowed */ +#define FLASH_EXTHDP_ONLY_ACCESS_PROTECTED 0x5CU /*!< Access to area denied and bits configuration allowed */ +#define FLASH_EXTHDP_ALL_PROTECTED 0x00U /*!< Access to bits configuration and area denied */ +/** + * @} + */ +#endif /* FLASH_SECHDPEXTR_HDP_PEXT */ /** @defgroup FLASHEx_ECC_Area FLASH ECC Area * @{ */ #define FLASH_ECC_AREA_USER_BANK1 0x00000000U /*!< FLASH bank 1 area */ +#if defined(FLASH_DBANK_SUPPORT) +#define FLASH_ECC_AREA_USER_BANK2 FLASH_ECCR_BK_ECC /*!< FLASH bank 2 area */ +#endif /* FLASH_DBANK_SUPPORT */ #define FLASH_ECC_AREA_SYSTEM FLASH_ECCR_SYSF_ECC /*!< System FLASH area */ /** * @} @@ -180,6 +220,31 @@ typedef struct /** @defgroup FLASHEx_Suspend_Request FLASH Suspend Request * @{ */ +#if defined(FLASH_DBANK_SUPPORT) +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define FLASH_SUSPEND_PROGRAM (FLASH_SECCR2_PS1 | FLASH_SECCR2_PS2) /*!< Suspend all program requests */ +#define FLASH_SUSPEND_BANK1_PROGRAM FLASH_SECCR2_PS1 /*!< Suspend all program requests in bank 1 */ +#define FLASH_SUSPEND_BANK2_PROGRAM FLASH_SECCR2_PS2 /*!< Suspend all program requests in bank 2 */ +#define FLASH_SUSPEND_ERASE (FLASH_SECCR2_ES1 | FLASH_SECCR2_ES2) /*!< Suspend all erase requests */ +#define FLASH_SUSPEND_BANK1_ERASE FLASH_SECCR2_ES1 /*!< Suspend all erase requests in bank 1 */ +#define FLASH_SUSPEND_BANK2_ERASE FLASH_SECCR2_ES2 /*!< Suspend all erase requests in bank 2 */ +#define FLASH_SUSPEND_PROGRAM_ERASE (FLASH_SECCR2_PS1 | FLASH_SECCR2_ES1 | \ + FLASH_SECCR2_PS2 | FLASH_SECCR2_ES2) /*!< Suspend all requests (program and erase) */ +#define FLASH_SUSPEND_BANK1_PROGRAM_ERASE (FLASH_SECCR2_PS1 | FLASH_SECCR2_ES1) /*!< Suspend all requests in bank 1 (program and erase) */ +#define FLASH_SUSPEND_BANK2_PROGRAM_ERASE (FLASH_SECCR2_PS2 | FLASH_SECCR2_ES2) /*!< Suspend all requests in bank 2 (program and erase) */ +#else +#define FLASH_SUSPEND_PROGRAM (FLASH_NSCR2_PS1 | FLASH_NSCR2_PS2) /*!< Suspend all program requests */ +#define FLASH_SUSPEND_BANK1_PROGRAM FLASH_NSCR2_PS1 /*!< Suspend all program requests in bank 1 */ +#define FLASH_SUSPEND_BANK2_PROGRAM FLASH_NSCR2_PS2 /*!< Suspend all program requests in bank 2 */ +#define FLASH_SUSPEND_ERASE (FLASH_NSCR2_ES1 | FLASH_NSCR2_ES2) /*!< Suspend all erase requests */ +#define FLASH_SUSPEND_BANK1_ERASE FLASH_NSCR2_ES1 /*!< Suspend all erase requests in bank 1 */ +#define FLASH_SUSPEND_BANK2_ERASE FLASH_NSCR2_ES2 /*!< Suspend all erase requests in bank 2 */ +#define FLASH_SUSPEND_PROGRAM_ERASE (FLASH_NSCR2_PS1 | FLASH_NSCR2_ES1 | \ + FLASH_NSCR2_PS2 | FLASH_NSCR2_ES2) /*!< Suspend all requests (program and erase) */ +#define FLASH_SUSPEND_BANK1_PROGRAM_ERASE (FLASH_NSCR2_PS1 | FLASH_NSCR2_ES1) /*!< Suspend all requests in bank 1 (program and erase) */ +#define FLASH_SUSPEND_BANK2_PROGRAM_ERASE (FLASH_NSCR2_PS2 | FLASH_NSCR2_ES2) /*!< Suspend all requests in bank 2 (program and erase) */ +#endif /* __ARM_FEATURE_CMSE */ +#else /* FLASH_DBANK_SUPPORT */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define FLASH_SUSPEND_PROGRAM FLASH_SECCR2_PS /*!< Suspend all program requests */ #define FLASH_SUSPEND_ERASE FLASH_SECCR2_ES /*!< Suspend all erase requests */ @@ -189,6 +254,7 @@ typedef struct #define FLASH_SUSPEND_ERASE FLASH_NSCR2_ES /*!< Suspend all erase requests */ #define FLASH_SUSPEND_PROGRAM_ERASE (FLASH_NSCR2_PS | FLASH_NSCR2_ES) /*!< Suspend all requests (program and erase) */ #endif /* __ARM_FEATURE_CMSE */ +#endif /* FLASH_DBANK_SUPPORT */ /** * @} */ @@ -196,6 +262,31 @@ typedef struct /** @defgroup FLASHEx_Allow_Request FLASH Allow Request * @{ */ +#if defined(FLASH_DBANK_SUPPORT) +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define FLASH_ALLOW_PROGRAM (FLASH_SECCR2_PS1 | FLASH_SECCR2_PS2) /*!< Suspend all program requests */ +#define FLASH_ALLOW_BANK1_PROGRAM FLASH_SECCR2_PS1 /*!< Suspend all program requests in bank 1 */ +#define FLASH_ALLOW_BANK2_PROGRAM FLASH_SECCR2_PS2 /*!< Suspend all program requests in bank 2 */ +#define FLASH_ALLOW_ERASE (FLASH_SECCR2_ES1 | FLASH_SECCR2_ES2) /*!< Suspend all erase requests */ +#define FLASH_ALLOW_BANK1_ERASE FLASH_SECCR2_ES1 /*!< Suspend all erase requests in bank 1 */ +#define FLASH_ALLOW_BANK2_ERASE FLASH_SECCR2_ES2 /*!< Suspend all erase requests in bank 2 */ +#define FLASH_ALLOW_PROGRAM_ERASE (FLASH_SECCR2_PS1 | FLASH_SECCR2_ES1 | \ + FLASH_SECCR2_PS2 | FLASH_SECCR2_ES2) /*!< Suspend all requests (program and erase) */ +#define FLASH_ALLOW_BANK1_PROGRAM_ERASE (FLASH_SECCR2_PS1 | FLASH_SECCR2_ES1) /*!< Suspend all requests in bank 1 (program and erase) */ +#define FLASH_ALLOW_BANK2_PROGRAM_ERASE (FLASH_SECCR2_PS2 | FLASH_SECCR2_ES2) /*!< Suspend all requests in bank 2 (program and erase) */ +#else +#define FLASH_ALLOW_PROGRAM (FLASH_NSCR2_PS1 | FLASH_NSCR2_PS2) /*!< Suspend all program requests */ +#define FLASH_ALLOW_BANK1_PROGRAM FLASH_NSCR2_PS1 /*!< Suspend all program requests in bank 1 */ +#define FLASH_ALLOW_BANK2_PROGRAM FLASH_NSCR2_PS2 /*!< Suspend all program requests in bank 2 */ +#define FLASH_ALLOW_ERASE (FLASH_NSCR2_ES1 | FLASH_NSCR2_ES2) /*!< Suspend all erase requests */ +#define FLASH_ALLOW_BANK1_ERASE FLASH_NSCR2_ES1 /*!< Suspend all erase requests in bank 1 */ +#define FLASH_ALLOW_BANK2_ERASE FLASH_NSCR2_ES2 /*!< Suspend all erase requests in bank 2 */ +#define FLASH_ALLOW_PROGRAM_ERASE (FLASH_NSCR2_PS1 | FLASH_NSCR2_ES1 | \ + FLASH_NSCR2_PS2 | FLASH_NSCR2_ES2) /*!< Suspend all requests (program and erase) */ +#define FLASH_ALLOW_BANK1_PROGRAM_ERASE (FLASH_NSCR2_PS1 | FLASH_NSCR2_ES1) /*!< Suspend all requests in bank 1 (program and erase) */ +#define FLASH_ALLOW_BANK2_PROGRAM_ERASE (FLASH_NSCR2_PS2 | FLASH_NSCR2_ES2) /*!< Suspend all requests in bank 2 (program and erase) */ +#endif /* __ARM_FEATURE_CMSE */ +#else /* FLASH_DBANK_SUPPORT */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define FLASH_ALLOW_PROGRAM FLASH_SECCR2_PS /*!< Allow all program requests */ #define FLASH_ALLOW_ERASE FLASH_SECCR2_ES /*!< Allow all erase requests */ @@ -205,6 +296,7 @@ typedef struct #define FLASH_ALLOW_ERASE FLASH_NSCR2_ES /*!< Allow all erase requests */ #define FLASH_ALLOW_PROGRAM_ERASE (FLASH_NSCR2_PS | FLASH_NSCR2_ES) /*!< Allow all requests (program and erase) */ #endif /* __ARM_FEATURE_CMSE */ +#endif /* FLASH_DBANK_SUPPORT */ /** * @} */ @@ -224,17 +316,25 @@ typedef struct /** @addtogroup FLASHEx_Exported_Functions_Group1 * @{ */ -HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError); +HAL_StatusTypeDef HAL_FLASHEx_Erase(const FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError); HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit); HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); #if defined(FLASH_SECBBR1_SECBB0) || defined(FLASH_PRIVBBR1_PRIVBB0) || defined(FLASH_SECBB1R1_SECBB0) || defined(FLASH_PRIVBB1R1_PRIVBB0) -HAL_StatusTypeDef HAL_FLASHEx_ConfigBBAttributes(FLASH_BBAttributesTypeDef *pBBAttributes); +HAL_StatusTypeDef HAL_FLASHEx_ConfigBBAttributes(const FLASH_BBAttributesTypeDef *pBBAttributes); void HAL_FLASHEx_GetConfigBBAttributes(FLASH_BBAttributesTypeDef *pBBAttributes); #endif /* FLASH_SECBBR1_SECBB0 || FLASH_PRIVBBR1_PRIVBB0 */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) void HAL_FLASHEx_EnableSecHideProtection(uint32_t Banks); +#if defined(FLASH_SECHDPEXTR_HDP_PEXT) +HAL_StatusTypeDef HAL_FLASHEx_ConfigHDPExtension(FLASH_HDPExtensionTypeDef *pHDPExtension); +void HAL_FLASHEx_GetConfigHDPExtension(FLASH_HDPExtensionTypeDef *pHDPExtension); +void HAL_FLASHEx_EnableHDPExtensionProtection(uint32_t Banks, uint32_t ProtectionType); +#endif /* FLASH_SECHDPEXTR_HDP_PEXT */ #endif /* __ARM_FEATURE_CMSE */ +#if defined(FLASH_OEMKEYSR_OEM1KEYCRC) +void HAL_FLASHEx_GetRDPKeyCRC(uint32_t RDPKeyType, uint32_t *CRCKeyValue); +#endif /* FLASH_OEMKEYSR_OEM1KEYCRC */ /** * @} */ @@ -253,7 +353,11 @@ uint32_t HAL_FLASHEx_GetPrivMode(void); HAL_StatusTypeDef HAL_FLASHEx_ConfigSecInversion(uint32_t SecInvState); uint32_t HAL_FLASHEx_GetSecInversion(void); #endif /* __ARM_FEATURE_CMSE */ +#if defined(FLASH_DBANK_SUPPORT) +HAL_StatusTypeDef HAL_FLASHEx_EnablePowerDown(uint32_t Banks); +#else /* FLASH_DBANK_SUPPORT */ HAL_StatusTypeDef HAL_FLASHEx_EnablePowerDown(void); +#endif /* FLASH_DBANK_SUPPORT */ HAL_StatusTypeDef HAL_FLASHEx_ConfigLowPowerRead(uint32_t ConfigLPM); uint32_t HAL_FLASHEx_GetLowPowerRead(void); void HAL_FLASHEx_GetOperation(FLASH_OperationTypeDef *pFlashOperation); @@ -282,7 +386,11 @@ __weak void HAL_FLASHEx_EccCorrectionCallback(void); /** @addtogroup FLASHEx_Private_Functions FLASHEx Private Functions * @{ */ +#if defined(FLASH_DBANK_SUPPORT) +void FLASH_PageErase(uint32_t Page, uint32_t Banks); +#else /* FLASH_DBANK_SUPPORT */ void FLASH_PageErase(uint32_t Page); +#endif /* FLASH_DBANK_SUPPORT */ /** * @} */ @@ -304,7 +412,32 @@ void FLASH_PageErase(uint32_t Page); #define IS_FLASH_CFGLPM(CFG) (((CFG) == FLASH_LPM_DISABLE) || \ ((CFG) == FLASH_LPM_ENABLE)) - +#if defined(FLASH_SECHDPEXTR_HDP_PEXT) +#define IS_FLASH_EXTHDP_PROTECTION(CFG) (((CFG) == FLASH_EXTHDP_ONLY_ACCESS_PROTECTED) || \ + ((CFG) == FLASH_EXTHDP_ALL_PROTECTED)) +#endif /* FLASH_SECHDPEXTR_HDP_PEXT */ + +#if defined(FLASH_DBANK_SUPPORT) +#define IS_FLASH_SUSPEND_REQ(VALUE) (((VALUE) == FLASH_SUSPEND_PROGRAM) || \ + ((VALUE) == FLASH_SUSPEND_BANK1_PROGRAM) || \ + ((VALUE) == FLASH_SUSPEND_BANK2_PROGRAM) || \ + ((VALUE) == FLASH_SUSPEND_ERASE) || \ + ((VALUE) == FLASH_SUSPEND_BANK1_ERASE) || \ + ((VALUE) == FLASH_SUSPEND_BANK2_ERASE) || \ + ((VALUE) == FLASH_SUSPEND_PROGRAM_ERASE) || \ + ((VALUE) == FLASH_SUSPEND_BANK1_PROGRAM_ERASE) || \ + ((VALUE) == FLASH_SUSPEND_BANK2_PROGRAM_ERASE)) + +#define IS_FLASH_ALLOW_REQ(VALUE) (((VALUE) == FLASH_ALLOW_PROGRAM) || \ + ((VALUE) == FLASH_ALLOW_BANK1_PROGRAM) || \ + ((VALUE) == FLASH_ALLOW_BANK2_PROGRAM) || \ + ((VALUE) == FLASH_ALLOW_ERASE) || \ + ((VALUE) == FLASH_ALLOW_BANK1_ERASE) || \ + ((VALUE) == FLASH_ALLOW_BANK2_ERASE) || \ + ((VALUE) == FLASH_ALLOW_PROGRAM_ERASE) || \ + ((VALUE) == FLASH_ALLOW_BANK1_PROGRAM_ERASE) || \ + ((VALUE) == FLASH_ALLOW_BANK2_PROGRAM_ERASE)) +#else /* FLASH_DBANK_SUPPORT */ #define IS_FLASH_SUSPEND_REQ(VALUE) (((VALUE) == FLASH_SUSPEND_PROGRAM) || \ ((VALUE) == FLASH_SUSPEND_ERASE) || \ ((VALUE) == FLASH_SUSPEND_PROGRAM_ERASE)) @@ -312,6 +445,7 @@ void FLASH_PageErase(uint32_t Page); #define IS_FLASH_ALLOW_REQ(VALUE) (((VALUE) == FLASH_ALLOW_PROGRAM) || \ ((VALUE) == FLASH_ALLOW_ERASE) || \ ((VALUE) == FLASH_ALLOW_PROGRAM_ERASE)) +#endif /* FLASH_DBANK_SUPPORT */ /** * @} */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_gpio.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_gpio.h index 5b2efdef2f..b1d1359dc0 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_gpio.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_gpio.h @@ -352,6 +352,10 @@ GPIO_PinState HAL_GPIO_ReadPin(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); void HAL_GPIO_WriteMultipleStatePin(GPIO_TypeDef *GPIOx, uint16_t PinReset, uint16_t PinSet); void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +#if defined (STM32WBA62xx) || defined (STM32WBA63xx) || defined (STM32WBA64xx) || defined (STM32WBA65xx) || defined (STM32WBA6Mxx) +void HAL_GPIO_EnableHighSPeedLowVoltage(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_DisableHighSPeedLowVoltage(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +#endif /* defined (STM32WBA62xx) || defined (STM32WBA63xx) || defined (STM32WBA64xx) || defined (STM32WBA65xx) || defined (STM32WBA6Mxx) */ HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin); void HAL_GPIO_EXTI_Rising_Callback(uint16_t GPIO_Pin); diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_gpio_ex.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_gpio_ex.h index 08ca6a5e92..1d580d31a2 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_gpio_ex.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_gpio_ex.h @@ -48,6 +48,9 @@ extern "C" { * @{ */ + + + #if defined(STM32WBA54xx) || defined(STM32WBA55xx) || defined(STM32WBA5Mxx) /** * @brief AF 0 selection @@ -114,6 +117,11 @@ extern "C" { */ #define GPIO_AF9_TSC ((uint8_t)0x09) /*!< TSC Alternate Function mapping */ +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_PTA ((uint8_t)0x0A) /*!< PTA Alternate Function mapping */ + /** * @brief AF 11 selection */ @@ -124,6 +132,7 @@ extern "C" { */ #define GPIO_AF12_COMP1 ((uint8_t)0x0C) /*!< COMP1 Alternate Function mapping */ #define GPIO_AF12_COMP2 ((uint8_t)0x0C) /*!< COMP2 Alternate Function mapping */ +#define GPIO_AF12_PTA ((uint8_t)0x0C) /*!< PTA Alternate Function mapping */ /** * @brief AF 13 selection @@ -318,6 +327,237 @@ extern "C" { #endif /* defined(STM32WBA50xx) */ +#if defined(STM32WBA62xx) || defined(STM32WBA64xx) || defined(STM32WBA65xx) || defined (STM32WBA6Mxx) +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /*!< RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< MCO Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /*!< SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00) /*!< TRACE Alternate Function mapping */ +#define GPIO_AF0_LPTIM1 ((uint8_t)0x00) /*!< LPTIM1 Alternate Function mapping */ +#define GPIO_AF0_PWR ((uint8_t)0x00) /*!< PWR Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01) /*!< TIM2 Alternate Function mapping */ +#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /*!< LPTIM1 Alternate Function mapping */ +#define GPIO_AF1_IR ((uint8_t)0x01) /*!< IR Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02) /*!< TIM2 Alternate Function mapping */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02) /*!< TIM3 Alternate Function mapping */ +#define GPIO_AF2_LPTIM1 ((uint8_t)0x02) /*!< LPTIM1 Alternate Function mapping */ +#define GPIO_AF2_LPTIM2 ((uint8_t)0x02) /*!< LPTIM2 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_SAI1 ((uint8_t)0x03) /*!< SAI1 Alternate Function mapping */ +#define GPIO_AF3_USART2 ((uint8_t)0x03) /*!< USART2 Alternate Function mapping */ +#define GPIO_AF3_IR ((uint8_t)0x03) /*!< IR Alternate Function mapping */ +#define GPIO_AF3_I2C4 ((uint8_t)0x03) /*!< I2C4 Alternate Function mapping */ +#define GPIO_AF3_SPI2 ((uint8_t)0x03) /*!< SPI2 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /*!< I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04) /*!< I2C2 Alternate Function mapping */ +#define GPIO_AF4_I2C3 ((uint8_t)0x04) /*!< I2C3 Alternate Function mapping */ +#define GPIO_AF4_I2C4 ((uint8_t)0x04) /*!< I2C4 Alternate Function mapping */ +#define GPIO_AF4_OTG_HS ((uint8_t)0x04) /*!< OTG-HS Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /*!< SPI1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF5_SPI3 ((uint8_t)0x05) /*!< SPI3 Alternate Function mapping */ +#define GPIO_AF5_I2C4 ((uint8_t)0x05) /*!< I2C4 Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_I2C3 ((uint8_t)0x06) /*!< I2C3 Alternate Function mapping */ +#define GPIO_AF6_SPI2 ((uint8_t)0x06) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06) /*!< SPI3 Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_USART1 ((uint8_t)0x07) /*!< USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07) /*!< USART2 Alternate Function mapping */ +#define GPIO_AF7_USART3 ((uint8_t)0x07) /*!< USART3 Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_LPUART1 ((uint8_t)0x08) /*!< LPUART1 Alternate Function mapping */ +#define GPIO_AF8_USART3 ((uint8_t)0x08) /*!< USART3 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_TSC ((uint8_t)0x09) /*!< TSC Alternate Function mapping */ + +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_PTA ((uint8_t)0x0A) /*!< PTA Alternate Function mapping */ +#define GPIO_AF10_USB_OTG_HS ((uint8_t)0x0A) /*!< USB OTG-HS Alternate Function mapping */ + +/** + * @brief AF 11 selection + */ +#define GPIO_AF11_RF ((uint8_t)0x0B) /*!< RF_ANTSW0 Alternate Function mapping */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_COMP1 ((uint8_t)0x0C) /*!< COMP1 Alternate Function mapping */ +#define GPIO_AF12_COMP2 ((uint8_t)0x0C) /*!< COMP2 Alternate Function mapping */ +#define GPIO_AF12_PTA ((uint8_t)0x0C) /*!< PTA Alternate Function mapping */ +#define GPIO_AF12_TIM4 ((uint8_t)0x0C) /*!< TIM4 Alternate Function mapping */ + +/** + * @brief AF 13 selection + */ +#define GPIO_AF13_SAI1 ((uint8_t)0x0D) /*!< SAI1 Alternate Function mapping */ +#define GPIO_AF13_LPTIM2 ((uint8_t)0x0D) /*!< LPTIM2 Alternate Function mapping */ +#define GPIO_AF13_TIM4 ((uint8_t)0x0D) /*!< TIM4 Alternate Function mapping */ + +/** + * @brief AF 14 selection + */ +#define GPIO_AF14_LPTIM2 ((uint8_t)0x0E) /*!< LPTIM2 Alternate Function mapping */ +#define GPIO_AF14_TIM3 ((uint8_t)0x0E) /*!< TIM3 Alternate Function mapping */ +#define GPIO_AF14_TIM16 ((uint8_t)0x0E) /*!< TIM16 Alternate Function mapping */ +#define GPIO_AF14_TIM17 ((uint8_t)0x0E) /*!< TIM17 Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /*!< EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F) + +#endif /* defined(STM32WBA62xx) || defined(STM32WBA64xx) || defined(STM32WBA65xx) || defined (STM32WBA6Mxx) */ + +#if defined(STM32WBA63xx) +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /*!< RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< MCO Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /*!< SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00) /*!< TRACE Alternate Function mapping */ +#define GPIO_AF0_LPTIM1 ((uint8_t)0x00) /*!< LPTIM1 Alternate Function mapping */ +#define GPIO_AF0_PWR ((uint8_t)0x00) /*!< PWR Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01) /*!< TIM2 Alternate Function mapping */ +#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /*!< LPTIM1 Alternate Function mapping */ +#define GPIO_AF1_IR ((uint8_t)0x01) /*!< IR Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02) /*!< TIM2 Alternate Function mapping */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02) /*!< TIM3 Alternate Function mapping */ +#define GPIO_AF2_LPTIM1 ((uint8_t)0x02) /*!< LPTIM1 Alternate Function mapping */ +#define GPIO_AF2_LPTIM2 ((uint8_t)0x02) /*!< LPTIM2 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_SAI1 ((uint8_t)0x03) /*!< SAI1 Alternate Function mapping */ +#define GPIO_AF3_USART2 ((uint8_t)0x03) /*!< USART2 Alternate Function mapping */ +#define GPIO_AF3_IR ((uint8_t)0x03) /*!< IR Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /*!< I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C3 ((uint8_t)0x04) /*!< I2C3 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /*!< SPI1 Alternate Function mapping */ +#define GPIO_AF5_SPI3 ((uint8_t)0x05) /*!< SPI3 Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_I2C3 ((uint8_t)0x06) /*!< I2C3 Alternate Function mapping */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06) /*!< SPI3 Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_USART1 ((uint8_t)0x07) /*!< USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07) /*!< USART2 Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_LPUART1 ((uint8_t)0x08) /*!< LPUART1 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_TSC ((uint8_t)0x09) /*!< TSC Alternate Function mapping */ + +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_PTA ((uint8_t)0x0A) /*!< PTA Alternate Function mapping */ + +/** + * @brief AF 11 selection + */ +#define GPIO_AF11_RF ((uint8_t)0x0B) /*!< RF_ANTSW0 Alternate Function mapping */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_COMP1 ((uint8_t)0x0C) /*!< COMP1 Alternate Function mapping */ +#define GPIO_AF12_COMP2 ((uint8_t)0x0C) /*!< COMP2 Alternate Function mapping */ +#define GPIO_AF12_PTA ((uint8_t)0x0C) /*!< PTA Alternate Function mapping */ + +/** + * @brief AF 13 selection + */ +#define GPIO_AF13_SAI1 ((uint8_t)0x0D) /*!< SAI1 Alternate Function mapping */ +#define GPIO_AF13_LPTIM2 ((uint8_t)0x0D) /*!< LPTIM2 Alternate Function mapping */ + +/** + * @brief AF 14 selection + */ +#define GPIO_AF14_LPTIM2 ((uint8_t)0x0E) /*!< LPTIM2 Alternate Function mapping */ +#define GPIO_AF14_TIM3 ((uint8_t)0x0E) /*!< TIM3 Alternate Function mapping */ +#define GPIO_AF14_TIM16 ((uint8_t)0x0E) /*!< TIM16 Alternate Function mapping */ +#define GPIO_AF14_TIM17 ((uint8_t)0x0E) /*!< TIM17 Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /*!< EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F) + +#endif /* defined (STM32WBA63xx) */ + /** * @} */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_gtzc.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_gtzc.h index 15db1cefc0..e49e1fe210 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_gtzc.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_gtzc.h @@ -45,6 +45,8 @@ extern "C" { /*!< Values needed for MPCBB_Attribute_ConfigTypeDef structure sizing */ #if defined (STM32WBA52xx) || defined (STM32WBA54xx) || defined (STM32WBA55xx) || defined (STM32WBA5Mxx) #define GTZC_MPCBB_NB_VCTR_REG_MAX 4U /*!< Maximum number of superblocks */ +#elif defined (STM32WBA62xx) || defined (STM32WBA63xx) || defined (STM32WBA64xx) || defined (STM32WBA65xx) || defined (STM32WBA6Mxx) +#define GTZC_MPCBB_NB_VCTR_REG_MAX 28U /*!< Maximum number of superblocks */ #endif #define GTZC_MPCBB_NB_LCK_VCTR_REG_MAX 1U /*!< Maximum number of 32-bit registers to lock superblocks */ typedef struct @@ -68,6 +70,7 @@ typedef struct MPCBB_Attribute_ConfigTypeDef AttributeConfig; /*!< MPCBB attribute configuration sub-structure */ } MPCBB_ConfigTypeDef; + /** * @} */ @@ -147,6 +150,7 @@ typedef struct * @} */ + /** @defgroup GTZC_TZSC_TZIC_PeriphId GTZC TZSC and TZIC Peripheral identifier values * @{ */ @@ -155,26 +159,46 @@ typedef struct #if defined (TIM3) #define GTZC_PERIPH_TIM3 (GTZC_PERIPH_REG1 | GTZC_CFGR1_TIM3_Pos) #endif /* TIM3 */ +#if defined (TIM4) +#define GTZC_PERIPH_TIM4 (GTZC_PERIPH_REG1 | GTZC_CFGR1_TIM4_Pos) +#endif /* TIM4 */ #if defined (WWDG) #define GTZC_PERIPH_WWDG (GTZC_PERIPH_REG1 | GTZC_CFGR1_WWDG_Pos) #endif /* WWDG */ #define GTZC_PERIPH_IWDG (GTZC_PERIPH_REG1 | GTZC_CFGR1_IWDG_Pos) +#if defined (SPI2) +#define GTZC_PERIPH_SPI2 (GTZC_PERIPH_REG1 | GTZC_CFGR1_SPI2_Pos) +#endif /* SPI2 */ #if defined (USART2) #define GTZC_PERIPH_USART2 (GTZC_PERIPH_REG1 | GTZC_CFGR1_USART2_Pos) #endif /* USART2 */ +#if defined (USART3) +#define GTZC_PERIPH_USART3 (GTZC_PERIPH_REG1 | GTZC_CFGR1_USART3_Pos) +#endif /* USART3 */ #define GTZC_PERIPH_I2C1 (GTZC_PERIPH_REG1 | GTZC_CFGR1_I2C1_Pos) +#if defined (I2C2) +#define GTZC_PERIPH_I2C2 (GTZC_PERIPH_REG1 | GTZC_CFGR1_I2C2_Pos) +#endif /* I2C2 */ +#if defined (I2C4) +#define GTZC_PERIPH_I2C4 (GTZC_PERIPH_REG1 | GTZC_CFGR1_I2C4_Pos) +#endif /* I2C4 */ #define GTZC_PERIPH_LPTIM2 (GTZC_PERIPH_REG1 | GTZC_CFGR1_LPTIM2_Pos) #if defined (TIM1) #define GTZC_PERIPH_TIM1 (GTZC_PERIPH_REG2 | GTZC_CFGR2_TIM1_Pos) #endif /* TIM1 */ +#if defined (SPI1) #define GTZC_PERIPH_SPI1 (GTZC_PERIPH_REG2 | GTZC_CFGR2_SPI1_Pos) +#endif /* SPI1 */ #define GTZC_PERIPH_USART1 (GTZC_PERIPH_REG2 | GTZC_CFGR2_USART1_Pos) #define GTZC_PERIPH_TIM16 (GTZC_PERIPH_REG2 | GTZC_CFGR2_TIM16_Pos) #define GTZC_PERIPH_TIM17 (GTZC_PERIPH_REG2 | GTZC_CFGR2_TIM17_Pos) #if defined (SAI1) #define GTZC_PERIPH_SAI1 (GTZC_PERIPH_REG2 | GTZC_CFGR2_SAI1_Pos) #endif /* SAI1 */ +#if defined (USB_DRD_FS) +#define GTZC_PERIPH_USB1 (GTZC_PERIPH_REG2 | GTZC_CFGR2_USB1_Pos) +#endif /* USB_DRD_FS */ #if defined (SPI3) #define GTZC_PERIPH_SPI3 (GTZC_PERIPH_REG2 | GTZC_CFGR2_SPI3_Pos) #endif /* SPI3 */ @@ -185,12 +209,18 @@ typedef struct #define GTZC_PERIPH_COMP (GTZC_PERIPH_REG2 | GTZC_CFGR2_COMP_Pos) #endif /* COMP1 */ #define GTZC_PERIPH_ADC4 (GTZC_PERIPH_REG2 | GTZC_CFGR2_ADC4_Pos) +#if defined (VREFBUF) +#define GTZC_PERIPH_VREFBUF (GTZC_PERIPH_REG2 | GTZC_CFGR2_VREFBUF_Pos) +#endif /* VREFBUF */ #define GTZC_PERIPH_CRC (GTZC_PERIPH_REG3 | GTZC_CFGR3_CRC_Pos) #if defined (TSC) #define GTZC_PERIPH_TSC (GTZC_PERIPH_REG3 | GTZC_CFGR3_TSC_Pos) #endif /* TSC */ #define GTZC_PERIPH_ICACHE_REG (GTZC_PERIPH_REG3 | GTZC_CFGR3_ICACHE_REG_Pos) +#if defined (USB_OTG_HS) +#define GTZC_PERIPH_OTG (GTZC_PERIPH_REG3 | GTZC_CFGR3_OTG_Pos) +#endif /* USB_OTG_HS */ #define GTZC_PERIPH_AES (GTZC_PERIPH_REG3 | GTZC_CFGR3_AES_Pos) #define GTZC_PERIPH_HASH (GTZC_PERIPH_REG3 | GTZC_CFGR3_HASH_Pos) #define GTZC_PERIPH_RNG (GTZC_PERIPH_REG3 | GTZC_CFGR3_RNG_Pos) @@ -201,15 +231,26 @@ typedef struct #define GTZC_PERIPH_HSEM (GTZC_PERIPH_REG3 | GTZC_CFGR3_HSEM_Pos) #endif /* HSEM */ #define GTZC_PERIPH_PKA (GTZC_PERIPH_REG3 | GTZC_CFGR3_PKA_Pos) +#if defined (XSPI1) +#define GTZC_PERIPH_XSPI1 (GTZC_PERIPH_REG3 | GTZC_CFGR3_XSPI1_Pos) +#endif /* XSPI1 */ #define GTZC_PERIPH_RAMCFG (GTZC_PERIPH_REG3 | GTZC_CFGR3_RAMCFG_Pos) #define GTZC_PERIPH_RADIO (GTZC_PERIPH_REG3 | GTZC_CFGR3_RADIO_Pos) #if defined (PTACONV) #define GTZC_PERIPH_PTACONV (GTZC_PERIPH_REG3 | GTZC_CFGR3_PTACONV_Pos) #endif /* PTACONV */ +#if defined (LPDMA1) +#define GTZC_PERIPH_LPDMA1 (GTZC_PERIPH_REG4 | GTZC_CFGR4_LPDMA1_Pos) +#endif /* LPDMA1 */ +#if defined (GPDMA1) #define GTZC_PERIPH_GPDMA1 (GTZC_PERIPH_REG4 | GTZC_CFGR4_GPDMA1_Pos) +#endif /* GPDMA1 */ #define GTZC_PERIPH_FLASH (GTZC_PERIPH_REG4 | GTZC_CFGR4_FLASH_Pos) #define GTZC_PERIPH_FLASH_REG (GTZC_PERIPH_REG4 | GTZC_CFGR4_FLASH_REG_Pos) +#if defined (OTFDEC1) +#define GTZC_PERIPH_OTFDEC1 (GTZC_PERIPH_REG4 | GTZC_CFGR4_OTFDEC1_Pos) +#endif /* OTFDEC1 */ #define GTZC_PERIPH_SYSCFG (GTZC_PERIPH_REG4 | GTZC_CFGR4_SYSCFG_Pos) #define GTZC_PERIPH_RTC (GTZC_PERIPH_REG4 | GTZC_CFGR4_RTC_Pos) #define GTZC_PERIPH_TAMP (GTZC_PERIPH_REG4 | GTZC_CFGR4_TAMP_Pos) @@ -218,14 +259,17 @@ typedef struct #define GTZC_PERIPH_EXTI (GTZC_PERIPH_REG4 | GTZC_CFGR4_EXTI_Pos) #define GTZC_PERIPH_TZSC (GTZC_PERIPH_REG4 | GTZC_CFGR4_TZSC_Pos) #define GTZC_PERIPH_TZIC (GTZC_PERIPH_REG4 | GTZC_CFGR4_TZIC_Pos) +#if defined (XSPI1) +#define GTZC_PERIPH_MPCWM1 (GTZC_PERIPH_REG4 | GTZC_CFGR4_MPCWM1_REG_Pos) +#endif /* XSPI1 */ #define GTZC_PERIPH_SRAM1 (GTZC_PERIPH_REG4 | GTZC_CFGR4_SRAM1_Pos) #define GTZC_PERIPH_MPCBB1_REG (GTZC_PERIPH_REG4 | GTZC_CFGR4_MPCBB1_REG_Pos) #define GTZC_PERIPH_SRAM2 (GTZC_PERIPH_REG4 | GTZC_CFGR4_SRAM2_Pos) #define GTZC_PERIPH_MPCBB2_REG (GTZC_PERIPH_REG4 | GTZC_CFGR4_MPCBB2_REG_Pos) -#if defined (SRAM6_BASE) +#if defined (GTZC_MPCBB6) #define GTZC_PERIPH_SRAM6 (GTZC_PERIPH_REG4 | GTZC_CFGR4_SRAM6_Pos) #define GTZC_PERIPH_MPCBB6_REG (GTZC_PERIPH_REG4 | GTZC_CFGR4_MPCBB6_REG_Pos) -#endif /* SRAM6 */ +#endif /* MPCBB6 */ #define GTZC_PERIPH_ALL (0x00000020U) @@ -240,7 +284,11 @@ typedef struct #else #define GTZC_TZSC_PERIPH_NUMBER (HAL_GTZC_GET_ARRAY_INDEX(GTZC_PERIPH_RADIO) + 1U) #endif /* PTACONV */ +#if defined(GTZC_MPCBB6) #define GTZC_TZIC_PERIPH_NUMBER (HAL_GTZC_GET_ARRAY_INDEX(GTZC_PERIPH_MPCBB6_REG) + 1U) +#else +#define GTZC_TZIC_PERIPH_NUMBER (HAL_GTZC_GET_ARRAY_INDEX(GTZC_PERIPH_MPCBB2_REG) + 1U) +#endif /* GTZC_MPCBB6 */ /** * @} @@ -396,6 +444,7 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_GetConfigPeriphAttributes(uint32_t PeriphId, * @} */ + #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** @addtogroup GTZC_Exported_Functions_Group3 diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_hcd.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_hcd.h new file mode 100644 index 0000000000..f2e387118b --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_hcd.h @@ -0,0 +1,633 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_hcd.h + * @author MCD Application Team + * @brief Header file of HCD HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_HAL_HCD_H +#define STM32WBAxx_HAL_HCD_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_ll_usb.h" + +#if defined (USB_OTG_HS) || defined (USB_DRD_FS) +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @addtogroup HCD HCD + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup HCD_Exported_Types HCD Exported Types + * @{ + */ + +/** @defgroup HCD_Exported_Types_Group1 HCD State Structure definition + * @{ + */ +typedef enum +{ + HAL_HCD_STATE_RESET = 0x00, + HAL_HCD_STATE_READY = 0x01, + HAL_HCD_STATE_ERROR = 0x02, + HAL_HCD_STATE_BUSY = 0x03, + HAL_HCD_STATE_TIMEOUT = 0x04 +} HCD_StateTypeDef; + +#if defined (USB_DRD_FS) +typedef USB_DRD_TypeDef HCD_TypeDef; +typedef USB_DRD_CfgTypeDef HCD_InitTypeDef; +typedef USB_DRD_HCTypeDef HCD_HCTypeDef; +typedef USB_DRD_URBStateTypeDef HCD_URBStateTypeDef; +typedef USB_DRD_HCStateTypeDef HCD_HCStateTypeDef; +#else +typedef USB_OTG_GlobalTypeDef HCD_TypeDef; +typedef USB_OTG_CfgTypeDef HCD_InitTypeDef; +typedef USB_OTG_HCTypeDef HCD_HCTypeDef; +typedef USB_OTG_URBStateTypeDef HCD_URBStateTypeDef; +typedef USB_OTG_HCStateTypeDef HCD_HCStateTypeDef; +#endif /* defined (USB_DRD_FS) */ +#if defined (USB_DRD_FS) +typedef enum +{ + HCD_HCD_STATE_DISCONNECTED = 0x00U, + HCD_HCD_STATE_CONNECTED = 0x01U, + HCD_HCD_STATE_RESETED = 0x02U, + HCD_HCD_STATE_RUN = 0x03U, + HCD_HCD_STATE_SUSPEND = 0x04U, + HCD_HCD_STATE_RESUME = 0x05U, +} HCD_HostStateTypeDef; + +/* PMA lookup Table size depending on PMA Size + * 8Bytes each Block 32Bit in each word + */ +#define PMA_BLOCKS ((USB_DRD_PMA_SIZE) / (8U * 32U)) +#endif /* defined (USB_DRD_FS) */ +/** + * @} + */ + +/** @defgroup HCD_Exported_Types_Group2 HCD Handle Structure definition + * @{ + */ +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) +typedef struct __HCD_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ +{ + HCD_TypeDef *Instance; /*!< Register base address */ + HCD_InitTypeDef Init; /*!< HCD required parameters */ + HCD_HCTypeDef hc[16]; /*!< Host channels parameters */ +#if defined (USB_DRD_FS) + uint32_t ep0_PmaAllocState; /*!< EP0 PMA allocation State (allocated, virtual Ch, EP0 direction) */ + uint16_t phy_chin_state[8]; /*!< Physical Channel in State (Used/Free) */ + uint16_t phy_chout_state[8]; /*!< Physical Channel out State (Used/Free)*/ + uint32_t PMALookupTable[PMA_BLOCKS]; /*PMA LookUp Table */ + HCD_HostStateTypeDef HostState; /*!< USB current state DICONNECT/CONNECT/RUN/SUSPEND/RESUME */ +#endif /* defined (USB_DRD_FS) */ + HAL_LockTypeDef Lock; /*!< HCD peripheral status */ + __IO HCD_StateTypeDef State; /*!< HCD communication state */ + __IO uint32_t ErrorCode; /*!< HCD Error code */ + void *pData; /*!< Pointer Stack Handler */ +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + void (* SOFCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD SOF callback */ + void (* ConnectCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Connect callback */ + void (* DisconnectCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Disconnect callback */ + void (* PortEnabledCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Port Enable callback */ + void (* PortDisabledCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Port Disable callback */ + void (* HC_NotifyURBChangeCallback)(struct __HCD_HandleTypeDef *hhcd, uint8_t chnum, + HCD_URBStateTypeDef urb_state); /*!< USB OTG HCD Host Channel Notify URB Change callback */ + + void (* MspInitCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Msp Init callback */ + void (* MspDeInitCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Msp DeInit callback */ +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ +} HCD_HandleTypeDef; +/** + * @} + */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup HCD_Exported_Constants HCD Exported Constants + * @{ + */ +#ifndef HAL_HCD_CHANNEL_NAK_COUNT +#define HAL_HCD_CHANNEL_NAK_COUNT 2U +#endif /* HAL_HCD_CHANNEL_NAK_COUNT */ + +/** @defgroup HCD_Speed HCD Speed + * @{ + */ +#define HCD_SPEED_HIGH USBH_HS_SPEED +#define HCD_SPEED_FULL USBH_FSLS_SPEED +#define HCD_SPEED_LOW USBH_FSLS_SPEED +/** + * @} + */ + +/** @defgroup HCD_Device_Speed HCD Device Speed + * @{ + */ +#define HCD_DEVICE_SPEED_HIGH 0U +#define HCD_DEVICE_SPEED_FULL 1U +#define HCD_DEVICE_SPEED_LOW 2U +/** + * @} + */ + +/** @defgroup HCD_PHY_Module HCD PHY Module + * @{ + */ +#define HCD_PHY_ULPI 1U +#define HCD_PHY_EMBEDDED 2U +/** + * @} + */ + +/** @defgroup HCD_Error_Code_definition HCD Error Code definition + * @brief HCD Error Code definition + * @{ + */ +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) +#define HAL_HCD_ERROR_INVALID_CALLBACK (0x00000010U) /*!< Invalid Callback error */ +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup HCD_Exported_Macros HCD Exported Macros + * @brief macros to handle interrupts and specific clock configurations + * @{ + */ +#define __HAL_HCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance) +#define __HAL_HCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance) + +#define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance)\ + & (__INTERRUPT__)) == (__INTERRUPT__)) +#if defined (USB_DRD_FS) +#define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) &= ~(__INTERRUPT__)) +#else +#define __HAL_HCD_GET_CH_FLAG(__HANDLE__, __chnum__, __INTERRUPT__) \ + ((USB_ReadChInterrupts((__HANDLE__)->Instance, (__chnum__)) & (__INTERRUPT__)) == (__INTERRUPT__)) + +#define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__)) +#endif /* defined (USB_DRD_FS) */ +#define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U) + +#if defined (USB_DRD_FS) +#define __HAL_HCD_GET_CHNUM(__HANDLE__) (((__HANDLE__)->Instance->ISTR) & USB_ISTR_IDN) +#define __HAL_HCD_GET_CHDIR(__HANDLE__) (((__HANDLE__)->Instance->ISTR) & USB_ISTR_DIR) +#else +#define __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__) (USBx_HC(chnum)->HCINT = (__INTERRUPT__)) +#define __HAL_HCD_MASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM) +#define __HAL_HCD_UNMASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM) +#define __HAL_HCD_MASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM) +#define __HAL_HCD_UNMASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM) +#define __HAL_HCD_SET_HC_CSPLT(chnum) (USBx_HC(chnum)->HCSPLT |= USB_OTG_HCSPLT_COMPLSPLT) +#define __HAL_HCD_CLEAR_HC_CSPLT(chnum) (USBx_HC(chnum)->HCSPLT &= ~USB_OTG_HCSPLT_COMPLSPLT) +#define __HAL_HCD_CLEAR_HC_SSPLT(chnum) (USBx_HC(chnum)->HCSPLT &= ~USB_OTG_HCSPLT_SPLITEN) +#endif /* defined (USB_DRD_FS) */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup HCD_Exported_Functions HCD Exported Functions + * @{ + */ + +/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd); +HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd); +HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num, + uint8_t epnum, uint8_t dev_address, + uint8_t speed, uint8_t ep_type, uint16_t mps); + +HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num); +HAL_StatusTypeDef HAL_HCD_HC_Activate(HCD_HandleTypeDef *hhcd, uint8_t ch_num); +#if defined (USB_DRD_FS) +HAL_StatusTypeDef HAL_HCD_HC_Close(HCD_HandleTypeDef *hhcd, uint8_t ch_num); +#endif /* defined (USB_DRD_FS) */ +void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd); +void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd); + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) +/** @defgroup HAL_HCD_Callback_ID_enumeration_definition HAL USB OTG HCD Callback ID enumeration definition + * @brief HAL USB OTG HCD Callback ID enumeration definition + * @{ + */ +typedef enum +{ + HAL_HCD_SOF_CB_ID = 0x01, /*!< USB HCD SOF callback ID */ + HAL_HCD_CONNECT_CB_ID = 0x02, /*!< USB HCD Connect callback ID */ + HAL_HCD_DISCONNECT_CB_ID = 0x03, /*!< USB HCD Disconnect callback ID */ + HAL_HCD_PORT_ENABLED_CB_ID = 0x04, /*!< USB HCD Port Enable callback ID */ + HAL_HCD_PORT_DISABLED_CB_ID = 0x05, /*!< USB HCD Port Disable callback ID */ + + HAL_HCD_MSPINIT_CB_ID = 0x06, /*!< USB HCD MspInit callback ID */ + HAL_HCD_MSPDEINIT_CB_ID = 0x07 /*!< USB HCD MspDeInit callback ID */ + +} HAL_HCD_CallbackIDTypeDef; +/** + * @} + */ + +/** @defgroup HAL_HCD_Callback_pointer_definition HAL USB OTG HCD Callback pointer definition + * @brief HAL USB OTG HCD Callback pointer definition + * @{ + */ + +typedef void (*pHCD_CallbackTypeDef)(HCD_HandleTypeDef *hhcd); /*!< pointer to a common USB OTG HCD callback function */ +typedef void (*pHCD_HC_NotifyURBChangeCallbackTypeDef)(HCD_HandleTypeDef *hhcd, + uint8_t epnum, + HCD_URBStateTypeDef urb_state); /*!< pointer to USB OTG HCD host channel callback */ +/** + * @} + */ + +HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd, + HAL_HCD_CallbackIDTypeDef CallbackID, + pHCD_CallbackTypeDef pCallback); + +HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd, + HAL_HCD_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd, + pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback); + +HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ +/** + * @} + */ + +/* I/O operation functions ***************************************************/ +/** @addtogroup HCD_Exported_Functions_Group2 Input and Output operation functions + * @{ + */ +HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, uint8_t ch_num, + uint8_t direction, uint8_t ep_type, + uint8_t token, uint8_t *pbuff, + uint16_t length, uint8_t do_ping); + +HAL_StatusTypeDef HAL_HCD_HC_SetHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num, + uint8_t addr, uint8_t PortNbr); + +HAL_StatusTypeDef HAL_HCD_HC_ClearHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num); + +/* Non-Blocking mode: Interrupt */ +void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd); +void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd); +void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd); +void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd); +void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd); +void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd); +#if defined (USB_DRD_FS) +void HAL_HCD_SuspendCallback(HCD_HandleTypeDef *hhcd); +void HAL_HCD_ResumeCallback(HCD_HandleTypeDef *hhcd); +#endif /* defined (USB_DRD_FS) */ +void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, + HCD_URBStateTypeDef urb_state); +/** + * @} + */ + +/* Peripheral Control functions **********************************************/ +/** @addtogroup HCD_Exported_Functions_Group3 Peripheral Control functions + * @{ + */ +HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd); +HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd); +HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd); +#if defined (USB_DRD_FS) +HAL_StatusTypeDef HAL_HCD_Suspend(HCD_HandleTypeDef *hhcd); +HAL_StatusTypeDef HAL_HCD_Resume(HCD_HandleTypeDef *hhcd); +HAL_StatusTypeDef HAL_HCD_ResumePort(HCD_HandleTypeDef *hhcd); +#endif /* defined (USB_DRD_FS) */ +/** + * @} + */ + +/* Peripheral State functions ************************************************/ +/** @addtogroup HCD_Exported_Functions_Group4 Peripheral State functions + * @{ + */ +HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef const *hhcd); +HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef const *hhcd, uint8_t chnum); +HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef const *hhcd, uint8_t chnum); +uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef const *hhcd, uint8_t chnum); +uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd); +uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd); + +#if defined (USB_DRD_FS) +/* PMA Allocation functions **********************************************/ +/** @addtogroup PMA Allocation + * @{ + */ +HAL_StatusTypeDef HAL_HCD_PMAlloc(HCD_HandleTypeDef *hhcd, uint8_t ch_num, + uint16_t ch_kind, uint16_t mps); + +HAL_StatusTypeDef HAL_HCD_PMADeAlloc(HCD_HandleTypeDef *hhcd, uint8_t ch_num); +HAL_StatusTypeDef HAL_HCD_PMAReset(HCD_HandleTypeDef *hhcd); + +/** + * @} + */ +#endif /* defined (USB_DRD_FS) */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup HCD_Private_Macros HCD Private Macros + * @{ + */ +#if defined (USB_DRD_FS) +#define HCD_MIN(a, b) (((a) < (b)) ? (a) : (b)) +#define HCD_MAX(a, b) (((a) > (b)) ? (a) : (b)) + +/** @defgroup HCD_LOGICAL_CHANNEL HCD Logical Channel + * @{ + */ +#define HCD_LOGICAL_CH_NOT_OPENED 0xFFU +#define HCD_FREE_CH_NOT_FOUND 0xFFU +/** + * @} + */ + +/** @defgroup HCD_ENDP_Kind HCD Endpoint Kind + * @{ + */ +#define HCD_SNG_BUF 0U +#define HCD_DBL_BUF 1U +/** + * @} + */ + +/* Powerdown exit count */ +#define HCD_PDWN_EXIT_CNT 0x100U + +/* Set Channel */ +#define HCD_SET_CHANNEL USB_DRD_SET_CHEP + +/* Get Channel Register */ +#define HCD_GET_CHANNEL USB_DRD_GET_CHEP + + +/** + * @brief free buffer used from the application realizing it to the line + * toggles bit SW_BUF in the double buffered endpoint register + * @param USBx USB device. + * @param bChNum, bDir + * @retval None + */ +#define HCD_FREE_USER_BUFFER USB_DRD_FREE_USER_BUFFER + +/** + * @brief Set the Setup bit in the corresponding channel, when a Setup + transaction is needed. + * @param USBx USB device. + * @param bChNum + * @retval None + */ +#define HAC_SET_CH_TX_SETUP USB_DRD_CHEP_TX_SETUP + +/** + * @brief sets the status for tx transfer (bits STAT_TX[1:0]). + * @param USBx USB peripheral instance register address. + * @param bChNum Endpoint Number. + * @param wState new state + * @retval None + */ +#define HCD_SET_CH_TX_STATUS USB_DRD_SET_CHEP_TX_STATUS + +/** + * @brief sets the status for rx transfer (bits STAT_TX[1:0]) + * @param USBx USB peripheral instance register address. + * @param bChNum Endpoint Number. + * @param wState new state + * @retval None + */ +#define HCD_SET_CH_RX_STATUS USB_DRD_SET_CHEP_RX_STATUS +/** + * @brief gets the status for tx/rx transfer (bits STAT_TX[1:0] + * /STAT_RX[1:0]) + * @param USBx USB peripheral instance register address. + * @param bChNum Endpoint Number. + * @retval status + */ +#define HCD_GET_CH_TX_STATUS USB_DRD_GET_CHEP_TX_STATUS +#define HCD_GET_CH_RX_STATUS USB_DRD_GET_CHEP_RX_STATUS +/** + * @brief Sets/clears CH_KIND bit in the Channel register. + * @param USBx USB peripheral instance register address. + * @param bChNum Endpoint Number. + * @retval None + */ +#define HCD_SET_CH_KIND USB_DRD_SET_CH_KIND +#define HCD_CLEAR_CH_KIND USB_DRD_CLEAR_CH_KIND +#define HCD_SET_BULK_CH_DBUF HCD_SET_CH_KIND +#define HCD_CLEAR_BULK_CH_DBUF HCD_CLEAR_CH_KIND + +/** + * @brief Clears bit ERR_RX in the Channel register + * @param USBx USB peripheral instance register address. + * @param bChNum Endpoint Number. + * @retval None + */ +#define HCD_CLEAR_RX_CH_ERR USB_DRD_CLEAR_CHEP_RX_ERR + +/** + * @brief Clears bit ERR_TX in the Channel register + * @param USBx USB peripheral instance register address. + * @param bChNum Endpoint Number. + * @retval None + */ +#define HCD_CLEAR_TX_CH_ERR USB_DRD_CLEAR_CHEP_TX_ERR +/** + * @brief Clears bit CTR_RX / CTR_TX in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bChNum Endpoint Number. + * @retval None + */ +#define HCD_CLEAR_RX_CH_CTR USB_DRD_CLEAR_RX_CHEP_CTR +#define HCD_CLEAR_TX_CH_CTR USB_DRD_CLEAR_TX_CHEP_CTR + +/** + * @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bChNum Endpoint Number. + * @retval None + */ +#define HCD_RX_DTOG USB_DRD_RX_DTOG +#define HCD_TX_DTOG USB_DRD_TX_DTOG +/** + * @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bChNum Endpoint Number. + * @retval None + */ +#define HCD_CLEAR_RX_DTOG USB_DRD_CLEAR_RX_DTOG +#define HCD_CLEAR_TX_DTOG USB_DRD_CLEAR_TX_DTOG + +/** + * @brief sets counter for the tx/rx buffer. + * @param USBx USB peripheral instance register address. + * @param bChNum Endpoint Number. + * @param wCount Counter value. + * @retval None + */ +#define HCD_SET_CH_TX_CNT USB_DRD_SET_CHEP_TX_CNT +#define HCD_SET_CH_RX_CNT USB_DRD_SET_CHEP_RX_CNT + +/** + * @brief gets counter of the tx buffer. + * @param USBx USB peripheral instance register address. + * @param bChNum channel Number. + * @retval Counter value + */ +#define HCD_GET_CH_TX_CNT USB_DRD_GET_CHEP_TX_CNT + +/** + * @brief gets counter of the rx buffer. + * @param Instance USB peripheral instance register address. + * @param bChNum channel Number. + * @retval Counter value + */ +__STATIC_INLINE uint16_t HCD_GET_CH_RX_CNT(HCD_TypeDef *Instance, uint16_t bChNum) +{ + uint32_t HostCoreSpeed; + uint32_t ep_reg = USB_DRD_GET_CHEP(Instance, bChNum); + __IO uint32_t count = 10U; + + /* Get Host core Speed */ + HostCoreSpeed = USB_GetHostSpeed(Instance); + + /* Count depends on device LS */ + if ((HostCoreSpeed == USB_DRD_SPEED_LS) || ((ep_reg & USB_CHEP_LSEP) == USB_CHEP_LSEP)) + { + count = (70U * (HAL_RCC_GetHCLKFreq() / 1000000U)) / 100U; + } + + if (count > 15U) + { + count = HCD_MAX(10U, (count - 15U)); + } + + /* WA: few cycles for RX PMA descriptor to update */ + while (count > 0U) + { + count--; + } + + return (uint16_t)USB_DRD_GET_CHEP_RX_CNT((Instance), (bChNum)); +} + +/** + * @brief Gets buffer 0/1 address of a double buffer endpoint. + * @param USBx USB peripheral instance register address. + * @param bChNum Endpoint Number. + * @param bDir endpoint dir EP_DBUF_OUT = OUT + * EP_DBUF_IN = IN + * @param wCount: Counter value + * @retval None + */ +#define HCD_SET_CH_DBUF0_CNT USB_DRD_SET_CHEP_DBUF0_CNT +#define HCD_SET_CH_DBUF1_CNT USB_DRD_SET_CHEP_DBUF1_CNT +#define HCD_SET_CH_DBUF_CNT USB_DRD_SET_CHEP_DBUF_CNT + + +/** + * @brief gets counter of the rx buffer0. + * @param Instance USB peripheral instance register address. + * @param bChNum channel Number. + * @retval Counter value + */ +__STATIC_INLINE uint16_t HCD_GET_CH_DBUF0_CNT(const HCD_TypeDef *Instance, uint16_t bChNum) +{ + UNUSED(Instance); + __IO uint32_t count = 10U; + + /* WA: few cycles for RX PMA descriptor to update */ + while (count > 0U) + { + count--; + } + + return (uint16_t)USB_DRD_GET_CHEP_DBUF0_CNT((Instance), (bChNum)); +} + +/** + * @brief gets counter of the rx buffer1. + * @param Instance USB peripheral instance register address. + * @param bChNum channel Number. + * @retval Counter value + */ +__STATIC_INLINE uint16_t HCD_GET_CH_DBUF1_CNT(const HCD_TypeDef *Instance, uint16_t bChNum) +{ + UNUSED(Instance); + __IO uint32_t count = 10U; + + /* WA: few cycles for RX PMA descriptor to update */ + while (count > 0U) + { + count--; + } + + return (uint16_t)USB_DRD_GET_CHEP_DBUF1_CNT((Instance), (bChNum)); +} +#endif /* defined (USB_DRD_FS) */ + +/** + * @} + */ +/* Private functions prototypes ----------------------------------------------*/ + +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +#endif /* defined (USB_OTG_HS) || defined (USB_DRD_FS) */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBAxx_HAL_HCD_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_hsem.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_hsem.h index c55dfa9be9..3e7bf52428 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_hsem.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_hsem.h @@ -179,6 +179,7 @@ void HAL_HSEM_IRQHandler(void); * @} */ +#if defined(HSEM_SECCFGR_SEC0) || defined(HSEM_PRIVCFGR_PRIV0) /** @addtogroup HSEM_Exported_Functions_Group4 * @brief HSEM Attributes functions. * @{ @@ -200,6 +201,7 @@ uint32_t HAL_HSEM_GetSemaphorePrivilege(void); /** * @} */ +#endif /* (HSEM_SECCFGR_SEC0) || (HSEM_PRIVCFGR_PRIV0) */ /** * @} diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_i2c_ex.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_i2c_ex.h index cc84e89e04..90f2f25058 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_i2c_ex.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_i2c_ex.h @@ -99,67 +99,67 @@ typedef struct /** @defgroup I2CEx_AutonomousMode_TriggerSelection I2C Extended Autonomous Mode Trigger Selection * @{ */ -#if defined(I2C1) -#define I2C_TRIG_GRP1 (0x10000000U) /*!< Trigger Group for I2C1 */ -#endif /* I2C1 */ +#if (defined(I2C1) || defined(I2C2) || defined(I2C4)) +#define I2C_TRIG_GRP1 (0x10000000U) /*!< Trigger Group for I2C1, I2C2, I2C4 */ +#endif /* I2C1, I2C2, I2C4 */ #define I2C_TRIG_GRP2 (0x20000000U) /*!< Trigger Group for I2C3 */ #if defined(I2C_TRIG_GRP1) #define I2C_GRP1_GPDMA_CH0_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x00000000U)) /*!< HW Trigger signal is GPDMA_CH0_TRG */ -#define I2C_GRP1_GPDMA_CH1_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x1U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP1_GPDMA_CH1_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x1UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is GPDMA_CH1_TRG */ -#define I2C_GRP1_GPDMA_CH2_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x2U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP1_GPDMA_CH2_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x2UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is GPDMA_CH2_TRG */ -#define I2C_GRP1_GPDMA_CH3_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x3U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP1_GPDMA_CH3_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x3UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is GPDMA_CH3_TRG */ -#define I2C_GRP1_EXTI5_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x4U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP1_EXTI5_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x4UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is EXTI5_TRG */ -#define I2C_GRP1_EXTI9_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x5U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP1_EXTI9_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x5UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is EXTI9_TRG */ -#define I2C_GRP1_LPTIM1_CH1_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x6U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP1_LPTIM1_CH1_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x6UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is LPTIM1_CH1_TRG */ -#define I2C_GRP1_LPTIM2_CH1_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x7U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP1_LPTIM2_CH1_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x7UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is LPTIM2_CH1_TRG */ #if defined(COMP1) -#define I2C_GRP1_COMP1_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x8U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP1_COMP1_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x8UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is COMP1_TRG */ #endif /* COMP1 */ #if defined(COMP2) -#define I2C_GRP1_COMP2_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x9U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP1_COMP2_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x9UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is COMP2_TRG */ #endif /* COMP2 */ -#define I2C_GRP1_RTC_ALRA_TRG (uint32_t)(I2C_TRIG_GRP1 | (0xAU << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP1_RTC_ALRA_TRG (uint32_t)(I2C_TRIG_GRP1 | (0xAUL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is RTC_ALRA_TRG */ -#define I2C_GRP1_RTC_WUT_TRG (uint32_t)(I2C_TRIG_GRP1 | (0xBU << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP1_RTC_WUT_TRG (uint32_t)(I2C_TRIG_GRP1 | (0xBUL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is RTC_WUT_TRG */ #endif /* I2C_TRIG_GRP1 */ #define I2C_GRP2_GPDMA_CH0_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x00000000U)) /*!< HW Trigger signal is GPDMA_CH0_TRG */ -#define I2C_GRP2_GPDMA_CH1_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x1U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP2_GPDMA_CH1_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x1UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is GPDMA_CH1_TRG */ -#define I2C_GRP2_GPDMA_CH2_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x2U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP2_GPDMA_CH2_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x2UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is GPDMA_CH2_TRG */ -#define I2C_GRP2_GPDMA_CH3_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x3U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP2_GPDMA_CH3_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x3UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is GPDMA_CH3_TRG */ -#define I2C_GRP2_EXTI5_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x4U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP2_EXTI5_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x4UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is EXTI5_TRG */ -#define I2C_GRP2_EXTI8_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x5U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP2_EXTI8_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x5UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is EXTI8_TRG */ -#define I2C_GRP2_LPTIM1_CH1_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x6U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP2_LPTIM1_CH1_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x6UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is LPTIM1_CH1_TRG */ #if defined(COMP1) -#define I2C_GRP2_COMP1_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x8U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP2_COMP1_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x8UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is COMP1_TRG */ #endif /* COMP1 */ #if defined(COMP2) -#define I2C_GRP2_COMP2_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x9U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP2_COMP2_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x9UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is COMP2_TRG */ #endif /* COMP2 */ -#define I2C_GRP2_RTC_ALRA_TRG (uint32_t)(I2C_TRIG_GRP2 | (0xAU << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP2_RTC_ALRA_TRG (uint32_t)(I2C_TRIG_GRP2 | (0xAUL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is RTC_ALRA_TRG */ -#define I2C_GRP2_RTC_WUT_TRG (uint32_t)(I2C_TRIG_GRP2 | (0xBU << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP2_RTC_WUT_TRG (uint32_t)(I2C_TRIG_GRP2 | (0xBUL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is RTC_WUT_TRG */ /** * @} diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_icache.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_icache.h index 83e18ee7dd..a39a60652e 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_icache.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_icache.h @@ -101,13 +101,13 @@ typedef struct /** @defgroup ICACHE_Region_Size Remapped Region size * @{ */ -#define ICACHE_REGIONSIZE_2MB 1U /*!< Region size 2MB */ -#define ICACHE_REGIONSIZE_4MB 2U /*!< Region size 4MB */ -#define ICACHE_REGIONSIZE_8MB 3U /*!< Region size 8MB */ -#define ICACHE_REGIONSIZE_16MB 4U /*!< Region size 16MB */ -#define ICACHE_REGIONSIZE_32MB 5U /*!< Region size 32MB */ -#define ICACHE_REGIONSIZE_64MB 6U /*!< Region size 64MB */ -#define ICACHE_REGIONSIZE_128MB 7U /*!< Region size 128MB */ +#define ICACHE_REGIONSIZE_2MB 1UL /*!< Region size 2MB */ +#define ICACHE_REGIONSIZE_4MB 2UL /*!< Region size 4MB */ +#define ICACHE_REGIONSIZE_8MB 3UL /*!< Region size 8MB */ +#define ICACHE_REGIONSIZE_16MB 4UL /*!< Region size 16MB */ +#define ICACHE_REGIONSIZE_32MB 5UL /*!< Region size 32MB */ +#define ICACHE_REGIONSIZE_64MB 6UL /*!< Region size 64MB */ +#define ICACHE_REGIONSIZE_128MB 7UL /*!< Region size 128MB */ /** * @} */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_irda_ex.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_irda_ex.h index 0419be8e2a..df64de2d42 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_irda_ex.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_irda_ex.h @@ -69,6 +69,78 @@ extern "C" { * @param __CLOCKSOURCE__ output variable. * @retval IRDA clocking source, written in __CLOCKSOURCE__. */ +#if defined(USART3) +#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK2: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ + case RCC_USART2CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART2CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART2CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART2CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + switch(__HAL_RCC_GET_USART3_SOURCE()) \ + { \ + case RCC_USART3CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART3CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART3CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART3CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) +#else #if defined(USART2) #define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ @@ -149,6 +221,7 @@ extern "C" { } \ } while(0U) #endif /* USART2 */ +#endif /* USART3 */ /** @brief Compute the mask to apply to retrieve the received data * according to the word length and to the parity bits activation. diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_pcd.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_pcd.h new file mode 100644 index 0000000000..30ed7cc90e --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_pcd.h @@ -0,0 +1,683 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_pcd.h + * @author MCD Application Team + * @brief Header file of PCD HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_HAL_PCD_H +#define STM32WBAxx_HAL_PCD_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_ll_usb.h" + +#if defined (USB_OTG_HS) || defined (USB_DRD_FS) + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @addtogroup PCD + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup PCD_Exported_Types PCD Exported Types + * @{ + */ + +/** + * @brief PCD State structure definition + */ +typedef enum +{ + HAL_PCD_STATE_RESET = 0x00, + HAL_PCD_STATE_READY = 0x01, + HAL_PCD_STATE_ERROR = 0x02, + HAL_PCD_STATE_BUSY = 0x03, + HAL_PCD_STATE_TIMEOUT = 0x04 +} PCD_StateTypeDef; + +/* Device LPM suspend state */ +typedef enum +{ + LPM_L0 = 0x00, /* on */ + LPM_L1 = 0x01, /* LPM L1 sleep */ + LPM_L2 = 0x02, /* suspend */ + LPM_L3 = 0x03, /* off */ +} PCD_LPM_StateTypeDef; + +typedef enum +{ + PCD_LPM_L0_ACTIVE = 0x00, /* on */ + PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */ +} PCD_LPM_MsgTypeDef; + +typedef enum +{ + PCD_BCD_ERROR = 0xFF, + PCD_BCD_CONTACT_DETECTION = 0xFE, + PCD_BCD_STD_DOWNSTREAM_PORT = 0xFD, + PCD_BCD_CHARGING_DOWNSTREAM_PORT = 0xFC, + PCD_BCD_DEDICATED_CHARGING_PORT = 0xFB, + PCD_BCD_DISCOVERY_COMPLETED = 0x00, + +} PCD_BCD_MsgTypeDef; + +#if defined (USB_OTG_HS) +typedef USB_OTG_GlobalTypeDef PCD_TypeDef; +typedef USB_OTG_CfgTypeDef PCD_InitTypeDef; +typedef USB_OTG_EPTypeDef PCD_EPTypeDef; +#endif /* defined (USB_OTG_HS) */ +#if defined (USB_DRD_FS) +typedef USB_DRD_TypeDef PCD_TypeDef; +typedef USB_DRD_CfgTypeDef PCD_InitTypeDef; +typedef USB_DRD_EPTypeDef PCD_EPTypeDef; +#endif /* defined (USB_DRD_FS) */ + +/** + * @brief PCD Handle Structure definition + */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +typedef struct __PCD_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +{ + PCD_TypeDef *Instance; /*!< Register base address */ + PCD_InitTypeDef Init; /*!< PCD required parameters */ + __IO uint8_t USB_Address; /*!< USB Address */ +#if defined (USB_OTG_HS) + PCD_EPTypeDef IN_ep[16]; /*!< IN endpoint parameters */ + PCD_EPTypeDef OUT_ep[16]; /*!< OUT endpoint parameters */ +#endif /* defined (USB_OTG_HS) */ +#if defined (USB_DRD_FS) + PCD_EPTypeDef IN_ep[8]; /*!< IN endpoint parameters */ + PCD_EPTypeDef OUT_ep[8]; /*!< OUT endpoint parameters */ +#endif /* defined (USB_DRD_FS) */ + HAL_LockTypeDef Lock; /*!< PCD peripheral status */ + __IO PCD_StateTypeDef State; /*!< PCD communication state */ + __IO uint32_t ErrorCode; /*!< PCD Error code */ + uint32_t Setup[12]; /*!< Setup packet buffer */ + PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */ + uint32_t BESL; + uint32_t FrameNumber; /*!< Store Current Frame number */ + + + uint32_t lpm_active; /*!< Enable or disable the Link Power Management . + This parameter can be set to ENABLE or DISABLE */ + + uint32_t battery_charging_active; /*!< Enable or disable Battery charging. + This parameter can be set to ENABLE or DISABLE */ + void *pData; /*!< Pointer to upper stack Handler */ + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + void (* SOFCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD SOF callback */ + void (* SetupStageCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Setup Stage callback */ + void (* ResetCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Reset callback */ + void (* SuspendCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Suspend callback */ + void (* ResumeCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Resume callback */ + void (* ConnectCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Connect callback */ + void (* DisconnectCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Disconnect callback */ + + void (* DataOutStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD Data OUT Stage callback */ + void (* DataInStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD Data IN Stage callback */ + void (* ISOOUTIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD ISO OUT Incomplete callback */ + void (* ISOINIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD ISO IN Incomplete callback */ + void (* BCDCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg); /*!< USB OTG PCD BCD callback */ + void (* LPMCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg); /*!< USB OTG PCD LPM callback */ + + void (* MspInitCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Msp Init callback */ + void (* MspDeInitCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Msp DeInit callback */ +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +} PCD_HandleTypeDef; + +/** + * @} + */ + +/* Include PCD HAL Extended module */ +#include "stm32wbaxx_hal_pcd_ex.h" + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup PCD_Exported_Constants PCD Exported Constants + * @{ + */ + +/** @defgroup PCD_Speed PCD Speed + * @{ + */ +#define PCD_SPEED_HIGH USBD_HS_SPEED +#define PCD_SPEED_HIGH_IN_FULL USBD_HSINFS_SPEED +#define PCD_SPEED_FULL USBD_FS_SPEED +/** + * @} + */ + +/** @defgroup PCD_PHY_Module PCD PHY Module + * @{ + */ +#define PCD_PHY_ULPI 1U +#define PCD_PHY_EMBEDDED 2U +#define PCD_PHY_UTMI 3U +/** + * @} + */ + +/** @defgroup PCD_Error_Code_definition PCD Error Code definition + * @brief PCD Error Code definition + * @{ + */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +#define HAL_PCD_ERROR_INVALID_CALLBACK (0x00000010U) /*!< Invalid Callback error */ +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup PCD_Exported_Macros PCD Exported Macros + * @brief macros to handle interrupts and specific clock configurations + * @{ + */ +#define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance) +#define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance) + +#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) \ + ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__)) + +#if defined (USB_OTG_HS) +#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) &= (__INTERRUPT__)) +#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U) + +#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) \ + *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= ~(USB_OTG_PCGCCTL_STOPCLK) + +#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) \ + *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK + +#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) \ + ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U) +#endif /* defined (USB_OTG_HS) */ + +#if defined (USB_DRD_FS) +#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR)\ + &= (uint16_t)(~(__INTERRUPT__))) +#endif /* defined (USB_DRD_FS) */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup PCD_Exported_Functions PCD Exported Functions + * @{ + */ + +/* Initialization/de-initialization functions ********************************/ +/** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd); +void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd); +void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd); + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +/** @defgroup HAL_PCD_Callback_ID_enumeration_definition HAL USB OTG PCD Callback ID enumeration definition + * @brief HAL USB OTG PCD Callback ID enumeration definition + * @{ + */ +typedef enum +{ + HAL_PCD_SOF_CB_ID = 0x01, /*!< USB PCD SOF callback ID */ + HAL_PCD_SETUPSTAGE_CB_ID = 0x02, /*!< USB PCD Setup Stage callback ID */ + HAL_PCD_RESET_CB_ID = 0x03, /*!< USB PCD Reset callback ID */ + HAL_PCD_SUSPEND_CB_ID = 0x04, /*!< USB PCD Suspend callback ID */ + HAL_PCD_RESUME_CB_ID = 0x05, /*!< USB PCD Resume callback ID */ + HAL_PCD_CONNECT_CB_ID = 0x06, /*!< USB PCD Connect callback ID */ + HAL_PCD_DISCONNECT_CB_ID = 0x07, /*!< USB PCD Disconnect callback ID */ + + HAL_PCD_MSPINIT_CB_ID = 0x08, /*!< USB PCD MspInit callback ID */ + HAL_PCD_MSPDEINIT_CB_ID = 0x09 /*!< USB PCD MspDeInit callback ID */ + +} HAL_PCD_CallbackIDTypeDef; +/** + * @} + */ + +/** @defgroup HAL_PCD_Callback_pointer_definition HAL USB OTG PCD Callback pointer definition + * @brief HAL USB OTG PCD Callback pointer definition + * @{ + */ + +typedef void (*pPCD_CallbackTypeDef)(PCD_HandleTypeDef *hpcd); /*!< pointer to a common USB OTG PCD callback function */ +typedef void (*pPCD_DataOutStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD Data OUT Stage callback */ +typedef void (*pPCD_DataInStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD Data IN Stage callback */ +typedef void (*pPCD_IsoOutIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD ISO OUT Incomplete callback */ +typedef void (*pPCD_IsoInIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD ISO IN Incomplete callback */ +typedef void (*pPCD_LpmCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg); /*!< pointer to USB OTG PCD LPM callback */ +typedef void (*pPCD_BcdCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg); /*!< pointer to USB OTG PCD BCD callback */ + +/** + * @} + */ + +HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, + pPCD_CallbackTypeDef pCallback); + +HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, + pPCD_DataOutStageCallbackTypeDef pCallback); + +HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd); + +HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, + pPCD_DataInStageCallbackTypeDef pCallback); + +HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd); + +HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, + pPCD_IsoOutIncpltCallbackTypeDef pCallback); + +HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd); + +HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, + pPCD_IsoInIncpltCallbackTypeDef pCallback); + +HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd); + +HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd); + +HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +/** + * @} + */ + +/* I/O operation functions ***************************************************/ +/* Non-Blocking mode: Interrupt */ +/** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation functions + * @{ + */ +HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd); +void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd); + +void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd); + +void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); +void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); +void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); +void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); +/** + * @} + */ + +/* Peripheral Control functions **********************************************/ +/** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions + * @{ + */ +HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address); +HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type); +HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); +HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); +HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); +#if defined (USB_OTG_HS) +HAL_StatusTypeDef HAL_PCD_SetTestMode(const PCD_HandleTypeDef *hpcd, uint8_t testmode); +#endif /* defined (USB_OTG_HS) */ + +uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef const *hpcd, uint8_t ep_addr); +/** + * @} + */ + +/* Peripheral State functions ************************************************/ +/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions + * @{ + */ +PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd); +/** + * @} + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup PCD_Private_Constants PCD Private Constants + * @{ + */ +#if defined (USB_DRD_FS) +/** @defgroup PCD_EP0_MPS PCD EP0 MPS + * @{ + */ +#define PCD_EP0MPS_64 EP_MPS_64 +#define PCD_EP0MPS_32 EP_MPS_32 +#define PCD_EP0MPS_16 EP_MPS_16 +#define PCD_EP0MPS_08 EP_MPS_8 +/** + * @} + */ + +/** @defgroup PCD_ENDP PCD ENDP + * @{ + */ +#define PCD_ENDP0 0U +#define PCD_ENDP1 1U +#define PCD_ENDP2 2U +#define PCD_ENDP3 3U +#define PCD_ENDP4 4U +#define PCD_ENDP5 5U +#define PCD_ENDP6 6U +#define PCD_ENDP7 7U +/** + * @} + */ + +/** @defgroup PCD_ENDP_Kind PCD Endpoint Kind + * @{ + */ +#define PCD_SNG_BUF 0U +#define PCD_DBL_BUF 1U +/** + * @} + */ +#endif /* defined (USB_DRD_FS) */ +/** + * @} + */ + +#if defined (USB_OTG_HS) +#ifndef USB_OTG_DOEPINT_OTEPSPR +#define USB_OTG_DOEPINT_OTEPSPR (0x1UL << 5) /*!< Status Phase Received interrupt */ +#endif /* defined USB_OTG_DOEPINT_OTEPSPR */ + +#ifndef USB_OTG_DOEPMSK_OTEPSPRM +#define USB_OTG_DOEPMSK_OTEPSPRM (0x1UL << 5) /*!< Setup Packet Received interrupt mask */ +#endif /* defined USB_OTG_DOEPMSK_OTEPSPRM */ + +#ifndef USB_OTG_DOEPINT_NAK +#define USB_OTG_DOEPINT_NAK (0x1UL << 13) /*!< NAK interrupt */ +#endif /* defined USB_OTG_DOEPINT_NAK */ + +#ifndef USB_OTG_DOEPMSK_NAKM +#define USB_OTG_DOEPMSK_NAKM (0x1UL << 13) /*!< OUT Packet NAK interrupt mask */ +#endif /* defined USB_OTG_DOEPMSK_NAKM */ + +#ifndef USB_OTG_DOEPINT_STPKTRX +#define USB_OTG_DOEPINT_STPKTRX (0x1UL << 15) /*!< Setup Packet Received interrupt */ +#endif /* defined USB_OTG_DOEPINT_STPKTRX */ + +#ifndef USB_OTG_DOEPMSK_NYETM +#define USB_OTG_DOEPMSK_NYETM (0x1UL << 14) /*!< Setup Packet Received interrupt mask */ +#endif /* defined USB_OTG_DOEPMSK_NYETM */ +#endif /* defined (USB_OTG_HS) */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup PCD_Private_Macros PCD Private Macros + * @{ + */ +#if defined (USB_DRD_FS) +/* PMA RX counter */ +#ifndef PCD_RX_PMA_CNT +#define PCD_RX_PMA_CNT 10U +#endif /* PCD_RX_PMA_CNT */ + +/* SetENDPOINT */ +#define PCD_SET_ENDPOINT USB_DRD_SET_CHEP + +/* GetENDPOINT Register value*/ +#define PCD_GET_ENDPOINT USB_DRD_GET_CHEP + + +/** + * @brief free buffer used from the application realizing it to the line + * toggles bit SW_BUF in the double buffered endpoint register + * @param USBx USB device. + * @param bEpNum, bDir + * @retval None + */ +#define PCD_FREE_USER_BUFFER USB_DRD_FREE_USER_BUFFER + +/** + * @brief sets the status for tx transfer (bits STAT_TX[1:0]). + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wState new state + * @retval None + */ +#define PCD_SET_EP_TX_STATUS USB_DRD_SET_CHEP_TX_STATUS + +/** + * @brief sets the status for rx transfer (bits STAT_TX[1:0]) + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wState new state + * @retval None + */ +#define PCD_SET_EP_RX_STATUS USB_DRD_SET_CHEP_RX_STATUS + +/** + * @brief Sets/clears directly EP_KIND bit in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_SET_EP_KIND USB_DRD_SET_CHEP_KIND +#define PCD_CLEAR_EP_KIND USB_DRD_CLEAR_CHEP_KIND +#define PCD_SET_BULK_EP_DBUF PCD_SET_EP_KIND +#define PCD_CLEAR_BULK_EP_DBUF PCD_CLEAR_EP_KIND + +/** + * @brief Sets/clears directly STATUS_OUT bit in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_SET_OUT_STATUS USB_DRD_SET_CHEP_KIND +#define PCD_CLEAR_OUT_STATUS USB_DRD_CLEAR_CHEP_KIND + +/** + * @brief Clears bit CTR_RX / CTR_TX in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_CLEAR_RX_EP_CTR USB_DRD_CLEAR_RX_CHEP_CTR +#define PCD_CLEAR_TX_EP_CTR USB_DRD_CLEAR_TX_CHEP_CTR +/** + * @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_RX_DTOG USB_DRD_RX_DTOG +#define PCD_TX_DTOG USB_DRD_TX_DTOG +/** + * @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_CLEAR_RX_DTOG USB_DRD_CLEAR_RX_DTOG +#define PCD_CLEAR_TX_DTOG USB_DRD_CLEAR_TX_DTOG + +/** + * @brief Sets address in an endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param bAddr Address. + * @retval None + */ +#define PCD_SET_EP_ADDRESS USB_DRD_SET_CHEP_ADDRESS + +/** + * @brief sets address of the tx/rx buffer. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wAddr address to be set (must be word aligned). + * @retval None + */ +#define PCD_SET_EP_TX_ADDRESS USB_DRD_SET_CHEP_TX_ADDRESS +#define PCD_SET_EP_RX_ADDRESS USB_DRD_SET_CHEP_RX_ADDRESS + +/** + * @brief sets counter for the tx/rx buffer. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wCount Counter value. + * @retval None + */ +#define PCD_SET_EP_TX_CNT USB_DRD_SET_CHEP_TX_CNT +#define PCD_SET_EP_RX_CNT USB_DRD_SET_CHEP_RX_CNT + +/** + * @brief gets counter of the tx buffer. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval Counter value + */ +#define PCD_GET_EP_TX_CNT USB_DRD_GET_CHEP_TX_CNT + +/** + * @brief gets counter of the rx buffer. + * @param Instance USB peripheral instance register address. + * @param bEpNum channel Number. + * @retval Counter value + */ +__STATIC_INLINE uint16_t PCD_GET_EP_RX_CNT(const PCD_TypeDef *Instance, uint16_t bEpNum) +{ + UNUSED(Instance); + __IO uint32_t count = PCD_RX_PMA_CNT; + + /* WA: few cycles for RX PMA descriptor to update */ + while (count > 0U) + { + count--; + } + + return (uint16_t)USB_DRD_GET_CHEP_RX_CNT((Instance), (bEpNum)); +} + +/** + * @brief Sets addresses in a double buffer endpoint. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wBuf0Addr: buffer 0 address. + * @param wBuf1Addr = buffer 1 address. + * @retval None + */ +#define PCD_SET_EP_DBUF_ADDR USB_DRD_SET_CHEP_DBUF_ADDR + +/** + * @brief Gets buffer 0/1 address of a double buffer endpoint. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param bDir endpoint dir EP_DBUF_OUT = OUT + * EP_DBUF_IN = IN + * @param wCount: Counter value + * @retval None + */ +#define PCD_SET_EP_DBUF0_CNT USB_DRD_SET_CHEP_DBUF0_CNT +#define PCD_SET_EP_DBUF1_CNT USB_DRD_SET_CHEP_DBUF1_CNT +#define PCD_SET_EP_DBUF_CNT USB_DRD_SET_CHEP_DBUF_CNT + +/** + * @brief gets counter of the rx buffer0. + * @param Instance USB peripheral instance register address. + * @param bEpNum channel Number. + * @retval Counter value + */ +__STATIC_INLINE uint16_t PCD_GET_EP_DBUF0_CNT(const PCD_TypeDef *Instance, uint16_t bEpNum) +{ + UNUSED(Instance); + __IO uint32_t count = PCD_RX_PMA_CNT; + + /* WA: few cycles for RX PMA descriptor to update */ + while (count > 0U) + { + count--; + } + + return (uint16_t)USB_DRD_GET_CHEP_DBUF0_CNT((Instance), (bEpNum)); +} + +/** + * @brief gets counter of the rx buffer1. + * @param Instance USB peripheral instance register address. + * @param bEpNum channel Number. + * @retval Counter value + */ +__STATIC_INLINE uint16_t PCD_GET_EP_DBUF1_CNT(const PCD_TypeDef *Instance, uint16_t bEpNum) +{ + UNUSED(Instance); + __IO uint32_t count = PCD_RX_PMA_CNT; + + /* WA: few cycles for RX PMA descriptor to update */ + while (count > 0U) + { + count--; + } + + return (uint16_t)USB_DRD_GET_CHEP_DBUF1_CNT((Instance), (bEpNum)); +} +#endif /* defined (USB_DRD_FS) */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* defined (USB_OTG_HS) || defined (USB_DRD_FS) */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBAxx_HAL_PCD_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_pcd_ex.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_pcd_ex.h new file mode 100644 index 0000000000..aeddde2c07 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_pcd_ex.h @@ -0,0 +1,91 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_pcd_ex.h + * @author MCD Application Team + * @brief Header file of PCD HAL Extension module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_HAL_PCD_EX_H +#define STM32WBAxx_HAL_PCD_EX_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal_def.h" + +#if defined (USB_OTG_HS) || defined (USB_DRD_FS) +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @addtogroup PCDEx + * @{ + */ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macros -----------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions + * @{ + */ +/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions + * @{ + */ +#if defined (USB_OTG_HS) +HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size); +HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size); +#endif /* defined (USB_OTG_HS) */ + +#if defined (USB_DRD_FS) +HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr, + uint16_t ep_kind, uint32_t pmaadress); +#endif /* defined (USB_DRD_FS) */ + +HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd); + + +HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd); +void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd); + +void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg); +void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* defined (USB_OTG_HS) || defined (USB_DRD_FS) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + + +#endif /* STM32WBAxx_HAL_PCD_EX_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_pwr.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_pwr.h index f501d7233d..afbd4c6811 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_pwr.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_pwr.h @@ -107,6 +107,12 @@ typedef struct */ #define PWR_LOWPOWERMODE_STOP0 (0x00000000U) /*!< Stop 0: stop mode with main regulator */ #define PWR_LOWPOWERMODE_STOP1 (PWR_CR1_LPMS_0) /*!< Stop 1: stop mode with low power regulator */ +#if defined(PWR_STOP2_SUPPORT) +#define PWR_LOWPOWERMODE_STOP2 (PWR_CR1_LPMS_1) /*!< Stop 2: stop mode with low power regulator */ +#endif /* defined(PWR_STOP2_SUPPORT) */ +#if defined(PWR_STOP3_SUPPORT) +#define PWR_LOWPOWERMODE_STOP3 (PWR_CR1_LPMS_1 | PWR_CR1_LPMS_0) /*!< Stop 3: stop mode with low power regulator */ +#endif /* defined(PWR_STOP3_SUPPORT) */ #define PWR_LOWPOWERMODE_STANDBY (PWR_CR1_LPMS_2) /*!< Standby mode */ /** * @} @@ -145,6 +151,13 @@ typedef struct #if defined(PWR_RADIOSCR_REGPARDYV11) #define PWR_FLAG_REGPARDYV11 (8U) /*!< Ready bit for VDDHPA voltage level when selecting VDD11 input */ #endif /* defined(PWR_RADIOSCR_REGPARDYV11) */ +#if defined(PWR_STOP2_SUPPORT) +#define PWR_FLAG_STOP2F (9U) /*!< Stop2 flag */ +#ifndef PWR_STOP3_SUPPORT +#define PWR_FLAG_VDD11USBRDY (10U) /*!< USB OTG_HS VDD11USB ready flag */ +#define PWR_FLAG_USBBOOSTRDY (11U) /*!< USB OTG_HS power booster ready flag */ +#endif +#endif /* defined(PWR_STOP2_SUPPORT) */ /** * @} */ @@ -173,7 +186,7 @@ typedef struct * @{ */ #define PWR_WAKEUP_PIN1_HIGH_0 (PWR_WUCR1_WUPEN1 | PWR_WAKEUP1_SOURCE_SELECTION_0) /*!< PA0 : Wakeup pin 1 (high polarity) */ -#if defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) || defined(STM32WBA5Mxx) +#if defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) || defined(STM32WBA5Mxx) || defined(PWR_STOP2_SUPPORT) #define PWR_WAKEUP_PIN1_HIGH_1 (PWR_WUCR1_WUPEN1 | PWR_WAKEUP1_SOURCE_SELECTION_1) /*!< PB2 : Wakeup pin 1 (high polarity) */ #endif /* defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) || defined(STM32WBA5Mxx) */ @@ -183,12 +196,12 @@ typedef struct #endif /* defined(PWR_WUCR1_WUPEN2) */ #define PWR_WAKEUP_PIN3_HIGH_1 (PWR_WUCR1_WUPEN3 | PWR_WAKEUP3_SOURCE_SELECTION_1) /*!< PA1 : Wakeup pin 3 (high polarity) */ -#if defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) || defined(STM32WBA5Mxx) +#if defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) || defined(STM32WBA5Mxx) || defined(PWR_STOP2_SUPPORT) #define PWR_WAKEUP_PIN3_HIGH_2 (PWR_WUCR1_WUPEN3 | PWR_WAKEUP3_SOURCE_SELECTION_2) /*!< PB6 : Wakeup pin 3 (high polarity) */ #endif /* defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) || defined(STM32WBA5Mxx) */ #define PWR_WAKEUP_PIN4_HIGH_0 (PWR_WUCR1_WUPEN4 | PWR_WAKEUP4_SOURCE_SELECTION_0) /*!< PA2 : Wakeup pin 4 (high polarity) */ -#if defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) || defined(STM32WBA5Mxx) +#if defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) || defined(STM32WBA5Mxx) || defined(PWR_STOP2_SUPPORT) #define PWR_WAKEUP_PIN4_HIGH_1 (PWR_WUCR1_WUPEN4 | PWR_WAKEUP4_SOURCE_SELECTION_1) /*!< PB1 : Wakeup pin 4 (high polarity) */ #endif /* defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) || defined(STM32WBA5Mxx) */ @@ -201,7 +214,7 @@ typedef struct #define PWR_WAKEUP_PIN6_HIGH_1 (PWR_WUCR1_WUPEN6 | PWR_WAKEUP6_SOURCE_SELECTION_1) /*!< PA5 : Wakeup pin 6 (high polarity) */ #define PWR_WAKEUP_PIN6_HIGH_3 (PWR_WUCR1_WUPEN6 | PWR_WAKEUP6_SOURCE_SELECTION_3) /*!< RTC : Wakeup pin 6 (high polarity) */ -#if defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) || defined(STM32WBA5Mxx) +#if defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) || defined(STM32WBA5Mxx) || defined(PWR_STOP2_SUPPORT) #define PWR_WAKEUP_PIN7_HIGH_0 (PWR_WUCR1_WUPEN7 | PWR_WAKEUP7_SOURCE_SELECTION_0) /*!< PB14 : Wakeup pin 7 (high polarity) */ #endif /* defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) || defined(STM32WBA5Mxx) */ #define PWR_WAKEUP_PIN7_HIGH_1 (PWR_WUCR1_WUPEN7 | PWR_WAKEUP7_SOURCE_SELECTION_1) /*!< PA6 : Wakeup pin 7 (high polarity) */ @@ -218,7 +231,7 @@ typedef struct * @{ */ #define PWR_WAKEUP_PIN1_LOW_0 (PWR_WUCR1_WUPEN1 | PWR_WAKEUP1_POLARITY_LOW | PWR_WAKEUP1_SOURCE_SELECTION_0) /*!< PA0 : Wakeup pin 1 (low polarity) */ -#if defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) || defined(STM32WBA5Mxx) +#if defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) || defined(STM32WBA5Mxx) || defined(PWR_STOP2_SUPPORT) #define PWR_WAKEUP_PIN1_LOW_1 (PWR_WUCR1_WUPEN1 | PWR_WAKEUP1_POLARITY_LOW | PWR_WAKEUP1_SOURCE_SELECTION_1) /*!< PB2 : Wakeup pin 1 (low polarity) */ #endif /* defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) || defined(STM32WBA5Mxx) */ @@ -228,12 +241,12 @@ typedef struct #endif /* defined(PWR_WUCR1_WUPEN2) */ #define PWR_WAKEUP_PIN3_LOW_1 (PWR_WUCR1_WUPEN3 | PWR_WAKEUP3_POLARITY_LOW | PWR_WAKEUP3_SOURCE_SELECTION_1) /*!< PA1 : Wakeup pin 3 (low polarity) */ -#if defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) || defined(STM32WBA5Mxx) +#if defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) || defined(STM32WBA5Mxx) || defined(PWR_STOP2_SUPPORT) #define PWR_WAKEUP_PIN3_LOW_2 (PWR_WUCR1_WUPEN3 | PWR_WAKEUP3_POLARITY_LOW | PWR_WAKEUP3_SOURCE_SELECTION_2) /*!< PB6 : Wakeup pin 3 (low polarity) */ #endif /* defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) || defined(STM32WBA5Mxx) */ #define PWR_WAKEUP_PIN4_LOW_0 (PWR_WUCR1_WUPEN4 | PWR_WAKEUP4_POLARITY_LOW | PWR_WAKEUP4_SOURCE_SELECTION_0) /*!< PA2 : Wakeup pin 4 (low polarity) */ -#if defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) || defined(STM32WBA5Mxx) +#if defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) || defined(STM32WBA5Mxx) || defined(PWR_STOP2_SUPPORT) #define PWR_WAKEUP_PIN4_LOW_1 (PWR_WUCR1_WUPEN4 | PWR_WAKEUP4_POLARITY_LOW | PWR_WAKEUP4_SOURCE_SELECTION_1) /*!< PB1 : Wakeup pin 4 (low polarity) */ #endif /* defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) || defined(STM32WBA5Mxx) */ @@ -246,7 +259,7 @@ typedef struct #define PWR_WAKEUP_PIN6_LOW_1 (PWR_WUCR1_WUPEN6 | PWR_WAKEUP6_POLARITY_LOW | PWR_WAKEUP6_SOURCE_SELECTION_1) /*!< PA5 : Wakeup pin 6 (low polarity) */ #define PWR_WAKEUP_PIN6_LOW_3 (PWR_WUCR1_WUPEN6 | PWR_WAKEUP6_POLARITY_LOW | PWR_WAKEUP6_SOURCE_SELECTION_3) /*!< RTC : Wakeup pin 6 (low polarity) */ -#if defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) || defined(STM32WBA5Mxx) +#if defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) || defined(STM32WBA5Mxx) || defined(PWR_STOP2_SUPPORT) #define PWR_WAKEUP_PIN7_LOW_0 (PWR_WUCR1_WUPEN7 | PWR_WAKEUP7_POLARITY_LOW | PWR_WAKEUP7_SOURCE_SELECTION_0) /*!< PB14 : Wakeup pin 7 (low polarity) */ #endif /* defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) || defined(STM32WBA5Mxx) */ #define PWR_WAKEUP_PIN7_LOW_1 (PWR_WUCR1_WUPEN7 | PWR_WAKEUP7_POLARITY_LOW | PWR_WAKEUP7_SOURCE_SELECTION_1) /*!< PA6 : Wakeup pin 7 (low polarity) */ @@ -352,6 +365,14 @@ typedef struct * Indicates that the Vcore level at or above VOS selected level. * @arg @ref PWR_FLAG_STOPF : Stop flag. * Indicates that the device was resumed from Stop mode. +#if defined(PWR_STOP2_SUPPORT) + * @arg @ref PWR_FLAG_STOP2F : Stop 2 flag. + * Indicates that the device was resumed from Stop 2 mode. + * @arg @ref PWR_FLAG_VDD11USBRDY : USB OTG_HS VDD11USB ready flag. + * Indicates that the USB OTG_HS VDD11 is ready. + * @arg @ref PWR_FLAG_USBBOOSTRDY : USB OTG_HS power booster ready flag. + * Indicates that the USB OTG_HS power booster is ready. +#endif * @arg @ref PWR_FLAG_SBF : Standby flag. * Indicates that the device was resumed from Standby mode. * @arg @ref PWR_FLAG_ACTVOSRDY : Currently applied VOS ready flag. @@ -376,8 +397,10 @@ typedef struct * Indicates that a wakeup event was received from the WKUP line 3. * @arg @ref PWR_WAKEUP_FLAG4 : Wakeup flag 4. * Indicates that a wakeup event was received from the WKUP line 4. +#if !defined(PWR_STOP3_SUPPORT) * @arg @ref PWR_WAKEUP_FLAG5 : Wakeup flag 5. * Indicates that a wakeup event was received from the WKUP line 5. +#endif * @arg @ref PWR_WAKEUP_FLAG6 : Wakeup flag 6. * Indicates that a wakeup event was received from the WKUP line 6. * @arg @ref PWR_WAKEUP_FLAG7 : Wakeup flag 7. @@ -387,6 +410,174 @@ typedef struct * (*) Feature not available on all devices of the family * @retval The state of __FLAG__ (TRUE or FALSE). */ +#if defined(PWR_STOP2_SUPPORT) && defined(USB_OTG_HS) && defined(PWR_FLAG_REGS) +#define __HAL_PWR_GET_FLAG(__FLAG__)( \ + ((__FLAG__) == PWR_FLAG_VOSRDY) ? (READ_BIT(PWR->VOSR, PWR_VOSR_VOSRDY)== \ + PWR_VOSR_VOSRDY) : \ + ((__FLAG__) == PWR_FLAG_VDD11USBRDY) ? (READ_BIT(PWR->VOSR, PWR_VOSR_VDD11USBRDY)== \ + PWR_VOSR_VDD11USBRDY): \ + ((__FLAG__) == PWR_FLAG_USBBOOSTRDY) ? (READ_BIT(PWR->VOSR, PWR_VOSR_USBBOOSTRDY)== \ + PWR_VOSR_USBBOOSTRDY): \ + ((__FLAG__) == PWR_FLAG_STOPF) ? (READ_BIT(PWR->SR, PWR_SR_STOPF)== \ + PWR_SR_STOPF) : \ + ((__FLAG__) == PWR_FLAG_STOP2F) ? (READ_BIT(PWR->SR, PWR_SR_STOP2F)== \ + PWR_SR_STOP2F) : \ + ((__FLAG__) == PWR_FLAG_SBF) ? (READ_BIT(PWR->SR, PWR_SR_SBF)== \ + PWR_SR_SBF) : \ + ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ?(READ_BIT(PWR->SVMSR, PWR_SVMSR_ACTVOSRDY)== \ + PWR_SVMSR_ACTVOSRDY): \ + ((__FLAG__) == PWR_FLAG_PVDO) ?(READ_BIT(PWR->SVMSR, PWR_SVMSR_PVDO)== \ + PWR_SVMSR_PVDO) : \ + ((__FLAG__) == PWR_FLAG_REGS) ?(READ_BIT(PWR->SVMSR, PWR_SVMSR_REGS)== \ + PWR_SVMSR_REGS) : \ + ((__FLAG__) == PWR_FLAG_REGPARDYVDDRFPA) ?(READ_BIT(PWR->RADIOSCR, PWR_RADIOSCR_REGPARDYVDDRFPA)== \ + PWR_RADIOSCR_REGPARDYVDDRFPA) : \ + ((__FLAG__) == PWR_FLAG_REGPARDYV11) ?(READ_BIT(PWR->RADIOSCR, PWR_RADIOSCR_REGPARDYV11)== \ + PWR_RADIOSCR_REGPARDYV11) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG1) ?(READ_BIT(PWR->WUSR, PWR_WUSR_WUF1) == \ + PWR_WUSR_WUF1) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG2) ?(READ_BIT(PWR->WUSR, PWR_WUSR_WUF2) == \ + PWR_WUSR_WUF2) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG3) ?(READ_BIT(PWR->WUSR, PWR_WUSR_WUF3) == \ + PWR_WUSR_WUF3) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG4) ?(READ_BIT(PWR->WUSR, PWR_WUSR_WUF4) == \ + PWR_WUSR_WUF4) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG5) ?(READ_BIT(PWR->WUSR, PWR_WUSR_WUF5) == \ + PWR_WUSR_WUF5) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG6) ?(READ_BIT(PWR->WUSR, PWR_WUSR_WUF6) == \ + PWR_WUSR_WUF6) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG7) ?(READ_BIT(PWR->WUSR, PWR_WUSR_WUF7) == \ + PWR_WUSR_WUF7) : \ + (READ_BIT(PWR->WUSR, PWR_WUSR_WUF8) == PWR_WUSR_WUF8)) +#elif defined(PWR_STOP2_SUPPORT) && defined(USB_OTG_HS) +#define __HAL_PWR_GET_FLAG(__FLAG__)( \ + ((__FLAG__) == PWR_FLAG_VOSRDY) ? (READ_BIT(PWR->VOSR, PWR_VOSR_VOSRDY)== \ + PWR_VOSR_VOSRDY) : \ + ((__FLAG__) == PWR_FLAG_VDD11USBRDY) ? (READ_BIT(PWR->VOSR, PWR_VOSR_VDD11USBRDY)== \ + PWR_VOSR_VDD11USBRDY): \ + ((__FLAG__) == PWR_FLAG_USBBOOSTRDY) ? (READ_BIT(PWR->VOSR, PWR_VOSR_USBBOOSTRDY)== \ + PWR_VOSR_USBBOOSTRDY): \ + ((__FLAG__) == PWR_FLAG_STOPF) ? (READ_BIT(PWR->SR, PWR_SR_STOPF)== \ + PWR_SR_STOPF) : \ + ((__FLAG__) == PWR_FLAG_STOP2F) ? (READ_BIT(PWR->SR, PWR_SR_STOP2F)== \ + PWR_SR_STOP2F) : \ + ((__FLAG__) == PWR_FLAG_SBF) ? (READ_BIT(PWR->SR, PWR_SR_SBF)== \ + PWR_SR_SBF) : \ + ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ?(READ_BIT(PWR->SVMSR, PWR_SVMSR_ACTVOSRDY)== \ + PWR_SVMSR_ACTVOSRDY): \ + ((__FLAG__) == PWR_FLAG_PVDO) ?(READ_BIT(PWR->SVMSR, PWR_SVMSR_PVDO)== \ + PWR_SVMSR_PVDO) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG1) ?(READ_BIT(PWR->WUSR, PWR_WUSR_WUF1) == \ + PWR_WUSR_WUF1) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG2) ?(READ_BIT(PWR->WUSR, PWR_WUSR_WUF2) == \ + PWR_WUSR_WUF2) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG3) ?(READ_BIT(PWR->WUSR, PWR_WUSR_WUF3) == \ + PWR_WUSR_WUF3) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG4) ?(READ_BIT(PWR->WUSR, PWR_WUSR_WUF4) == \ + PWR_WUSR_WUF4) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG5) ?(READ_BIT(PWR->WUSR, PWR_WUSR_WUF5) == \ + PWR_WUSR_WUF5) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG6) ?(READ_BIT(PWR->WUSR, PWR_WUSR_WUF6) == \ + PWR_WUSR_WUF6) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG7) ?(READ_BIT(PWR->WUSR, PWR_WUSR_WUF7) == \ + PWR_WUSR_WUF7) : \ + (READ_BIT(PWR->WUSR, PWR_WUSR_WUF8) == PWR_WUSR_WUF8)) +#elif defined(PWR_STOP2_SUPPORT) && defined(PWR_FLAG_REGS) && !defined(PWR_STOP3_SUPPORT) +#define __HAL_PWR_GET_FLAG(__FLAG__)( \ + ((__FLAG__) == PWR_FLAG_VOSRDY) ? (READ_BIT(PWR->VOSR, PWR_VOSR_VOSRDY)== \ + PWR_VOSR_VOSRDY) : \ + ((__FLAG__) == PWR_FLAG_STOPF) ? (READ_BIT(PWR->SR, PWR_SR_STOPF)== \ + PWR_SR_STOPF) : \ + ((__FLAG__) == PWR_FLAG_SBF) ? (READ_BIT(PWR->SR, PWR_SR_SBF)== \ + PWR_SR_SBF) : \ + ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ?(READ_BIT(PWR->SVMSR, PWR_SVMSR_ACTVOSRDY)== \ + PWR_SVMSR_ACTVOSRDY): \ + ((__FLAG__) == PWR_FLAG_PVDO) ?(READ_BIT(PWR->SVMSR, PWR_SVMSR_PVDO)== \ + PWR_SVMSR_PVDO) : \ + ((__FLAG__) == PWR_FLAG_REGS) ?(READ_BIT(PWR->SVMSR, PWR_SVMSR_REGS)== \ + PWR_SVMSR_REGS) : \ + ((__FLAG__) == PWR_FLAG_REGPARDYVDDRFPA) ?(READ_BIT(PWR->RADIOSCR, PWR_RADIOSCR_REGPARDYVDDRFPA)== \ + PWR_RADIOSCR_REGPARDYVDDRFPA) : \ + ((__FLAG__) == PWR_FLAG_REGPARDYV11) ?(READ_BIT(PWR->RADIOSCR, PWR_RADIOSCR_REGPARDYV11)== \ + PWR_RADIOSCR_REGPARDYV11) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG1) ?(READ_BIT(PWR->WUSR, PWR_WUSR_WUF1) == \ + PWR_WUSR_WUF1) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG2) ?(READ_BIT(PWR->WUSR, PWR_WUSR_WUF2) == \ + PWR_WUSR_WUF2) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG3) ?(READ_BIT(PWR->WUSR, PWR_WUSR_WUF3) == \ + PWR_WUSR_WUF3) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG4) ?(READ_BIT(PWR->WUSR, PWR_WUSR_WUF4) == \ + PWR_WUSR_WUF4) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG5) ?(READ_BIT(PWR->WUSR, PWR_WUSR_WUF5) == \ + PWR_WUSR_WUF5) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG6) ?(READ_BIT(PWR->WUSR, PWR_WUSR_WUF6) == \ + PWR_WUSR_WUF6) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG7) ?(READ_BIT(PWR->WUSR, PWR_WUSR_WUF7) == \ + PWR_WUSR_WUF7) : \ + (READ_BIT(PWR->WUSR, PWR_WUSR_WUF8) == PWR_WUSR_WUF8)) +#elif defined(PWR_STOP2_SUPPORT) && defined(PWR_STOP3_SUPPORT) +#define __HAL_PWR_GET_FLAG(__FLAG__)( \ + ((__FLAG__) == PWR_FLAG_VOSRDY) ? (READ_BIT(PWR->VOSR, PWR_VOSR_VOSRDY)== \ + PWR_VOSR_VOSRDY) : \ + ((__FLAG__) == PWR_FLAG_STOPF) ? (READ_BIT(PWR->SR, PWR_SR_STOPF)== \ + PWR_SR_STOPF) : \ + ((__FLAG__) == PWR_FLAG_STOP2F) ? (READ_BIT(PWR->SR, PWR_SR_STOP2F)== \ + PWR_SR_STOP2F) : \ + ((__FLAG__) == PWR_FLAG_SBF) ? (READ_BIT(PWR->SR, PWR_SR_SBF)== \ + PWR_SR_SBF) : \ + ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ?(READ_BIT(PWR->SVMSR, PWR_SVMSR_ACTVOSRDY)== \ + PWR_SVMSR_ACTVOSRDY): \ + ((__FLAG__) == PWR_FLAG_PVDO) ?(READ_BIT(PWR->SVMSR, PWR_SVMSR_PVDO)== \ + PWR_SVMSR_PVDO) : \ + ((__FLAG__) == PWR_FLAG_REGS) ?(READ_BIT(PWR->SVMSR, PWR_SVMSR_REGS)== \ + PWR_SVMSR_REGS) : \ + ((__FLAG__) == PWR_FLAG_REGPARDYVDDRFPA) ?(READ_BIT(PWR->RADIOSCR, PWR_RADIOSCR_REGPARDYVDDRFPA)== \ + PWR_RADIOSCR_REGPARDYVDDRFPA) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG1) ?(READ_BIT(PWR->WUSR, PWR_WUSR_WUF1) == \ + PWR_WUSR_WUF1) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG2) ?(READ_BIT(PWR->WUSR, PWR_WUSR_WUF2) == \ + PWR_WUSR_WUF2) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG3) ?(READ_BIT(PWR->WUSR, PWR_WUSR_WUF3) == \ + PWR_WUSR_WUF3) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG4) ?(READ_BIT(PWR->WUSR, PWR_WUSR_WUF4) == \ + PWR_WUSR_WUF4) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG6) ?(READ_BIT(PWR->WUSR, PWR_WUSR_WUF6) == \ + PWR_WUSR_WUF6) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG7) ?(READ_BIT(PWR->WUSR, PWR_WUSR_WUF7) == \ + PWR_WUSR_WUF7) : \ + (READ_BIT(PWR->WUSR, PWR_WUSR_WUF8) == PWR_WUSR_WUF8)) +#elif defined(PWR_STOP2_SUPPORT) +#define __HAL_PWR_GET_FLAG(__FLAG__)( \ + ((__FLAG__) == PWR_FLAG_VOSRDY) ? (READ_BIT(PWR->VOSR, PWR_VOSR_VOSRDY)== \ + PWR_VOSR_VOSRDY) : \ + ((__FLAG__) == PWR_FLAG_STOPF) ? (READ_BIT(PWR->SR, PWR_SR_STOPF)== \ + PWR_SR_STOPF) : \ + ((__FLAG__) == PWR_FLAG_STOP2F) ? (READ_BIT(PWR->SR, PWR_SR_STOP2F)== \ + PWR_SR_STOP2F) : \ + ((__FLAG__) == PWR_FLAG_SBF) ? (READ_BIT(PWR->SR, PWR_SR_SBF)== \ + PWR_SR_SBF) : \ + ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ?(READ_BIT(PWR->SVMSR, PWR_SVMSR_ACTVOSRDY)== \ + PWR_SVMSR_ACTVOSRDY): \ + ((__FLAG__) == PWR_FLAG_PVDO) ?(READ_BIT(PWR->SVMSR, PWR_SVMSR_PVDO)== \ + PWR_SVMSR_PVDO) : \ + ((__FLAG__) == PWR_FLAG_REGPARDYVDDRFPA) ?(READ_BIT(PWR->RADIOSCR, PWR_RADIOSCR_REGPARDYVDDRFPA)== \ + PWR_RADIOSCR_REGPARDYVDDRFPA) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG1) ?(READ_BIT(PWR->WUSR, PWR_WUSR_WUF1) == \ + PWR_WUSR_WUF1) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG2) ?(READ_BIT(PWR->WUSR, PWR_WUSR_WUF2) == \ + PWR_WUSR_WUF2) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG3) ?(READ_BIT(PWR->WUSR, PWR_WUSR_WUF3) == \ + PWR_WUSR_WUF3) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG4) ?(READ_BIT(PWR->WUSR, PWR_WUSR_WUF4) == \ + PWR_WUSR_WUF4) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG5) ?(READ_BIT(PWR->WUSR, PWR_WUSR_WUF5) == \ + PWR_WUSR_WUF5) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG6) ?(READ_BIT(PWR->WUSR, PWR_WUSR_WUF6) == \ + PWR_WUSR_WUF6) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG7) ?(READ_BIT(PWR->WUSR, PWR_WUSR_WUF7) == \ + PWR_WUSR_WUF7) : \ + (READ_BIT(PWR->WUSR, PWR_WUSR_WUF8) == PWR_WUSR_WUF8)) +#else #if defined(PWR_WUCR1_WUPEN2) && defined(PWR_WUCR1_WUPEN5) #if defined(PWR_FLAG_REGS) #define __HAL_PWR_GET_FLAG(__FLAG__)( \ @@ -477,12 +668,17 @@ typedef struct PWR_WUSR_WUF7) : \ (READ_BIT(PWR->WUSR, PWR_WUSR_WUF8) == PWR_WUSR_WUF8)) #endif /*defined(PWR_WUCR1_WUPEN2) && defined(PWR_WUCR1_WUPEN5) */ +#endif /* defined(PWR_STOP2_SUPPORT) */ /** @brief Clear PWR flags. * @param __FLAG__ : Specifies the flag to clear. * This parameter can be one of the following values when available: * @arg @ref PWR_FLAG_STOPF : Stop flag. * Indicates that the device was resumed from Stop mode. +#if defined(PWR_STOP2_SUPPORT) + * @arg @ref PWR_FLAG_STOP2F : Stop 2 flag. + * Indicates that the device was resumed from Stop 2 mode. +#endif * @arg @ref PWR_FLAG_SBF : Standby flag. * Indicates that the device was resumed from Standby mode. * @arg @ref PWR_WAKEUP_FLAG1 : Wakeup flag 1. @@ -504,6 +700,51 @@ typedef struct * @arg @ref PWR_WAKEUP_ALL_FLAG : all Wakeup flags. * @retval None. */ +#if defined(PWR_STOP2_SUPPORT) +#if defined(PWR_STOP3_SUPPORT) +#define __HAL_PWR_CLEAR_FLAG(__FLAG__) ( \ + ((__FLAG__) == PWR_FLAG_STOPF) ? (SET_BIT(PWR->SR, PWR_SR_CSSF)) : \ + ((__FLAG__) == PWR_FLAG_STOP2F) ? (SET_BIT(PWR->SR, PWR_SR_CSSF)) : \ + ((__FLAG__) == PWR_FLAG_SBF) ? (SET_BIT(PWR->SR, PWR_SR_CSSF)) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG1) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF1)) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG2) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF2)) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG3) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF3)) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG4) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF4)) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG6) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF6)) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG7) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF7)) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG8) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF8)) : \ + (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF))) +#else +#if defined(PWR_WUCR1_WUPEN2) && defined(PWR_WUCR1_WUPEN5) +#define __HAL_PWR_CLEAR_FLAG(__FLAG__) ( \ + ((__FLAG__) == PWR_FLAG_STOPF) ? (SET_BIT(PWR->SR, PWR_SR_CSSF)) : \ + ((__FLAG__) == PWR_FLAG_STOP2F) ? (SET_BIT(PWR->SR, PWR_SR_CSSF)) : \ + ((__FLAG__) == PWR_FLAG_SBF) ? (SET_BIT(PWR->SR, PWR_SR_CSSF)) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG1) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF1)) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG2) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF2)) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG3) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF3)) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG4) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF4)) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG5) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF5)) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG6) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF6)) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG7) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF7)) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG8) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF8)) : \ + (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF))) +#else +#define __HAL_PWR_CLEAR_FLAG(__FLAG__) ( \ + ((__FLAG__) == PWR_FLAG_STOPF) ? (SET_BIT(PWR->SR, PWR_SR_CSSF)) : \ + ((__FLAG__) == PWR_FLAG_STOP2F) ? (SET_BIT(PWR->SR, PWR_SR_CSSF)) : \ + ((__FLAG__) == PWR_FLAG_SBF) ? (SET_BIT(PWR->SR, PWR_SR_CSSF)) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG1) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF1)) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG3) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF3)) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG4) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF4)) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG6) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF6)) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG7) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF7)) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG8) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF8)) : \ + (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF))) + +#endif /* defined(PWR_WUCR1_WUPEN2) && defined(PWR_WUCR1_WUPEN5) */ +#endif /* defined(PWR_STOP3_SUPPORT) */ +#else #if defined(PWR_WUCR1_WUPEN2) && defined(PWR_WUCR1_WUPEN5) #define __HAL_PWR_CLEAR_FLAG(__FLAG__) ( \ ((__FLAG__) == PWR_FLAG_STOPF) ? (SET_BIT(PWR->SR, PWR_SR_CSSF)) : \ @@ -529,6 +770,7 @@ typedef struct ((__FLAG__) == PWR_WAKEUP_FLAG8) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF8)) : \ (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF))) #endif /* defined(PWR_WUCR1_WUPEN2) && defined(PWR_WUCR1_WUPEN5) */ +#endif /* defined(PWR_STOP2_SUPPORT) */ /** * @brief Enable the PVD Extended Interrupt Line. @@ -652,7 +894,7 @@ typedef struct /* Defines wake up lines selection */ #define PWR_WAKEUP1_SOURCE_SELECTION_0 (0U) -#if defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) || defined(STM32WBA5Mxx) +#if defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) || defined(STM32WBA5Mxx) || defined(PWR_STOP2_SUPPORT) #define PWR_WAKEUP1_SOURCE_SELECTION_1 (PWR_WUCR3_WUSEL1_0 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ #endif /* defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) || defined(STM32WBA5Mxx) */ @@ -662,12 +904,12 @@ typedef struct #endif /* defined(PWR_WUCR1_WUPEN2) */ #define PWR_WAKEUP3_SOURCE_SELECTION_1 (PWR_WUCR3_WUSEL3_0 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ -#if defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) || defined(STM32WBA5Mxx) +#if defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) || defined(STM32WBA5Mxx) || defined(PWR_STOP2_SUPPORT) #define PWR_WAKEUP3_SOURCE_SELECTION_2 (PWR_WUCR3_WUSEL3_1 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ #endif /* defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) || defined(STM32WBA5Mxx) */ #define PWR_WAKEUP4_SOURCE_SELECTION_0 (0U) /*!< Internal constant used to retrieve wakeup signal selection */ -#if defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) || defined(STM32WBA5Mxx) +#if defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) || defined(STM32WBA5Mxx) || defined(PWR_STOP2_SUPPORT) #define PWR_WAKEUP4_SOURCE_SELECTION_1 (PWR_WUCR3_WUSEL4_0 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ #endif /* defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) || defined(STM32WBA5Mxx) */ @@ -680,7 +922,7 @@ typedef struct #define PWR_WAKEUP6_SOURCE_SELECTION_1 (PWR_WUCR3_WUSEL6_0 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ #define PWR_WAKEUP6_SOURCE_SELECTION_3 ((PWR_WUCR3_WUSEL6_0 | PWR_WUCR3_WUSEL6_1) << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ -#if defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) || defined(STM32WBA5Mxx) +#if defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) || defined(STM32WBA5Mxx) || defined(PWR_STOP2_SUPPORT) #define PWR_WAKEUP7_SOURCE_SELECTION_0 (0U) /*!< Internal constant used to retrieve wakeup signal selection */ #endif /* defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) || defined(STM32WBA5Mxx) */ #define PWR_WAKEUP7_SOURCE_SELECTION_1 (PWR_WUCR3_WUSEL7_0 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ @@ -718,8 +960,21 @@ typedef struct */ /* Stop mode entry check macro */ +#if defined(PWR_STOP2_SUPPORT) +#if defined(PWR_STOP3_SUPPORT) +#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_LOWPOWERMODE_STOP0) || \ + ((REGULATOR) == PWR_LOWPOWERMODE_STOP1) || \ + ((REGULATOR) == PWR_LOWPOWERMODE_STOP2) || \ + ((REGULATOR) == PWR_LOWPOWERMODE_STOP3)) +#else +#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_LOWPOWERMODE_STOP0) || \ + ((REGULATOR) == PWR_LOWPOWERMODE_STOP1) || \ + ((REGULATOR) == PWR_LOWPOWERMODE_STOP2)) +#endif /* defined(PWR_STOP3_SUPPORT) */ +#else #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_LOWPOWERMODE_STOP0) || \ ((REGULATOR) == PWR_LOWPOWERMODE_STOP1)) +#endif /* defined(PWR_STOP2_SUPPORT) */ /* Wake up pins check macro */ @@ -848,12 +1103,67 @@ typedef struct ((PIN) == PWR_WAKEUP_PIN8)) #endif /* defined (STM32WBA55xx) */ #endif /* defined (STM32WBA52xx) || defined (STM32WBA54xx) || defined (STM32WBA55xx) */ +#if defined (STM32WBA62xx) || defined (STM32WBA63xx) || defined (STM32WBA64xx) || defined (STM32WBA65xx) || defined (STM32WBA6Mxx) +#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1_HIGH_0) ||\ + ((PIN) == PWR_WAKEUP_PIN1_HIGH_1) ||\ + ((PIN) == PWR_WAKEUP_PIN2_HIGH_0) ||\ + ((PIN) == PWR_WAKEUP_PIN2_HIGH_1) ||\ + ((PIN) == PWR_WAKEUP_PIN3_HIGH_1) ||\ + ((PIN) == PWR_WAKEUP_PIN3_HIGH_2) ||\ + ((PIN) == PWR_WAKEUP_PIN4_HIGH_0) ||\ + ((PIN) == PWR_WAKEUP_PIN4_HIGH_1) ||\ + ((PIN) == PWR_WAKEUP_PIN5_HIGH_1) ||\ + ((PIN) == PWR_WAKEUP_PIN5_HIGH_2) ||\ + ((PIN) == PWR_WAKEUP_PIN6_HIGH_0) ||\ + ((PIN) == PWR_WAKEUP_PIN6_HIGH_1) ||\ + ((PIN) == PWR_WAKEUP_PIN6_HIGH_3) ||\ + ((PIN) == PWR_WAKEUP_PIN7_HIGH_0) ||\ + ((PIN) == PWR_WAKEUP_PIN7_HIGH_1) ||\ + ((PIN) == PWR_WAKEUP_PIN7_HIGH_3) ||\ + ((PIN) == PWR_WAKEUP_PIN8_HIGH_1) ||\ + ((PIN) == PWR_WAKEUP_PIN8_HIGH_2) ||\ + ((PIN) == PWR_WAKEUP_PIN8_HIGH_3) ||\ + ((PIN) == PWR_WAKEUP_PIN1_LOW_0) ||\ + ((PIN) == PWR_WAKEUP_PIN1_LOW_1) ||\ + ((PIN) == PWR_WAKEUP_PIN2_LOW_0) ||\ + ((PIN) == PWR_WAKEUP_PIN2_LOW_1) ||\ + ((PIN) == PWR_WAKEUP_PIN3_LOW_1) ||\ + ((PIN) == PWR_WAKEUP_PIN3_LOW_2) ||\ + ((PIN) == PWR_WAKEUP_PIN4_LOW_0) ||\ + ((PIN) == PWR_WAKEUP_PIN4_LOW_1) ||\ + ((PIN) == PWR_WAKEUP_PIN5_LOW_1) ||\ + ((PIN) == PWR_WAKEUP_PIN5_LOW_2) ||\ + ((PIN) == PWR_WAKEUP_PIN6_LOW_0) ||\ + ((PIN) == PWR_WAKEUP_PIN6_LOW_1) ||\ + ((PIN) == PWR_WAKEUP_PIN6_LOW_3) ||\ + ((PIN) == PWR_WAKEUP_PIN7_LOW_0) ||\ + ((PIN) == PWR_WAKEUP_PIN7_LOW_1) ||\ + ((PIN) == PWR_WAKEUP_PIN7_LOW_3) ||\ + ((PIN) == PWR_WAKEUP_PIN8_LOW_1) ||\ + ((PIN) == PWR_WAKEUP_PIN8_LOW_2) ||\ + ((PIN) == PWR_WAKEUP_PIN8_LOW_3) ||\ + ((PIN) == PWR_WAKEUP_PIN1) ||\ + ((PIN) == PWR_WAKEUP_PIN2) ||\ + ((PIN) == PWR_WAKEUP_PIN3) ||\ + ((PIN) == PWR_WAKEUP_PIN4) ||\ + ((PIN) == PWR_WAKEUP_PIN5) ||\ + ((PIN) == PWR_WAKEUP_PIN6) ||\ + ((PIN) == PWR_WAKEUP_PIN7) ||\ + ((PIN) == PWR_WAKEUP_PIN8)) +#endif /* defined (STM32WBA62xx) || defined (STM32WBA63xx) || defined (STM32WBA64xx) || defined (STM32WBA65xx) || defined (STM32WBA6Mxx) */ /* PVD level check macro */ +#if defined(PWR_STOP3_SUPPORT) +#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1) || \ + ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3) || \ + ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5) || \ + ((LEVEL) == PWR_PVDLEVEL_6)) +#else #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1) || \ ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3) || \ ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5) || \ ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) +#endif /* defined(PWR_STOP3_SUPPORT) */ /* PVD mode check macro */ #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_NORMAL) ||\ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_pwr_ex.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_pwr_ex.h index 827b1e0b7f..63ffd0d005 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_pwr_ex.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_pwr_ex.h @@ -52,13 +52,38 @@ extern "C" { * @{ */ /* SRAM1 pages retention defines */ +#if defined(PWR_STOP2_SUPPORT) && !defined(PWR_STOP3_SUPPORT) +#define PWR_SRAM1_PAGE1_STOP_RETENTION PWR_CR2_SRAM1PDS1 /*!< SRAM1 page 1 retention in Stop mode */ +#define PWR_SRAM1_PAGE2_STOP_RETENTION PWR_CR2_SRAM1PDS2 /*!< SRAM1 page 2 retention in Stop mode */ +#define PWR_SRAM1_PAGE3_STOP_RETENTION PWR_CR2_SRAM1PDS3 /*!< SRAM1 page 3 retention in Stop mode */ +#define PWR_SRAM1_PAGE4_STOP_RETENTION PWR_CR2_SRAM1PDS4 /*!< SRAM1 page 4 retention in Stop mode */ +#define PWR_SRAM1_PAGE567_STOP_RETENTION PWR_CR2_SRAM1PDS567 /*!< SRAM1 page 5-6-7 retention in Stop mode */ +#define PWR_SRAM1_FULL_STOP_RETENTION (PWR_CR2_SRAM1PDS1 |PWR_CR2_SRAM1PDS2 |PWR_CR2_SRAM1PDS3 |\ + PWR_CR2_SRAM1PDS4 | PWR_CR2_SRAM1PDS567) +#else #define PWR_SRAM1_FULL_STOP_RETENTION PWR_CR2_SRAM1PDS1 /*!< SRAM1 full retention in Stop modes */ +#endif /* defined(PWR_STOP2_SUPPORT) && !defined(PWR_STOP3_SUPPORT) */ /* SRAM2 pages retention defines */ +#if defined(PWR_STOP3_SUPPORT) +#define PWR_SRAM2_PAGE1_STOP_RETENTION PWR_CR2_SRAM2PDS1 /*!< SRAM2 page1 retention in Stop modes */ +#define PWR_SRAM2_PAGE2_STOP_RETENTION PWR_CR2_SRAM2PDS2 /*!< SRAM2 page2 retention in Stop modes */ +#define PWR_SRAM2_FULL_STOP_RETENTION (PWR_CR2_SRAM2PDS1 | PWR_CR2_SRAM2PDS2) /*!< SRAM2 full retention in Stop modes */ +#else #define PWR_SRAM2_FULL_STOP_RETENTION PWR_CR2_SRAM2PDS1 /*!< SRAM2 full retention in Stop modes */ +#endif /* !defined(PWR_STOP3_SUPPORT) */ /* Cache RAMs retention defines */ #define PWR_ICACHE_FULL_STOP_RETENTION PWR_CR2_ICRAMPDS /*!< ICACHE SRAM retention in Stop modes */ +#if defined(PWR_STOP2_SUPPORT) +#if defined(USB_OTG_HS) +/* USB_OTG_HS SRAM power-down in Stop modes */ +#define PWR_USB_OTG_HS_SRAM_STOP_RETENTION PWR_CR2_PRAMPDS /*!< USB_OTG_HS SRAM content retained in Stop modes */ +#endif /* defined(USB_OTG_HS) */ + +/* PKA SRAM power-down in Stop modes */ +#define PWR_PKA_SRAM_STOP_RETENTION PWR_CR2_PKARAMPDS /*!< PKA SRAM content retained in Stop modes */ +#endif /* defined(PWR_STOP2_SUPPORT) */ /** * @} */ @@ -67,9 +92,25 @@ extern "C" { /** @defgroup PWREx_RAM_Contents_Standby_Retention PWR Extended SRAM Contents Standby Retention * @{ */ +#if defined(PWR_STOP2_SUPPORT) && !defined(PWR_STOP3_SUPPORT) +#define PWR_SRAM1_PAGE1_STANDBY_RETENTION PWR_CR1_R1RSB1 /*!< SRAM1 page 1 retention in Standby mode */ +#define PWR_SRAM1_PAGE2_STANDBY_RETENTION PWR_CR1_R1RSB2 /*!< SRAM1 page 2 retention in Standby mode */ +#define PWR_SRAM1_PAGE3_STANDBY_RETENTION PWR_CR1_R1RSB3 /*!< SRAM1 page 3 retention in Standby mode */ +#define PWR_SRAM1_PAGE4_STANDBY_RETENTION PWR_CR1_R1RSB4 /*!< SRAM1 page 4 retention in Standby mode */ +#define PWR_SRAM1_PAGE567_STANDBY_RETENTION PWR_CR1_R1RSB567 /*!< SRAM1 page 5-6-7 retention in Standby mode */ +#define PWR_SRAM1_FULL_STANDBY_RETENTION (PWR_CR1_R1RSB1 |PWR_CR1_R1RSB2 | PWR_CR1_R1RSB3 |\ + PWR_CR1_R1RSB4 | PWR_CR1_R1RSB567) /*!< SRAM1 full retention in Standby mode */ +#else #define PWR_SRAM1_FULL_STANDBY_RETENTION PWR_CR1_R1RSB1 /*!< SRAM1 full retention in Standby mode */ +#endif /* defined(PWR_STOP2_SUPPORT) */ +#if defined(PWR_STOP3_SUPPORT) +#define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_CR1_R2RSB1 /*!< SRAM2 page 1 retention in Standby mode */ +#define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_CR1_R2RSB2 /*!< SRAM2 page 2 retention in Standby mode */ +#define PWR_SRAM2_FULL_STANDBY_RETENTION (PWR_CR1_R2RSB1 | PWR_CR1_R2RSB2) /*!< SRAM2 full retention in Standby mode */ +#else #define PWR_SRAM2_FULL_STANDBY_RETENTION PWR_CR1_R2RSB1 /*!< SRAM2 full retention in Standby mode */ +#endif /* defined(PWR_STOP3_SUPPORT) */ #define PWR_RADIOSRAM_FULL_STANDBY_RETENTION PWR_CR1_RADIORSB /*!< 2.4GHz RADIO SRAMs (TXRX and Sequence) and Sleep clock retention in Standby mode */ /** @@ -90,8 +131,14 @@ extern "C" { /** @defgroup PWREx_Regulator_Voltage_Scale PWR Extended Regulator Voltage Scale * @{ */ +#if defined(PWR_STOP3_SUPPORT) +#define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_VOSR_VOS_0 /*!< Voltage scaling range 1 */ +#define PWR_REGULATOR_VOLTAGE_SCALE1_5 PWR_VOSR_VOS_1 /*!< Voltage scaling range 1.5 */ +#define PWR_REGULATOR_VOLTAGE_SCALE2 (0U) /*!< Voltage scaling range 2 */ +#else #define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_VOSR_VOS /*!< Voltage scaling range 1 */ #define PWR_REGULATOR_VOLTAGE_SCALE2 (0U) /*!< Voltage scaling range 2 */ +#endif /* defined(PWR_STOP3_SUPPORT) */ /** * @} */ @@ -102,6 +149,17 @@ extern "C" { #define PWR_GPIO_A (0x00U) /*!< GPIO port A */ #define PWR_GPIO_B (0x01U) /*!< GPIO port B */ #define PWR_GPIO_C (0x02U) /*!< GPIO port C */ +#if defined(PWR_STOP2_SUPPORT) +#if defined(GPIOD) +#define PWR_GPIO_D (0x03U) /*!< GPIO port D */ +#endif /* defined(GPIOD) */ +#if defined(GPIOE) +#define PWR_GPIO_E (0x04U) /*!< GPIO port E */ +#endif /* defined(GPIOE) */ +#if defined(GPIOG) +#define PWR_GPIO_G (0x06U) /*!< GPIO port G */ +#endif /* defined(GPIOG) */ +#endif /* defined(PWR_STOP2_SUPPORT) */ #define PWR_GPIO_H (0x07U) /*!< GPIO port H */ /** * @} @@ -220,8 +278,30 @@ extern "C" { */ /* All available RAM retention in Stop mode define */ +#if defined(PWR_STOP2_SUPPORT) && !defined(PWR_STOP3_SUPPORT) +#if defined(USB_OTG_HS) +#define PWR_ALL_RAM_STOP_RETENTION_MASK (PWR_SRAM1_FULL_STOP_RETENTION | PWR_SRAM2_FULL_STOP_RETENTION | \ + PWR_ICACHE_FULL_STOP_RETENTION | PWR_USB_OTG_HS_SRAM_STOP_RETENTION | \ + PWR_PKA_SRAM_STOP_RETENTION) +#else +#define PWR_ALL_RAM_STOP_RETENTION_MASK (PWR_SRAM1_FULL_STOP_RETENTION | PWR_SRAM2_FULL_STOP_RETENTION | \ + PWR_ICACHE_FULL_STOP_RETENTION | PWR_PKA_SRAM_STOP_RETENTION) + +#endif /* defined(USB_OTG_HS) */ +#else +#if defined(PWR_STOP3_SUPPORT) +#if defined (PWR_USB_SRAM_STOP_RETENTION) +#define PWR_ALL_RAM_STOP_RETENTION_MASK (PWR_SRAM1_FULL_STOP_RETENTION | PWR_SRAM2_FULL_STOP_RETENTION | \ + PWR_USB_SRAM_STOP_RETENTION | PWR_PKA_SRAM_STOP_RETENTION) +#else /* defined (PWR_USB_SRAM_STOP_RETENTION) */ +#define PWR_ALL_RAM_STOP_RETENTION_MASK (PWR_SRAM1_FULL_STOP_RETENTION | PWR_SRAM2_FULL_STOP_RETENTION | \ + PWR_PKA_SRAM_STOP_RETENTION) +#endif /* defined (PWR_USB_SRAM_STOP_RETENTION) */ +#else #define PWR_ALL_RAM_STOP_RETENTION_MASK (PWR_SRAM1_FULL_STOP_RETENTION | PWR_SRAM2_FULL_STOP_RETENTION | \ PWR_ICACHE_FULL_STOP_RETENTION ) +#endif /* defined(PWR_STOP3_SUPPORT) */ +#endif /* defined(PWR_STOP2_SUPPORT) && !defined(PWR_STOP3_SUPPORT) */ /* All available RAM retention in Standby mode define */ #define PWR_ALL_RAM_STANDBY_RETENTION_MASK (PWR_SRAM1_FULL_STANDBY_RETENTION | PWR_SRAM2_FULL_STANDBY_RETENTION) /** @@ -241,32 +321,129 @@ extern "C" { #endif /* defined(PWR_CR3_REGSEL) */ /* Voltage scaling range check macro */ +#if defined(PWR_STOP3_SUPPORT) #define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) ||\ + ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1_5) ||\ ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2)) +#else +#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) ||\ + ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2)) +#endif /* defined(PWR_STOP3_SUPPORT) */ /* GPIO port check macro */ +#if defined(PWR_STOP2_SUPPORT) +#if defined(PWR_GPIO_D) +#if defined(PWR_GPIO_E) && defined(PWR_GPIO_G) +#define IS_PWR_GPIO_PORT(GPIO_PORT) (((GPIO_PORT) == PWR_GPIO_A) ||\ + ((GPIO_PORT) == PWR_GPIO_B) ||\ + ((GPIO_PORT) == PWR_GPIO_C) ||\ + ((GPIO_PORT) == PWR_GPIO_D) ||\ + ((GPIO_PORT) == PWR_GPIO_E) ||\ + ((GPIO_PORT) == PWR_GPIO_G) ||\ + ((GPIO_PORT) == PWR_GPIO_H)) +#elif defined(PWR_GPIO_E) +#define IS_PWR_GPIO_PORT(GPIO_PORT) (((GPIO_PORT) == PWR_GPIO_A) ||\ + ((GPIO_PORT) == PWR_GPIO_B) ||\ + ((GPIO_PORT) == PWR_GPIO_C) ||\ + ((GPIO_PORT) == PWR_GPIO_D) ||\ + ((GPIO_PORT) == PWR_GPIO_E) ||\ + ((GPIO_PORT) == PWR_GPIO_H)) +#elif defined(PWR_GPIO_G) +#define IS_PWR_GPIO_PORT(GPIO_PORT) (((GPIO_PORT) == PWR_GPIO_A) ||\ + ((GPIO_PORT) == PWR_GPIO_B) ||\ + ((GPIO_PORT) == PWR_GPIO_C) ||\ + ((GPIO_PORT) == PWR_GPIO_D) ||\ + ((GPIO_PORT) == PWR_GPIO_G) ||\ + ((GPIO_PORT) == PWR_GPIO_H)) +#else /* No PWR_GPIO_E and PWR_GPIO_G */ +#define IS_PWR_GPIO_PORT(GPIO_PORT) (((GPIO_PORT) == PWR_GPIO_A) ||\ + ((GPIO_PORT) == PWR_GPIO_B) ||\ + ((GPIO_PORT) == PWR_GPIO_C) ||\ + ((GPIO_PORT) == PWR_GPIO_D) ||\ + ((GPIO_PORT) == PWR_GPIO_H)) +#endif /* PWR_GPIO_E */ +#else /* No PWR_GPIO_D */ +#define IS_PWR_GPIO_PORT(GPIO_PORT) (((GPIO_PORT) == PWR_GPIO_A) ||\ + ((GPIO_PORT) == PWR_GPIO_B) ||\ + ((GPIO_PORT) == PWR_GPIO_C) ||\ + ((GPIO_PORT) == PWR_GPIO_H)) +#endif /* PWR_GPIO_D */ +#else #define IS_PWR_GPIO_PORT(GPIO_PORT) (((GPIO_PORT) == PWR_GPIO_A) ||\ ((GPIO_PORT) == PWR_GPIO_B) ||\ ((GPIO_PORT) == PWR_GPIO_C) ||\ ((GPIO_PORT) == PWR_GPIO_H)) +#endif /* defined(PWR_STOP2_SUPPORT) */ /* GPIO pin mask check macro */ #define IS_PWR_GPIO_PIN_MASK(BIT_MASK) ((((BIT_MASK) & PWR_GPIO_PIN_MASK) != 0U) &&\ ((BIT_MASK) <= PWR_GPIO_PIN_MASK)) /* SRAM1 retention in Standby mode check macro */ +#if defined(PWR_STOP2_SUPPORT) && !defined(PWR_STOP3_SUPPORT) +#define IS_PWR_SRAM1_STANDBY_RETENTION(CONTENT) (((CONTENT) == PWR_SRAM1_PAGE1_STANDBY_RETENTION) ||\ + ((CONTENT) == PWR_SRAM1_PAGE2_STANDBY_RETENTION) ||\ + ((CONTENT) == PWR_SRAM1_PAGE3_STANDBY_RETENTION) ||\ + ((CONTENT) == PWR_SRAM1_PAGE4_STANDBY_RETENTION) ||\ + ((CONTENT) == PWR_SRAM1_PAGE567_STANDBY_RETENTION) ||\ + ((CONTENT) == PWR_SRAM1_FULL_STANDBY_RETENTION)) +#else #define IS_PWR_SRAM1_STANDBY_RETENTION(CONTENT) ((CONTENT) == PWR_SRAM1_FULL_STANDBY_RETENTION) +#endif /* defined(PWR_STOP2_SUPPORT) && !defined(PWR_STOP3_SUPPORT) */ /* SRAM2 retention in Standby mode check macro */ +#if defined(PWR_STOP3_SUPPORT) +#define IS_PWR_SRAM2_STANDBY_RETENTION(CONTENT) (((CONTENT) == PWR_SRAM2_PAGE1_STANDBY_RETENTION) ||\ + ((CONTENT) == PWR_SRAM2_PAGE2_STANDBY_RETENTION) ||\ + ((CONTENT) == PWR_SRAM2_FULL_STANDBY_RETENTION)) +#else #define IS_PWR_SRAM2_STANDBY_RETENTION(CONTENT) ((CONTENT) == PWR_SRAM2_FULL_STANDBY_RETENTION) +#endif /* defined(PWR_STOP3_SUPPORT) */ /* RADIO SRAM retention in Standby mode check macro */ #define IS_PWR_RADIOSRAM_STANDBY_RETENTION(CONTENT) ((CONTENT) == PWR_RADIOSRAM_FULL_STANDBY_RETENTION) /* RAMs retention in Stop mode check macro */ +#if defined(PWR_STOP2_SUPPORT) +#if defined(USB_OTG_HS) +#define IS_PWR_RAM_STOP_RETENTION(RAMCONTENT) (((RAMCONTENT) == PWR_SRAM1_PAGE1_STOP_RETENTION) ||\ + ((RAMCONTENT) == PWR_SRAM1_PAGE2_STOP_RETENTION) ||\ + ((RAMCONTENT) == PWR_SRAM1_PAGE3_STOP_RETENTION) ||\ + ((RAMCONTENT) == PWR_SRAM1_PAGE4_STOP_RETENTION) ||\ + ((RAMCONTENT) == PWR_SRAM1_PAGE567_STOP_RETENTION) ||\ + ((RAMCONTENT) == PWR_SRAM1_FULL_STOP_RETENTION) ||\ + ((RAMCONTENT) == PWR_SRAM2_FULL_STOP_RETENTION) ||\ + ((RAMCONTENT) == PWR_ICACHE_FULL_STOP_RETENTION) ||\ + ((RAMCONTENT) == PWR_USB_OTG_HS_SRAM_STOP_RETENTION) ||\ + ((RAMCONTENT) == PWR_PKA_SRAM_STOP_RETENTION)) +#else +#if defined(PWR_STOP3_SUPPORT) +#define IS_PWR_RAM_STOP_RETENTION(RAMCONTENT) (((RAMCONTENT) == PWR_SRAM1_FULL_STOP_RETENTION) ||\ + ((RAMCONTENT) == PWR_SRAM2_PAGE1_STOP_RETENTION) ||\ + ((RAMCONTENT) == PWR_SRAM2_PAGE2_STOP_RETENTION) ||\ + ((RAMCONTENT) == PWR_SRAM2_FULL_STOP_RETENTION) ||\ + ((RAMCONTENT) == PWR_PKA_SRAM_STOP_RETENTION)) +#else +#define IS_PWR_RAM_STOP_RETENTION(RAMCONTENT) (((RAMCONTENT) == PWR_SRAM1_PAGE1_STOP_RETENTION) ||\ + ((RAMCONTENT) == PWR_SRAM1_PAGE2_STOP_RETENTION) ||\ + ((RAMCONTENT) == PWR_SRAM1_PAGE3_STOP_RETENTION) ||\ + ((RAMCONTENT) == PWR_SRAM1_PAGE4_STOP_RETENTION) ||\ + ((RAMCONTENT) == PWR_SRAM1_PAGE567_STOP_RETENTION) ||\ + ((RAMCONTENT) == PWR_SRAM1_FULL_STOP_RETENTION) ||\ + ((RAMCONTENT) == PWR_SRAM2_FULL_STOP_RETENTION) ||\ + ((RAMCONTENT) == PWR_ICACHE_FULL_STOP_RETENTION) ||\ + ((RAMCONTENT) == PWR_PKA_SRAM_STOP_RETENTION)) +#endif /* defined(PWR_STOP3_SUPPORT) */ +#endif /* defined(USB_OTG_HS) */ +#else #define IS_PWR_RAM_STOP_RETENTION(RAMCONTENT) (((RAMCONTENT) == PWR_SRAM1_FULL_STOP_RETENTION) ||\ ((RAMCONTENT) == PWR_SRAM2_FULL_STOP_RETENTION) ||\ ((RAMCONTENT) == PWR_ICACHE_FULL_STOP_RETENTION)) +#endif /* defined(PWR_STOP2_SUPPORT) */ +#if defined(PWR_STOP2_SUPPORT) +/* Vdd11 USB switch delay check macro */ +#define IS_PWR_VDD11USB_SWITCH_DELAY(DELAY) ((DELAY) <= 1023U) +#endif /* defined(PWR_STOP2_SUPPORT) */ /** * @} */ @@ -291,6 +468,25 @@ void HAL_PWREx_DisableSMPSPWM(void); #endif /* defined(PWR_CR2_FPWM) */ void HAL_PWREx_EnableFastSoftStart(void); void HAL_PWREx_DisableFastSoftStart(void); +#if defined(PWR_STOP2_SUPPORT) +#if defined(PWR_VOSR_USBPWREN) +void HAL_PWREx_ConfigVdd11UsbSwitchDelay(uint32_t Delay); +void HAL_PWREx_EnableVdd11USB(void); +void HAL_PWREx_DisableVdd11USB(void); +HAL_StatusTypeDef HAL_PWREx_EnableUSBBooster(void); +HAL_StatusTypeDef HAL_PWREx_DisableUSBBooster(void); +void HAL_PWREx_EnableUSBPWR(void); +void HAL_PWREx_DisableUSBPWR(void); +#endif /* defined(PWR_VOSR_USBPWREN) */ +#if defined(PWR_SVMCR_USV) +void HAL_PWREx_EnableVddUSB(void); +void HAL_PWREx_DisableVddUSB(void); +#endif /* defined(PWR_SVMCR_USV) */ +#if defined(PWR_SVMCR_IO2SV) +void HAL_PWREx_EnableVddIO2(void); +void HAL_PWREx_DisableVddIO2(void); +#endif /* defined(PWR_SVMCR_IO2SV) */ +#endif /* defined(PWR_STOP2_SUPPORT) */ /** * @} */ @@ -328,6 +524,12 @@ HAL_StatusTypeDef HAL_PWREx_EnableStandbyIORetention(uint32_t GPIO_Port, uint32_ HAL_StatusTypeDef HAL_PWREx_DisableStandbyIORetention(uint32_t GPIO_Port, uint32_t GPIO_Pin); uint32_t HAL_PWREx_GetStandbyIORetentionStatus(uint32_t GPIO_Port); HAL_StatusTypeDef HAL_PWREx_DisableStandbyRetainedIOState(uint32_t GPIO_Port, uint32_t GPIO_Pin); +#if defined(PWR_STOP2_SUPPORT) +void HAL_PWREx_EnablePTAOutputStop2Retention(void); +void HAL_PWREx_DisablePTAOutputStop2Retention(void); +uint32_t HAL_PWREx_GetPTAOutputStop2RetentionState(void); +void HAL_PWREx_ClearPTAOutputStop2RetentionState(void); +#endif /* defined(PWR_STOP2_SUPPORT) */ /** * @} */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_ramcfg.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_ramcfg.h index 926969e5fd..02d7102768 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_ramcfg.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_ramcfg.h @@ -393,8 +393,11 @@ HAL_RAMCFG_StateTypeDef HAL_RAMCFG_GetState(const RAMCFG_HandleTypeDef *hramcfg) ((WAITSTATE) == RAMCFG_WAITSTATE_4) || ((WAITSTATE) == RAMCFG_WAITSTATE_5) || \ ((WAITSTATE) == RAMCFG_WAITSTATE_6) || ((WAITSTATE) == RAMCFG_WAITSTATE_7)) -#define IS_RAMCFG_WRITEPROTECTION_PAGE(PAGE) ((PAGE) <= 64U) - +#if defined(RAMCFG_WPR2_P32WP) +#define IS_RAMCFG_WRITEPROTECTION_PAGE(PAGE) ((PAGE) < 64U) +#else /* defined(RAMCFG_WPR2_P32WP) */ +#define IS_RAMCFG_WRITEPROTECTION_PAGE(PAGE) ((PAGE) < 32U) +#endif /* defined(RAMCFG_WPR2_P32WP) */ /** diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rcc.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rcc.h index b964b7729c..f5b1b4e1e2 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rcc.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rcc.h @@ -413,20 +413,20 @@ typedef struct * @{ */ /* Flags in the CIFR register */ -#define RCC_IT_LSI1RDY ((CIFR_REG_INDEX << 5U) | RCC_CIFR_LSI1RDYF_Pos) /*!< LSI1 Ready Interrupt flag */ -#define RCC_IT_LSERDY ((CIFR_REG_INDEX << 5U) | RCC_CIFR_LSERDYF_Pos) /*!< LSE Ready Interrupt flag */ -#define RCC_IT_HSIRDY ((CIFR_REG_INDEX << 5U) | RCC_CIFR_HSIRDYF_Pos) /*!< HSI16 Ready Interrupt flag */ -#define RCC_IT_HSERDY ((CIFR_REG_INDEX << 5U) | RCC_CIFR_HSERDYF_Pos) /*!< HSE Ready Interrupt flag */ -#define RCC_IT_PLL1RDY ((CIFR_REG_INDEX << 5U) | RCC_CIFR_PLL1RDYF_Pos) /*!< PLL1 Ready Interrupt flag */ -#define RCC_IT_CSS ((CIFR_REG_INDEX << 5U) | RCC_CIFR_HSECSSF_Pos) /*!< HSE32 Clock Security System Interrupt flag */ +#define RCC_IT_LSI1RDY ((CIFR_REG_INDEX << 5UL) | RCC_CIFR_LSI1RDYF_Pos) /*!< LSI1 Ready Interrupt flag */ +#define RCC_IT_LSERDY ((CIFR_REG_INDEX << 5UL) | RCC_CIFR_LSERDYF_Pos) /*!< LSE Ready Interrupt flag */ +#define RCC_IT_HSIRDY ((CIFR_REG_INDEX << 5UL) | RCC_CIFR_HSIRDYF_Pos) /*!< HSI16 Ready Interrupt flag */ +#define RCC_IT_HSERDY ((CIFR_REG_INDEX << 5UL) | RCC_CIFR_HSERDYF_Pos) /*!< HSE Ready Interrupt flag */ +#define RCC_IT_PLL1RDY ((CIFR_REG_INDEX << 5UL) | RCC_CIFR_PLL1RDYF_Pos) /*!< PLL1 Ready Interrupt flag */ +#define RCC_IT_CSS ((CIFR_REG_INDEX << 5UL) | RCC_CIFR_HSECSSF_Pos) /*!< HSE32 Clock Security System Interrupt flag */ #if defined(RCC_LSI2_SUPPORT) -#define RCC_IT_LSI2RDY ((CIFR_REG_INDEX << 5U) | RCC_CIFR_LSI2RDYF_Pos) /*!< LSI2 Ready Interrupt flag */ +#define RCC_IT_LSI2RDY ((CIFR_REG_INDEX << 5UL) | RCC_CIFR_LSI2RDYF_Pos) /*!< LSI2 Ready Interrupt flag */ #endif /* RCC_BDCR1_LSI2ON */ /* Flags in the ASSR register */ -#define RCC_IT_CAPTURE_ERROR ((ASSR_REG_INDEX << 5U) | RCC_ASSR_CAEF_Pos) /*!< Capture Error Interrupt flag */ -#define RCC_IT_COMPARER ((ASSR_REG_INDEX << 5U) | RCC_ASSR_COF_Pos) /*!< Comparer Interrupt flag */ -#define RCC_IT_CAPTURE_TRIGGER ((ASSR_REG_INDEX << 5U) | RCC_ASSR_CAF_Pos) /*!< Capture Trigger Interrupt flag */ +#define RCC_IT_CAPTURE_ERROR ((ASSR_REG_INDEX << 5UL) | RCC_ASSR_CAEF_Pos) /*!< Capture Error Interrupt flag */ +#define RCC_IT_COMPARER ((ASSR_REG_INDEX << 5UL) | RCC_ASSR_COF_Pos) /*!< Comparer Interrupt flag */ +#define RCC_IT_CAPTURE_TRIGGER ((ASSR_REG_INDEX << 5UL) | RCC_ASSR_CAF_Pos) /*!< Capture Trigger Interrupt flag */ /** * @} */ @@ -564,7 +564,17 @@ typedef struct * using it. * @{ */ +#if defined(LPDMA1) +#define __HAL_RCC_LPDMA1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_LPDMA1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_LPDMA1EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* LPDMA1 */ +#if defined(GPDMA1) #define __HAL_RCC_GPDMA1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN); \ @@ -572,6 +582,7 @@ typedef struct tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN); \ UNUSED(tmpreg); \ } while(0) +#endif /* GPDMA1 */ #define __HAL_RCC_FLASH_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -625,7 +636,12 @@ typedef struct UNUSED(tmpreg); \ } while(0) +#if defined(LPDMA1) +#define __HAL_RCC_LPDMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_LPDMA1EN) +#endif /* LPDMA1 */ +#if defined(GPDMA1) #define __HAL_RCC_GPDMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN) +#endif /* GPDMA1 */ #define __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) #define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) #define __HAL_RCC_TSC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) @@ -670,8 +686,35 @@ typedef struct tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \ UNUSED(tmpreg); \ } while(0) +#if defined(GPIOD) +#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* GPIOD */ +#if defined(GPIOE) +#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* GPIOE */ +#if defined(GPIOG) +#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* GPIOG */ #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -681,6 +724,23 @@ typedef struct UNUSED(tmpreg); \ } while(0) +#if defined(USB_OTG_HS) +#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGEN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_USB_OTG_HS_PHY_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGHSPHYEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGHSPHYEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* USB_OTG_HS */ #define __HAL_RCC_AES_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -734,7 +794,25 @@ typedef struct UNUSED(tmpreg); \ } while(0) +#if defined(OTFDEC1) +#define __HAL_RCC_OTFDEC1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTFDEC1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTFDEC1EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* OTFDEC1 */ +#if defined(XSPI1) +#define __HAL_RCC_XSPI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_XSPI1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_XSPI1EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* XSPI1 */ #define __HAL_RCC_SRAM2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -747,7 +825,20 @@ typedef struct #define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) #define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) #define __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) +#if defined(GPIOD) +#define __HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) +#endif /* GPIOD */ +#if defined(GPIOE) +#define __HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) +#endif /* GPIOE */ +#if defined(GPIOG) +#define __HAL_RCC_GPIOG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) +#endif /* GPIOG */ #define __HAL_RCC_GPIOH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) +#if defined(USB_OTG_HS) +#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGEN) +#define __HAL_RCC_USB_OTG_HS_PHY_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGHSPHYEN) +#endif /* USB_OTG_HS */ #define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) #define __HAL_RCC_HASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) #define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) @@ -758,6 +849,12 @@ typedef struct #define __HAL_RCC_HSEM_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HSEMEN) #endif /* HSEM */ #define __HAL_RCC_PKA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN) +#if defined(OTFDEC1) +#define __HAL_RCC_OTFDEC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTFDEC1EN) +#endif /* OTFDEC1 */ +#if defined(XSPI1) +#define __HAL_RCC_XSPI1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_XSPI1EN) +#endif /* XSPI1 */ #define __HAL_RCC_SRAM2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM2EN) /** * @} @@ -852,6 +949,15 @@ typedef struct } while(0) #endif /* TIM3 */ +#if defined(TIM4) +#define __HAL_RCC_TIM4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* TIM4 */ #if defined(WWDG) #define __HAL_RCC_WWDG_CLK_ENABLE() do { \ @@ -863,6 +969,15 @@ typedef struct } while(0) #endif /* WWDG */ +#if defined(SPI2) +#define __HAL_RCC_SPI2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* SPI2 */ #if defined(USART2) #define __HAL_RCC_USART2_CLK_ENABLE() do { \ @@ -874,6 +989,15 @@ typedef struct } while(0) #endif /* USART2 */ +#if defined(USART3) +#define __HAL_RCC_USART3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* USART3 */ #if defined(I2C1) #define __HAL_RCC_I2C1_CLK_ENABLE() do { \ @@ -885,7 +1009,25 @@ typedef struct } while(0) #endif /* I2C1 */ +#if defined(I2C2) +#define __HAL_RCC_I2C2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* I2C2 */ +#if defined(I2C4) +#define __HAL_RCC_I2C4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* I2C4 */ #if defined(LPTIM2) #define __HAL_RCC_LPTIM2_CLK_ENABLE() do { \ @@ -901,12 +1043,27 @@ typedef struct #if defined(TIM3) #define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) #endif /* TIM3 */ +#if defined(TIM4) +#define __HAL_RCC_TIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) +#endif /* TIM4 */ +#if defined(SPI2) +#define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) +#endif /* SPI2 */ #if defined(USART2) #define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) #endif /* USART2 */ +#if defined(USART3) +#define __HAL_RCC_USART3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) +#endif /* USART3 */ #if defined(I2C1) #define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) #endif /* I2C1 */ +#if defined(I2C2) +#define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) +#endif /* I2C2 */ +#if defined(I2C4) +#define __HAL_RCC_I2C4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) +#endif /* I2C4 */ #if defined(LPTIM2) #define __HAL_RCC_LPTIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) #endif /* LPTIM2 */ @@ -977,6 +1134,15 @@ typedef struct } while(0) #endif /* SAI1 */ +#if defined(USB_DRD_FS) +#define __HAL_RCC_USB_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* USB_DRD_FS */ #if defined(TIM1) #define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) @@ -992,6 +1158,9 @@ typedef struct #if defined(SAI1) #define __HAL_RCC_SAI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) #endif /* SAI1 */ +#if defined(USB_DRD_FS) +#define __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN) +#endif /* USB_DRD_FS */ /** * @} */ @@ -1051,6 +1220,15 @@ typedef struct UNUSED(tmpreg); \ } while(0) +#if defined(VREFBUF) +#define __HAL_RCC_VREF_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB7ENR, RCC_APB7ENR_VREFEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB7ENR, RCC_APB7ENR_VREFEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* VREFBUF */ #define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -1066,6 +1244,9 @@ typedef struct #define __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APB7ENR, RCC_APB7ENR_I2C3EN) #define __HAL_RCC_COMP_CLK_DISABLE() CLEAR_BIT(RCC->APB7ENR, RCC_APB7ENR_COMPEN) #define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB7ENR, RCC_APB7ENR_LPTIM1EN) +#if defined(VREFBUF) +#define __HAL_RCC_VREF_CLK_DISABLE() CLEAR_BIT(RCC->APB7ENR, RCC_APB7ENR_VREFEN) +#endif /* VREFBUF */ #define __HAL_RCC_RTCAPB_CLK_DISABLE() CLEAR_BIT(RCC->APB7ENR, RCC_APB7ENR_RTCAPBEN) /** * @} @@ -1075,7 +1256,12 @@ typedef struct * @brief Check whether the AHB1 peripheral clock is enabled or not. * @{ */ +#if defined(LPDMA1) +#define __HAL_RCC_LPDMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_LPDMA1EN) != 0U) +#endif /* LPDMA1 */ +#if defined(GPDMA1) #define __HAL_RCC_GPDMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN) != 0U) +#endif /* GPDMA1 */ #define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != 0U) #define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != 0U) #define __HAL_RCC_TSC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) != 0U) @@ -1095,7 +1281,20 @@ typedef struct #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) != 0U) #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) != 0U) #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != 0U) +#if defined(GPIOD) +#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) != 0U) +#endif /* GPIOD */ +#if defined(GPIOE) +#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) != 0U) +#endif /* GPIOE */ +#if defined(GPIOG) +#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) != 0U) +#endif /* GPIOG */ #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) != 0U) +#if defined(USB_OTG_HS) +#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGEN) != 0U) +#define __HAL_RCC_USB_OTG_HS_PHY_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGHSPHYEN) != 0U) +#endif /* USB_OTG_HS */ #define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) != 0U) #define __HAL_RCC_HASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) != 0U) #define __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) != 0U) @@ -1106,6 +1305,12 @@ typedef struct #define __HAL_RCC_HSEM_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HSEMEN) != 0U) #endif /* HSEM */ #define __HAL_RCC_PKA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN) != 0U) +#if defined(OTFDEC1) +#define __HAL_RCC_OTFDEC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTFDEC1EN) != 0U) +#endif /* OTFDEC1 */ +#if defined(XSPI1) +#define __HAL_RCC_XSPI1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_XSPI1EN) != 0U) +#endif /* XSPI1 */ #define __HAL_RCC_SRAM2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM2EN) != 0U) /** * @} @@ -1141,15 +1346,30 @@ typedef struct #if defined(TIM3) #define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) != 0U) #endif /* TIM3 */ +#if defined(TIM4) +#define __HAL_RCC_TIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) != 0U) +#endif /* TIM4 */ #if defined(WWDG) #define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) != 0U) #endif /* WWDG */ +#if defined(SPI2) +#define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) != 0U) +#endif /* SPI2 */ #if defined(USART2) #define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != 0U) #endif /* USART2 */ +#if defined(USART3) +#define __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) != 0U) +#endif /* USART3 */ #if defined(I2C1) #define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) != 0U) #endif /* I2C1 */ +#if defined(I2C2) +#define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) != 0U) +#endif /* I2C2 */ +#if defined(I2C4) +#define __HAL_RCC_I2C4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) != 0U) +#endif /* I2C4 */ #if defined(LPTIM2) #define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) != 0U) #endif /* LPTIM2 */ @@ -1175,6 +1395,9 @@ typedef struct #if defined(SAI1) #define __HAL_RCC_SAI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != 0U) #endif /* SAI1 */ +#if defined(USB_DRD_FS) +#define __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN) != 0U) +#endif /* USB_DRD_FS */ /** * @} */ @@ -1189,6 +1412,9 @@ typedef struct #define __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APB7ENR, RCC_APB7ENR_I2C3EN) != 0U) #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB7ENR, RCC_APB7ENR_LPTIM1EN) != 0U) #define __HAL_RCC_COMP_IS_CLK_ENABLED() (READ_BIT(RCC->APB7ENR, RCC_APB7ENR_COMPEN) != 0U) +#if defined(VREFBUF) +#define __HAL_RCC_VREF_IS_CLK_ENABLED() (READ_BIT(RCC->APB7ENR, RCC_APB7ENR_VREFEN) != 0U) +#endif /* VREFBUF */ #define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() (READ_BIT(RCC->APB7ENR, RCC_APB7ENR_RTCAPBEN) != 0U) /** * @} @@ -1199,12 +1425,22 @@ typedef struct * @{ */ #define __HAL_RCC_AHB1_FORCE_RESET() WRITE_REG(RCC->AHB1RSTR, 0xFFFFFFFFU) +#if defined(LPDMA1) +#define __HAL_RCC_LPDMA1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_LPDMA1RST) +#endif /* LPDMA1 */ +#if defined(GPDMA1) #define __HAL_RCC_GPDMA1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPDMA1RST) +#endif /* GPDMA1 */ #define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) #define __HAL_RCC_TSC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST) #define __HAL_RCC_AHB1_RELEASE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x00000000U) +#if defined(LPDMA1) +#define __HAL_RCC_LPDMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_LPDMA1RST) +#endif /* LPDMA1 */ +#if defined(GPDMA1) #define __HAL_RCC_GPDMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPDMA1RST) +#endif /* GPDMA1 */ #define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) #define __HAL_RCC_TSC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST) /** @@ -1219,7 +1455,19 @@ typedef struct #define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST) #define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST) #define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST) +#if defined(GPIOD) +#define __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST) +#endif /* GPIOD */ +#if defined(GPIOE) +#define __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST) +#endif /* GPIOE */ +#if defined(GPIOG) +#define __HAL_RCC_GPIOG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST) +#endif /* GPIOG */ #define __HAL_RCC_GPIOH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST) +#if defined(USB_OTG_HS) +#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGRST) +#endif /* USB_OTG_HS */ #define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST) #define __HAL_RCC_HASH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HASHRST) #define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST) @@ -1230,11 +1478,29 @@ typedef struct #define __HAL_RCC_HSEM_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HSEMRST) #endif /* HSEM */ #define __HAL_RCC_PKA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_PKARST) +#if defined(OTFDEC1) +#define __HAL_RCC_OTFDEC1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTFDEC1RST) +#endif /* OTFDEC1 */ +#if defined(XSPI1) +#define __HAL_RCC_XSPI1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_XSPI1RST) +#endif /* XSPI1 */ #define __HAL_RCC_AHB2_RELEASE_RESET() WRITE_REG(RCC->AHB2RSTR, 0x00000000U) #define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST) #define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST) #define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST) +#if defined(GPIOD) +#define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST) +#endif /* GPIOD */ +#if defined(GPIOE) +#define __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST) +#endif /* GPIOE */ +#if defined(GPIOG) +#define __HAL_RCC_GPIOG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST) +#endif /* GPIOG */ #define __HAL_RCC_GPIOH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST) +#if defined(USB_OTG_HS) +#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGRST) +#endif /* USB_OTG_HS */ #define __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST) #define __HAL_RCC_HASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HASHRST) #define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST) @@ -1245,6 +1511,12 @@ typedef struct #define __HAL_RCC_HSEM_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HSEMRST) #endif /* HSEM */ #define __HAL_RCC_PKA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_PKARST) +#if defined(OTFDEC1) +#define __HAL_RCC_OTFDEC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTFDEC1RST) +#endif /* OTFDEC1 */ +#if defined(XSPI1) +#define __HAL_RCC_XSPI1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_XSPI1RST) +#endif /* XSPI1 */ /** * @} */ @@ -1293,12 +1565,27 @@ typedef struct #if defined(TIM3) #define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST) #endif /* TIM3 */ +#if defined(TIM4) +#define __HAL_RCC_TIM4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST) +#endif /* TIM4 */ +#if defined(SPI2) +#define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST) +#endif /* SPI2 */ #if defined(USART2) #define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST) #endif /* USART2 */ +#if defined(USART3) +#define __HAL_RCC_USART3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST) +#endif /* USART3 */ #if defined(I2C1) #define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST) #endif /* I2C1 */ +#if defined(I2C2) +#define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST) +#endif /* I2C2 */ +#if defined(I2C4) +#define __HAL_RCC_I2C4_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST) +#endif /* I2C4 */ #if defined(LPTIM2) #define __HAL_RCC_LPTIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST) #endif /* LPTIM2 */ @@ -1311,12 +1598,27 @@ typedef struct #if defined(TIM3) #define __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST) #endif /* TIM3 */ +#if defined(TIM4) +#define __HAL_RCC_TIM4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST) +#endif /* TIM4 */ +#if defined(SPI2) +#define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST) +#endif /* SPI2 */ #if defined(USART2) #define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST) #endif /* USART2 */ +#if defined(USART3) +#define __HAL_RCC_USART3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST) +#endif /* USART3 */ #if defined(I2C1) #define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST) #endif /* I2C1 */ +#if defined(I2C2) +#define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST) +#endif /* I2C2 */ +#if defined(I2C4) +#define __HAL_RCC_I2C4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST) +#endif /* I2C4 */ #if defined(LPTIM2) #define __HAL_RCC_LPTIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST) #endif /* LPTIM2 */ @@ -1343,6 +1645,9 @@ typedef struct #if defined(SAI1) #define __HAL_RCC_SAI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) #endif /* SAI1 */ +#if defined(USB_DRD_FS) +#define __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USBRST) +#endif /* USB_DRD_FS */ #define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00000000U) #define __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST) @@ -1357,6 +1662,9 @@ typedef struct #if defined(SAI1) #define __HAL_RCC_SAI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) #endif /* SAI1 */ +#if defined(USB_DRD_FS) +#define __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USBRST) +#endif /* USB_DRD_FS */ /** * @} */ @@ -1372,6 +1680,9 @@ typedef struct #define __HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APB7RSTR, RCC_APB7RSTR_I2C3RST) #define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB7RSTR, RCC_APB7RSTR_LPTIM1RST) #define __HAL_RCC_COMP_FORCE_RESET() SET_BIT(RCC->APB7RSTR, RCC_APB7RSTR_COMPRST) +#if defined(VREFBUF) +#define __HAL_RCC_VREF_FORCE_RESET() SET_BIT(RCC->APB7RSTR, RCC_APB7RSTR_VREFRST) +#endif /* VREFBUF */ #define __HAL_RCC_APB7_RELEASE_RESET() WRITE_REG(RCC->APB7RSTR, 0x00000000U) #define __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APB7RSTR, RCC_APB7RSTR_SYSCFGRST) @@ -1380,6 +1691,9 @@ typedef struct #define __HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APB7RSTR, RCC_APB7RSTR_I2C3RST) #define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB7RSTR, RCC_APB7RSTR_LPTIM1RST) #define __HAL_RCC_COMP_RELEASE_RESET() CLEAR_BIT(RCC->APB7RSTR, RCC_APB7RSTR_COMPRST) +#if defined(VREFBUF) +#define __HAL_RCC_VREF_RELEASE_RESET() CLEAR_BIT(RCC->APB7RSTR, RCC_APB7RSTR_VREFRST) +#endif /* VREFBUF */ /** * @} */ @@ -1393,7 +1707,12 @@ typedef struct * is enabled only when a peripheral requests AHB clock. * @{ */ +#if defined(LPDMA1) +#define __HAL_RCC_LPDMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_LPDMA1SMEN) +#endif /* LPDMA1 */ +#if defined(GPDMA1) #define __HAL_RCC_GPDMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GPDMA1SMEN) +#endif /* GPDMA1 */ #define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) #define __HAL_RCC_TSC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) @@ -1404,7 +1723,12 @@ typedef struct #define __HAL_RCC_ICACHE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_ICACHESMEN) #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) +#if defined(LPDMA1) +#define __HAL_RCC_LPDMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_LPDMA1SMEN) +#endif /* LPDMA1 */ +#if defined(GPDMA1) #define __HAL_RCC_GPDMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GPDMA1SMEN) +#endif /* GPDMA1 */ #define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) #define __HAL_RCC_TSC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) @@ -1430,7 +1754,20 @@ typedef struct #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) +#if defined(GPIOD) +#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) +#endif /* GPIOD */ +#if defined(GPIOE) +#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) +#endif /* GPIOE */ +#if defined(GPIOG) +#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) +#endif /* GPIOG */ #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) +#if defined(USB_OTG_HS) +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGSMEN) +#define __HAL_RCC_USB_OTG_HS_PHY_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGHSPHYSMEN) +#endif /* USB_OTG_HS */ #define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) @@ -1438,12 +1775,31 @@ typedef struct #define __HAL_RCC_SAES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SAESSMEN) #endif /* SAES */ #define __HAL_RCC_PKA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_PKASMEN) +#if defined(OTFDEC1) +#define __HAL_RCC_OTFDEC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTFDEC1SMEN) +#endif /* OTFDEC1 */ +#if defined(XSPI1) +#define __HAL_RCC_XSPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_XSPI1SMEN) +#endif /* XSPI1 */ #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) +#if defined(GPIOD) +#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) +#endif /* GPIOD */ +#if defined(GPIOE) +#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) +#endif /* GPIOE */ +#if defined(GPIOG) +#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) +#endif /* GPIOG */ #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) +#if defined(USB_OTG_HS) +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGSMEN) +#define __HAL_RCC_USB_OTG_HS_PHY_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGHSPHYSMEN) +#endif /* USB_OTG_HS */ #define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) @@ -1451,6 +1807,12 @@ typedef struct #define __HAL_RCC_SAES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SAESSMEN) #endif /* SAES */ #define __HAL_RCC_PKA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_PKASMEN) +#if defined(OTFDEC1) +#define __HAL_RCC_OTFDEC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTFDEC1SMEN) +#endif /* OTFDEC1 */ +#if defined(XSPI1) +#define __HAL_RCC_XSPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_XSPI1SMEN) +#endif /* XSPI1 */ #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) /** * @} @@ -1507,15 +1869,30 @@ typedef struct #if defined(TIM3) #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) #endif /* TIM3 */ +#if defined(TIM4) +#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) +#endif /* TIM4 */ #if defined(WWDG) #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) #endif /* WWDG */ +#if defined(SPI2) +#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) +#endif /* SPI2 */ #if defined(USART2) #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) #endif /* USART2 */ +#if defined(USART3) +#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) +#endif /* USART3 */ #if defined(I2C1) #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) #endif /* I2C1 */ +#if defined(I2C2) +#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) +#endif /* I2C2 */ +#if defined(I2C4) +#define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) +#endif /* I2C4 */ #if defined(LPTIM2) #define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) #endif /* LPTIM2 */ @@ -1524,15 +1901,30 @@ typedef struct #if defined(TIM3) #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) #endif /* TIM3 */ +#if defined(TIM4) +#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) +#endif /* TIM4 */ +#if defined(SPI2) +#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) +#endif /* SPI2 */ #if defined(WWDG) #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) #endif /* WWDG */ #if defined(USART2) #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) #endif /* USART2 */ +#if defined(USART3) +#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) +#endif /* USART3 */ #if defined(I2C1) #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) #endif /* I2C1 */ +#if defined(I2C2) +#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) +#endif /* I2C2 */ +#if defined(I2C4) +#define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) +#endif /* I2C4 */ #if defined(LPTIM2) #define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) #endif /* LPTIM2 */ @@ -1563,6 +1955,9 @@ typedef struct #if defined(SAI1) #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) #endif /* SAI1 */ +#if defined(USB_DRD_FS) +#define __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USBSMEN) +#endif /* USB_DRD_FS */ #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) #if defined(SPI1) @@ -1576,6 +1971,9 @@ typedef struct #if defined(SAI1) #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) #endif /* SAI1 */ +#if defined(USB_DRD_FS) +#define __HAL_RCC_USB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USBSMEN) +#endif /* USB_DRD_FS */ /** * @} */ @@ -1596,6 +1994,9 @@ typedef struct #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB7SMENR, RCC_APB7SMENR_LPTIM1SMEN) #define __HAL_RCC_COMP_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB7SMENR, RCC_APB7SMENR_COMPSMEN) #define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB7SMENR, RCC_APB7SMENR_RTCAPBSMEN) +#if defined(VREFBUF) +#define __HAL_RCC_VREF_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB7SMENR, RCC_APB7SMENR_VREFSMEN) +#endif /* VREFBUF */ #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB7SMENR, RCC_APB7SMENR_SYSCFGSMEN) #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB7SMENR, RCC_APB7SMENR_SPI3SMEN) @@ -1603,6 +2004,9 @@ typedef struct #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB7SMENR, RCC_APB7SMENR_I2C3SMEN) #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB7SMENR, RCC_APB7SMENR_LPTIM1SMEN) #define __HAL_RCC_COMP_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB7SMENR, RCC_APB7SMENR_COMPSMEN) +#if defined(VREFBUF) +#define __HAL_RCC_VREF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB7SMENR, RCC_APB7SMENR_VREFSMEN) +#endif /* VREFBUF */ #define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB7SMENR, RCC_APB7SMENR_RTCAPBSMEN) /** * @} @@ -1612,7 +2016,12 @@ typedef struct * @brief Check whether the AHB1 peripheral clock during Low Power (Sleep) is enabled or not. * @{ */ +#if defined(LPDMA1) +#define __HAL_RCC_LPDMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_LPDMA1SMEN) != 0U) +#endif /* LPDMA1 */ +#if defined(GPDMA1) #define __HAL_RCC_GPDMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GPDMA1SMEN) != 0U) +#endif /* GPDMA1 */ #define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) != 0U) #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) != 0U) #define __HAL_RCC_TSC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) != 0U) @@ -1633,7 +2042,20 @@ typedef struct #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) != 0U) #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) != 0U) #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) != 0U) +#if defined(GPIOD) +#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) != 0U) +#endif /* GPIOD */ +#if defined(GPIOE) +#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) != 0U) +#endif /* GPIOE */ +#if defined(GPIOG) +#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) != 0U) +#endif /* GPIOG */ #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) != 0U) +#if defined(USB_OTG_HS) +#define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGSMEN) != 0U) +#define __HAL_RCC_USB_OTG_HS_PHY_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGHSPHYSMEN) != 0U) +#endif /* USB_OTG_HS */ #define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) != 0U) #define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) != 0U) #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) != 0U) @@ -1641,6 +2063,12 @@ typedef struct #define __HAL_RCC_SAES_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SAESSMEN) != 0U) #endif /* SAES */ #define __HAL_RCC_PKA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_PKASMEN) != 0U) +#if defined(OTFDEC1) +#define __HAL_RCC_OTFDEC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTFDEC1SMEN) != 0U) +#endif /* OTFDEC1 */ +#if defined(XSPI1) +#define __HAL_RCC_XSPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_XSPI1SMEN) != 0U) +#endif /* XSPI1 */ #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) != 0U) /** * @} @@ -1676,15 +2104,30 @@ typedef struct #if defined(TIM3) #define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) != 0U) #endif /* TIM3 */ +#if defined(TIM4) +#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) != 0U) +#endif /* TIM4 */ #if defined(WWDG) #define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) != 0U) #endif /* WWDG */ +#if defined(SPI2) +#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) != 0U) +#endif /* SPI2 */ #if defined(USART2) #define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) != 0U) #endif /* USART2 */ +#if defined(USART3) +#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) != 0U) +#endif /* USART3 */ #if defined(I2C1) #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) != 0U) #endif /* I2C1 */ +#if defined(I2C2) +#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) != 0U) +#endif /* I2C2 */ +#if defined(I2C4) +#define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) != 0U) +#endif /* I2C4 */ #if defined(LPTIM2) #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) != 0U) #endif /* LPTIM2 */ @@ -1710,6 +2153,9 @@ typedef struct #if defined(SAI1) #define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) != 0U) #endif /* SAI1 */ +#if defined(USB_DRD_FS) +#define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USBSMEN) != 0U) +#endif /* USB_DRD_FS */ /** * @} */ @@ -1724,6 +2170,9 @@ typedef struct #define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB7SMENR, RCC_APB7SMENR_I2C3SMEN) != 0U) #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB7SMENR, RCC_APB7SMENR_LPTIM1SMEN) != 0U) #define __HAL_RCC_COMP_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB7SMENR, RCC_APB7SMENR_COMPSMEN) != 0U) +#if defined(VREFBUF) +#define __HAL_RCC_VREF_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB7SMENR, RCC_APB7SMENR_VREFSMEN) != 0U) +#endif /* VREFBUF */ #define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB7SMENR, RCC_APB7SMENR_RTCAPBSMEN) != 0U) /** * @} @@ -2227,8 +2676,8 @@ typedef struct */ #if defined(RCC_CCIPR2_ASSEL) #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) ((((__INTERRUPT__) >> 5U) == 0U) ? \ - WRITE_REG(RCC->CICR,1U << ((__INTERRUPT__) & RCC_FLAG_MASK)) : \ - CLEAR_BIT(RCC->ASSR,1U << ((__INTERRUPT__) & RCC_FLAG_MASK))) + WRITE_REG(RCC->CICR,1UL << ((__INTERRUPT__) & RCC_FLAG_MASK)) : \ + CLEAR_BIT(RCC->ASSR,1UL << ((__INTERRUPT__) & RCC_FLAG_MASK))) #else #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) WRITE_REG(RCC->CICR, (__INTERRUPT__)) #endif /* RCC_CCIPR2_ASSEL */ @@ -2253,8 +2702,8 @@ typedef struct */ #if defined(RCC_CCIPR2_ASSEL) #define __HAL_RCC_GET_IT(__INTERRUPT__) ((((__INTERRUPT__) >> 5U) == 0U) ? \ - ((RCC->CIFR & (1U << ((__INTERRUPT__) & RCC_FLAG_MASK))) == (1U << ((__INTERRUPT__) & RCC_FLAG_MASK))) : \ - ((RCC->ASSR & (1U << ((__INTERRUPT__) & RCC_FLAG_MASK))) == (1U << ((__INTERRUPT__) & RCC_FLAG_MASK)))) + ((RCC->CIFR & (1UL << ((__INTERRUPT__) & RCC_FLAG_MASK))) == (1UL << ((__INTERRUPT__) & RCC_FLAG_MASK))) : \ + ((RCC->ASSR & (1UL << ((__INTERRUPT__) & RCC_FLAG_MASK))) == (1UL << ((__INTERRUPT__) & RCC_FLAG_MASK)))) #else #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__)) #endif /* RCC_CCIPR2_ASSEL */ @@ -2310,13 +2759,13 @@ typedef struct /* Defines used for Flags */ -#define CR_REG_INDEX (1U) -#define BDCR1_REG_INDEX (2U) -#define CSR_REG_INDEX (3U) +#define CR_REG_INDEX (1UL) +#define BDCR1_REG_INDEX (2UL) +#define CSR_REG_INDEX (3UL) #if defined(RCC_CCIPR2_ASSEL) /* Defines used for Interrupt Flags */ -#define CIFR_REG_INDEX (0U) -#define ASSR_REG_INDEX (1U) +#define CIFR_REG_INDEX (0UL) +#define ASSR_REG_INDEX (1UL) #endif /* RCC_CCIPR2_ASSEL */ #define RCC_FLAG_MASK (0x1FU) diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rcc_ex.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rcc_ex.h index b29a1c54b5..5c362d98d6 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rcc_ex.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rcc_ex.h @@ -69,14 +69,30 @@ typedef struct This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ #endif +#if defined (USART3) + uint32_t Usart3ClockSelection; /*!< Specifies USART3 clock source. + This parameter can be a value of @ref RCCEx_USART3_Clock_Source */ +#endif #if defined (I2C1) uint32_t I2c1ClockSelection; /*!< Specifies I2C1 clock source. This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */ #endif +#if defined (I2C2) + uint32_t I2c2ClockSelection; /*!< Specifies I2C2 clock source. + This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ +#endif +#if defined (I2C4) + uint32_t I2c4ClockSelection; /*!< Specifies I2C4 clock source. + This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */ +#endif +#if defined (SPI2) + uint32_t Spi2ClockSelection; /*!< Specifies SPI2 clock source + This parameter can be a value of @ref RCCEx_SPI2_Clock_Source */ +#endif #if defined (LPTIM2) uint32_t Lptim2ClockSelection; /*!< Specifies LPTIM2 clock source. @@ -102,6 +118,10 @@ typedef struct uint32_t RngClockSelection; /*!< Specifies RNG clock source This parameter can be a value of @ref RCCEx_RNG_Clock_Source */ +#if defined (USB_OTG_HS) + uint32_t UsbOtgHsPhyClockSelection; /*!< Specifies USB OTG HS PHY clock source. + This parameter can be a value of @ref RCCEx_USBOTGHSPHY_Clock_Source */ +#endif #if defined (RCC_CCIPR2_ASSEL) uint32_t AudioSyncClockSelection; /*!< Specifies Audio Sync clock source. @@ -184,6 +204,21 @@ uint32_t CompareValue; /*!< Compare value. #define RCC_PERIPHCLK_ADC 0x00002000U #define RCC_PERIPHCLK_RTC 0x00004000U #define RCC_PERIPHCLK_RADIOST 0x00008000U +#if defined (USART3) +#define RCC_PERIPHCLK_USART3 0x00010000U +#endif +#if defined (I2C2) +#define RCC_PERIPHCLK_I2C2 0x00020000U +#endif +#if defined (I2C4) +#define RCC_PERIPHCLK_I2C4 0x00040000U +#endif +#if defined (SPI2) +#define RCC_PERIPHCLK_SPI2 0x00080000U +#endif +#if defined (USB_OTG_HS) +#define RCC_PERIPHCLK_USBOTGHSPHY 0x00100000U +#endif #if defined (RCC_CCIPR2_ASSEL) #define RCC_PERIPHCLK_AUDIOSYNC 0x00200000U #endif @@ -215,6 +250,18 @@ uint32_t CompareValue; /*!< Compare value. */ #endif +#if defined (USART3) +/** @defgroup RCCEx_USART3_Clock_Source USART3 Clock Source + * @{ + */ +#define RCC_USART3CLKSOURCE_PCLK1 0x00000000U +#define RCC_USART3CLKSOURCE_SYSCLK RCC_CCIPR1_USART3SEL_0 +#define RCC_USART3CLKSOURCE_HSI RCC_CCIPR1_USART3SEL_1 +#define RCC_USART3CLKSOURCE_LSE (RCC_CCIPR1_USART3SEL_0 | RCC_CCIPR1_USART3SEL_1) +/** + * @} + */ +#endif #if defined (I2C1) /** @defgroup RCCEx_I2C1_Clock_Source I2C1 Clock Source @@ -228,8 +275,41 @@ uint32_t CompareValue; /*!< Compare value. */ #endif +#if defined (I2C2) +/** @defgroup RCCEx_I2C2_Clock_Source I2C2 Clock Source + * @{ + */ +#define RCC_I2C2CLKSOURCE_PCLK1 0x00000000U +#define RCC_I2C2CLKSOURCE_SYSCLK RCC_CCIPR1_I2C2SEL_0 +#define RCC_I2C2CLKSOURCE_HSI RCC_CCIPR1_I2C2SEL_1 +/** + * @} + */ +#endif +#if defined (I2C4) +/** @defgroup RCCEx_I2C4_Clock_Source I2C4 Clock Source + * @{ + */ +#define RCC_I2C4CLKSOURCE_PCLK1 0x00000000U +#define RCC_I2C4CLKSOURCE_SYSCLK RCC_CCIPR1_I2C4SEL_0 +#define RCC_I2C4CLKSOURCE_HSI RCC_CCIPR1_I2C4SEL_1 +/** + * @} + */ +#endif +#if defined (SPI2) +/** @defgroup RCCEx_SPI2_Clock_Source SPI2 Clock Source + * @{ + */ +#define RCC_SPI2CLKSOURCE_PCLK1 0x00000000U +#define RCC_SPI2CLKSOURCE_SYSCLK RCC_CCIPR1_SPI2SEL_0 +#define RCC_SPI2CLKSOURCE_HSI RCC_CCIPR1_SPI2SEL_1 +/** + * @} + */ +#endif #if defined (LPTIM2) /** @defgroup RCCEx_LPTIM2_Clock_Source LPTIM2 Clock Source @@ -262,6 +342,9 @@ uint32_t CompareValue; /*!< Compare value. #define RCC_SYSTICKCLKSOURCE_HCLK_DIV8 0x00000000U #define RCC_SYSTICKCLKSOURCE_LSI RCC_CCIPR1_SYSTICKSEL_0 #define RCC_SYSTICKCLKSOURCE_LSE RCC_CCIPR1_SYSTICKSEL_1 +#if !defined (STM32WBA50xx) && !defined (STM32WBA52xx) && !defined (STM32WBA54xx) && !defined (STM32WBA55xx) && !defined (STM32WBA5Mxx) +#define RCC_SYSTICKCLKSOURCE_HSI_DIV4 (RCC_CCIPR1_SYSTICKSEL_1 | RCC_CCIPR1_SYSTICKSEL_0) +#endif /** * @} */ @@ -300,6 +383,18 @@ uint32_t CompareValue; /*!< Compare value. * @} */ +#if defined (USB_OTG_HS) +/** @defgroup RCCEx_USBOTGHSPHY_Clock_Source USB OTGHS PHY Clock Source + * @{ + */ +#define RCC_USBOTGHSPHYCLKSOURCE_HSE 0x00000000U +#define RCC_USBOTGHSPHYCLKSOURCE_PLL1P RCC_CCIPR2_OTGHSSEL_0 +#define RCC_USBOTGHSPHYCLKSOURCE_HSE_DIV2 RCC_CCIPR2_OTGHSSEL_1 +#define RCC_USBOTGHSPHYCLKSOURCE_PLL1P_DIV2 (RCC_CCIPR2_OTGHSSEL_1 | RCC_CCIPR2_OTGHSSEL_0) +/** + * @} + */ +#endif #if defined (RCC_CCIPR2_ASSEL) /** @defgroup RCCEx_AudioSync_Clock_Source Audio Sync Clock Source @@ -482,6 +577,28 @@ uint32_t CompareValue; /*!< Compare value. #define __HAL_RCC_GET_USART2_SOURCE() READ_BIT(RCC->CCIPR1, RCC_CCIPR1_USART2SEL) #endif +#if defined (USART3) +/** @brief Macro to configure the USART3 clock (USART3CLK). + * @param __USART3_CLKSOURCE__ specifies the USART3 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock + * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock + * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock + * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock + * @retval None + */ +#define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_USART3SEL, (__USART3_CLKSOURCE__)) + +/** @brief Macro to get the USART3 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock + * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock + * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock + * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock + */ +#define __HAL_RCC_GET_USART3_SOURCE() READ_BIT(RCC->CCIPR1, RCC_CCIPR1_USART3SEL) +#endif #if defined (I2C1) /** @brief Macro to configure the I2C1 clock (I2C1CLK). @@ -504,8 +621,67 @@ uint32_t CompareValue; /*!< Compare value. #define __HAL_RCC_GET_I2C1_SOURCE() READ_BIT(RCC->CCIPR1, RCC_CCIPR1_I2C1SEL) #endif +#if defined (I2C2) +/** @brief Macro to configure the I2C2 clock (I2C2CLK). + * @param __I2C2_CLKSOURCE__ specifies the I2C2 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock + * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock + * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock + * @retval None + */ +#define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_I2C2SEL, (__I2C2_CLKSOURCE__)) +/** @brief Macro to get the I2C2 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock + * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock + * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock + */ +#define __HAL_RCC_GET_I2C2_SOURCE() READ_BIT(RCC->CCIPR1, RCC_CCIPR1_I2C2SEL) +#endif +#if defined (I2C4) +/** @brief Macro to configure the I2C4 clock (I2C4CLK). + * @param __I2C4_CLKSOURCE__ specifies the I2C4 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_I2C4CLKSOURCE_PCLK1 PCLK1 selected as I2C4 clock + * @arg @ref RCC_I2C4CLKSOURCE_SYSCLK System Clock selected as I2C4 clock + * @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock + * @retval None + */ +#define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_I2C4SEL, (__I2C4_CLKSOURCE__)) + +/** @brief Macro to get the I2C4 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_I2C4CLKSOURCE_PCLK1 PCLK1 selected as I2C4 clock + * @arg @ref RCC_I2C4CLKSOURCE_SYSCLK System Clock selected as I2C4 clock + * @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock + */ +#define __HAL_RCC_GET_I2C4_SOURCE() READ_BIT(RCC->CCIPR1, RCC_CCIPR1_I2C4SEL) +#endif + +#if defined (SPI2) +/** @brief macro to configure the SPI2 clock source. + * @param __SPI2_CLKSOURCE__ specifies the SPI2 clock source. + * This parameter can be one of the following values: + * @arg RCC_SPI2CLKSOURCE_PCLK2 : PCLK2 Clock selected as SPI2 clock + * @arg RCC_SPI2CLKSOURCE_SYSCLK : SYSCLK Clock selected as SPI2 clock + * @arg RCC_SPI2CLKSOURCE_HSI : HSI Clock selected as SPI2 clock + */ +#define __HAL_RCC_SPI2_CONFIG(__SPI2_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_SPI2SEL, (__SPI2_CLKSOURCE__)) + +/** @brief macro to get the SPI2 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SPI2CLKSOURCE_PCLK2 : PCLK2 Clock used as SPI2 clock + * @arg RCC_SPI2CLKSOURCE_SYSCLK : SYSCLK Clock used as SPI2 clock + * @arg RCC_SPI2CLKSOURCE_HSI : HSI Clock used as SPI2 clock + */ +#define __HAL_RCC_GET_SPI2_SOURCE() READ_BIT(RCC->CCIPR1, RCC_CCIPR1_SPI2SEL) +#endif #if defined (LPTIM2) /** @brief Macro to configure the LPTIM2 clock (LPTIM2CLK). @@ -555,6 +731,8 @@ uint32_t CompareValue; /*!< Compare value. * @arg RCC_SYSTICKCLKSOURCE_HCLK_DIV8 : HCLK divided by 8 Clock selected as SYSTICK clock * @arg RCC_SYSTICKCLKSOURCE_LSI : LSI Clock selected as SYSTICK clock * @arg RCC_SYSTICKCLKSOURCE_LSE : LSE Clock selected as SYSTICK clock + * @arg RCC_SYSTICKCLKSOURCE_HSI_DIV4 : HSI divided by 4 Clock selected as SYSTICK clock (1) + * @note (1) Source is not available on all devices */ #define __HAL_RCC_SYSTICK_CONFIG(__SYSTICK_CLKSOURCE__) \ MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_SYSTICKSEL, (__SYSTICK_CLKSOURCE__)) @@ -564,6 +742,8 @@ uint32_t CompareValue; /*!< Compare value. * @arg RCC_SYSTICKCLKSOURCE_HCLK_DIV8 : HCLK divided by 8 Clock selected as SYSTICK clock * @arg RCC_SYSTICKCLKSOURCE_LSI : LSI Clock selected as SYSTICK clock * @arg RCC_SYSTICKCLKSOURCE_LSE : LSE Clock selected as SYSTICK clock + * @arg RCC_SYSTICKCLKSOURCE_HSI_DIV4 : HSI divided by 4 Clock selected as SYSTICK clock (1) + * @note (1) Source is not available on all devices */ #define __HAL_RCC_GET_SYSTICK_SOURCE() READ_BIT(RCC->CCIPR1, RCC_CCIPR1_SYSTICKSEL) @@ -609,6 +789,29 @@ uint32_t CompareValue; /*!< Compare value. #define __HAL_RCC_GET_SAI1_SOURCE() READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SAI1SEL) #endif +#if defined (USB_OTG_HS) +/** @brief Macro to configure the USB OTG HS PHY clock (USBOTGHSPHYCLK). + * @param __USBOTGHSPHY_CLKSOURCE__ specifies the USBOTGHSPHY clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_USBOTGHSPHYCLKSOURCE_HSE HSE selected as USBOTGHSPHY clock + * @arg @ref RCC_USBOTGHSPHYCLKSOURCE_PLL1P PLL1P selected as USBOTGHSPHY clock + * @arg @ref RCC_USBOTGHSPHYCLKSOURCE_HSE_DIV2 HSE divided by 2 selected as USBOTGHSPHY clock + * @arg @ref RCC_USBOTGHSPHYCLKSOURCE_PLL1P_DIV2 PLL1P divided by 2 selected as USBOTGHSPHY clock + * @retval None + */ +#define __HAL_RCC_USB_OTG_HS_PHY_CONFIG(__USBOTGHSPHY_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_OTGHSSEL, (__USBOTGHSPHY_CLKSOURCE__)) + +/** @brief Macro to get the USB OTG HS PHY clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_USBOTGHSPHYCLKSOURCE_HSE HSE selected as USBOTGHSPHY clock + * @arg @ref RCC_USBOTGHSPHYCLKSOURCE_PLL1P PLL1P selected as USBOTGHSPHY clock + * @arg @ref RCC_USBOTGHSPHYCLKSOURCE_HSE_DIV2 HSE divided by 2 selected as USBOTGHSPHY clock + * @arg @ref RCC_USBOTGHSPHYCLKSOURCE_PLL1P_DIV2 PLL1P divided by 2 selected as USBOTGHSPHY clock + */ +#define __HAL_RCC_GET_USB_OTG_HS_PHY_SOURCE() \ + READ_BIT(RCC->CCIPR2, RCC_CCIPR2_OTGHSSEL) +#endif #if defined (RCC_CCIPR2_ASSEL) /** @brief macro to configure the Audio Sync clock source. @@ -874,6 +1077,22 @@ uint32_t HAL_RCCEx_GetAudioSyncCaptureValue(void); RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_I2C3 | \ RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_RTC | \ RCC_PERIPHCLK_RADIOST) +#elif defined (STM32WBA62xx) || defined (STM32WBA64xx) || defined (STM32WBA65xx) || defined (STM32WBA6Mxx) +#define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_I2C1 | \ + RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SYSTICK | \ + RCC_PERIPHCLK_TIMIC | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_RNG | \ + RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_I2C3 | \ + RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_RTC | \ + RCC_PERIPHCLK_RADIOST | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_I2C2 | \ + RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_USBOTGHSPHY | \ + RCC_PERIPHCLK_AUDIOSYNC) +#elif defined (STM32WBA63xx) +#define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_I2C1 | \ + RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SYSTICK | \ + RCC_PERIPHCLK_TIMIC | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_RNG | \ + RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_I2C3 | \ + RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_RTC | \ + RCC_PERIPHCLK_RADIOST | RCC_PERIPHCLK_AUDIOSYNC) #endif /** * @} @@ -898,6 +1117,12 @@ uint32_t HAL_RCCEx_GetAudioSyncCaptureValue(void); ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE)) #endif +#if defined(USART3) +#define IS_RCC_USART3CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE)) +#endif #if defined(I2C1) #define IS_RCC_I2C1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \ @@ -905,8 +1130,23 @@ uint32_t HAL_RCCEx_GetAudioSyncCaptureValue(void); ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI)) #endif +#if defined(I2C2) +#define IS_RCC_I2C2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_I2C2CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI)) +#endif +#if defined(I2C4) +#define IS_RCC_I2C4CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C4CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_I2C4CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_I2C4CLKSOURCE_HSI)) +#endif +#if defined (SPI2) +#define IS_RCC_SPI2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SPI2CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_SPI2CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_SPI2CLKSOURCE_HSI)) +#endif #if defined (LPTIM2) #define IS_RCC_LPTIM2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK1) || \ @@ -926,9 +1166,16 @@ uint32_t HAL_RCCEx_GetAudioSyncCaptureValue(void); ((__SOURCE__) == RCC_SPI1CLKSOURCE_HSI)) #endif +#if !defined (STM32WBA50xx) && !defined (STM32WBA52xx) && !defined (STM32WBA54xx) && !defined (STM32WBA55xx) && !defined (STM32WBA5Mxx) +#define IS_RCC_SYSTICKCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSTICKCLKSOURCE_HCLK_DIV8) || \ + ((__SOURCE__) == RCC_SYSTICKCLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_SYSTICKCLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_SYSTICKCLKSOURCE_HSI_DIV4)) +#else #define IS_RCC_SYSTICKCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSTICKCLKSOURCE_HCLK_DIV8) || \ ((__SOURCE__) == RCC_SYSTICKCLKSOURCE_LSI) || \ ((__SOURCE__) == RCC_SYSTICKCLKSOURCE_LSE)) +#endif #define IS_RCC_TIMICCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_TIMICCLKSOURCE_HSI) || \ ((__SOURCE__) == RCC_TIMICCLKSOURCE_HSI_DIV256)) @@ -946,6 +1193,12 @@ uint32_t HAL_RCCEx_GetAudioSyncCaptureValue(void); ((__SOURCE__) == RCC_RNGCLKSOURCE_HSI) || \ ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL1Q)) +#if defined (USB_OTG_HS) +#define IS_RCC_USBOTGHSPHYCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USBOTGHSPHYCLKSOURCE_HSE) || \ + ((__SOURCE__) == RCC_USBOTGHSPHYCLKSOURCE_PLL1P) || \ + ((__SOURCE__) == RCC_USBOTGHSPHYCLKSOURCE_HSE_DIV2) || \ + ((__SOURCE__) == RCC_USBOTGHSPHYCLKSOURCE_PLL1P_DIV2)) +#endif #if defined (RCC_CCIPR2_ASSEL) #define IS_RCC_ASCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_ASCLKSOURCE_PLL1P) || \ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rng.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rng.h index c6e13320e4..c37b7dac22 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rng.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rng.h @@ -178,6 +178,7 @@ typedef void (*pRNG_ReadyDataCallbackTypeDef)(RNG_HandleTypeDef *hrng, uint32_t #define HAL_RNG_ERROR_BUSY 0x00000004U /*!< Busy error */ #define HAL_RNG_ERROR_SEED 0x00000008U /*!< Seed error */ #define HAL_RNG_ERROR_CLOCK 0x00000010U /*!< Clock error */ +#define HAL_RNG_ERROR_RECOVERSEED 0x00000020U /*!< Recover Seed error */ /** * @} */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rtc_ex.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rtc_ex.h index 3ff0e43461..66a8fffc38 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rtc_ex.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rtc_ex.h @@ -354,14 +354,19 @@ typedef struct #define RTC_TAMPER_3 TAMP_CR1_TAMP3E #ifdef TAMP_CR1_TAMP4E #define RTC_TAMPER_4 TAMP_CR1_TAMP4E +#endif /* TAMP_CR1_TAMP4E */ +#ifdef TAMP_CR1_TAMP5E #define RTC_TAMPER_5 TAMP_CR1_TAMP5E #define RTC_TAMPER_6 TAMP_CR1_TAMP6E -#endif /* TAMP_CR1_TAMP4E */ +#endif /* TAMP_CR1_TAMP5E */ -#ifdef TAMP_CR1_TAMP4E +#ifdef TAMP_CR1_TAMP5E #define RTC_TAMPER_ALL (RTC_TAMPER_1 | RTC_TAMPER_2 |\ RTC_TAMPER_3 | RTC_TAMPER_4 |\ RTC_TAMPER_5 | RTC_TAMPER_6) +#elif defined(TAMP_CR1_TAMP4E) +#define RTC_TAMPER_ALL (RTC_TAMPER_1 | RTC_TAMPER_2 |\ + RTC_TAMPER_3 | RTC_TAMPER_4) #else #define RTC_TAMPER_ALL (RTC_TAMPER_1 | RTC_TAMPER_2 |\ RTC_TAMPER_3) diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_sai.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_sai.h index 5a4d728267..3d9bfbf10e 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_sai.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_sai.h @@ -47,8 +47,14 @@ extern "C" { typedef struct { FunctionalState Activation; /*!< Enable/disable PDM interface */ +#if defined(STM32WBA62xx) || defined(STM32WBA63xx) || defined(STM32WBA64xx) || defined(STM32WBA65xx) || defined (STM32WBA6Mxx) + uint32_t MicPairsNbr; /*!< Specifies the number of microphone pairs used. + This parameter must be a number between Min_Data = 1 and + Max_Data = 3 for STM32WBA6xxx devices, Max_Data = 2 for other devices. */ +#else /* defined(STM32WBA62xx) || defined(STM32WBA63xx) || defined(STM32WBA64xx) || defined(STM32WBA65xx) || defined (STM32WBA6Mxx) */ uint32_t MicPairsNbr; /*!< Specifies the number of microphone pairs used. This parameter must be a number between Min_Data = 1 and Max_Data = 2. */ +#endif /* defined(STM32WBA62xx) || defined(STM32WBA63xx) || defined(STM32WBA64xx) || defined(STM32WBA65xx) || defined (STM32WBA6Mxx) */ uint32_t ClockEnable; /*!< Specifies which clock must be enabled. This parameter can be a values combination of @ref SAI_PDM_ClockEnable */ } SAI_PdmInitTypeDef; @@ -853,7 +859,11 @@ uint32_t HAL_SAI_GetError(const SAI_HandleTypeDef *hsai); #define IS_SAI_BLOCK_MCK_OVERSAMPLING(VALUE) (((VALUE) == SAI_MCK_OVERSAMPLING_DISABLE) || \ ((VALUE) == SAI_MCK_OVERSAMPLING_ENABLE)) +#if defined(STM32WBA62xx) || defined(STM32WBA63xx) || defined(STM32WBA64xx) || defined(STM32WBA65xx) || defined (STM32WBA6Mxx) +#define IS_SAI_PDM_MIC_PAIRS_NUMBER(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 3U)) +#else /* defined(STM32WBA62xx) || defined(STM32WBA63xx) || defined(STM32WBA64xx) || defined(STM32WBA65xx) || defined (STM32WBA6Mxx) */ #define IS_SAI_PDM_MIC_PAIRS_NUMBER(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 2U)) +#endif /* defined(STM32WBA62xx) || defined(STM32WBA63xx) || defined(STM32WBA64xx) || defined(STM32WBA65xx) || defined (STM32WBA6Mxx) */ #define IS_SAI_PDM_CLOCK_ENABLE(CLOCK) (((CLOCK) != 0U) && \ (((CLOCK) & ~(SAI_PDM_CLOCK1_ENABLE | SAI_PDM_CLOCK2_ENABLE)) == 0U)) diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_sai_ex.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_sai_ex.h index 0e870a31c1..12086bea95 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_sai_ex.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_sai_ex.h @@ -45,8 +45,14 @@ extern "C" { */ typedef struct { +#if defined(STM32WBA62xx) || defined(STM32WBA63xx) || defined(STM32WBA64xx) || defined(STM32WBA65xx) || defined (STM32WBA6Mxx) + uint32_t MicPair; /*!< Specifies which pair of microphones is selected. + This parameter must be a number between Min_Data = 1 and + Max_Data = 3 for STM32WBA6xxx devices, Max_Data = 2 for other devices. */ +#else /* defined(STM32WBA62xx) || defined(STM32WBA63xx) || defined(STM32WBA64xx) || defined(STM32WBA65xx) || defined (STM32WBA6Mxx) */ uint32_t MicPair; /*!< Specifies which pair of microphones is selected. This parameter must be a number between Min_Data = 1 and Max_Data = 2. */ +#endif /* defined(STM32WBA62xx) || defined(STM32WBA63xx) || defined(STM32WBA64xx) || defined(STM32WBA65xx) || defined (STM32WBA6Mxx) */ uint32_t LeftDelay; /*!< Specifies the delay in PDM clock unit to apply on left microphone. This parameter must be a number between Min_Data = 0 and Max_Data = 7. */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_smartcard.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_smartcard.h index b175ba0a22..305ee0a295 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_smartcard.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_smartcard.h @@ -726,13 +726,13 @@ typedef enum */ #define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ SMARTCARD_CR_POS) == 1U)?\ - ((__HANDLE__)->Instance->CR1 &= ~ (1U <<\ + ((__HANDLE__)->Instance->CR1 &= ~ (1UL <<\ ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ SMARTCARD_CR_POS) == 2U)?\ - ((__HANDLE__)->Instance->CR2 &= ~ (1U <<\ + ((__HANDLE__)->Instance->CR2 &= ~ (1UL <<\ ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 &= ~ (1U <<\ + ((__HANDLE__)->Instance->CR3 &= ~ (1UL <<\ ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) /** @brief Check whether the specified SmartCard interrupt has occurred or not. @@ -863,6 +863,78 @@ typedef enum * @param __CLOCKSOURCE__ output variable. * @retval the SMARTCARD clocking source, written in __CLOCKSOURCE__. */ +#if defined(USART3) +#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK2: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ + case RCC_USART2CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART2CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART2CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART2CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + switch(__HAL_RCC_GET_USART3_SOURCE()) \ + { \ + case RCC_USART3CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART3CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART3CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART3CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) +#else #if defined(USART2) #define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ @@ -943,6 +1015,7 @@ typedef enum } \ } while(0U) #endif /* USART2 */ +#endif /* USART3 */ /** @brief Check the Baud rate range. * @note The maximum Baud Rate is derived from the maximum clock on WBA (100 MHz) diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_smbus_ex.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_smbus_ex.h index bf8ff2b2cb..76150a8200 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_smbus_ex.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_smbus_ex.h @@ -91,67 +91,67 @@ typedef struct /** @defgroup SMBUSEx_AutonomousMode_TriggerSelection SMBUS Extended Autonomous Mode Trigger Selection * @{ */ -#if defined(I2C1) -#define SMBUS_TRIG_GRP1 (0x10000000U) /*!< Trigger Group for I2C1 */ -#endif /* I2C1 */ +#if (defined(I2C1) || defined(I2C2) || defined(I2C4)) +#define SMBUS_TRIG_GRP1 (0x10000000U) /*!< Trigger Group for I2C1, I2C2, I2C4 */ +#endif /* I2C1, I2C2, I2C4 */ #define SMBUS_TRIG_GRP2 (0x20000000U) /*!< Trigger Group for I2C3 */ #if defined(SMBUS_TRIG_GRP1) #define SMBUS_GRP1_GPDMA_CH0_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x00000000U)) /*!< HW Trigger signal is GPDMA_CH0_TRG */ -#define SMBUS_GRP1_GPDMA_CH1_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x1U << I2C_AUTOCR_TRIGSEL_Pos)) +#define SMBUS_GRP1_GPDMA_CH1_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x1UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is GPDMA_CH1_TRG */ -#define SMBUS_GRP1_GPDMA_CH2_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x2U << I2C_AUTOCR_TRIGSEL_Pos)) +#define SMBUS_GRP1_GPDMA_CH2_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x2UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is GPDMA_CH2_TRG */ -#define SMBUS_GRP1_GPDMA_CH3_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x3U << I2C_AUTOCR_TRIGSEL_Pos)) +#define SMBUS_GRP1_GPDMA_CH3_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x3UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is GPDMA_CH3_TRG */ -#define SMBUS_GRP1_EXTI5_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x4U << I2C_AUTOCR_TRIGSEL_Pos)) +#define SMBUS_GRP1_EXTI5_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x4UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is EXTI5_TRG */ -#define SMBUS_GRP1_EXTI9_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x5U << I2C_AUTOCR_TRIGSEL_Pos)) +#define SMBUS_GRP1_EXTI9_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x5UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is EXTI9_TRG */ -#define SMBUS_GRP1_LPTIM1_CH1_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x6U << I2C_AUTOCR_TRIGSEL_Pos)) +#define SMBUS_GRP1_LPTIM1_CH1_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x6UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is LPTIM1_CH1_TRG */ -#define SMBUS_GRP1_LPTIM2_CH1_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x7U << I2C_AUTOCR_TRIGSEL_Pos)) +#define SMBUS_GRP1_LPTIM2_CH1_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x7UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is LPTIM2_CH1_TRG */ #if defined(COMP1) -#define SMBUS_GRP1_COMP1_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x8U << I2C_AUTOCR_TRIGSEL_Pos)) +#define SMBUS_GRP1_COMP1_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x8UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is COMP1_TRG */ #endif /* COMP1 */ #if defined(COMP2) -#define SMBUS_GRP1_COMP2_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x9U << I2C_AUTOCR_TRIGSEL_Pos)) +#define SMBUS_GRP1_COMP2_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x9UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is COMP2_TRG */ #endif /* COMP2 */ -#define SMBUS_GRP1_RTC_ALRA_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0xAU << I2C_AUTOCR_TRIGSEL_Pos)) +#define SMBUS_GRP1_RTC_ALRA_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0xAUL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is RTC_ALRA_TRG */ -#define SMBUS_GRP1_RTC_WUT_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0xBU << I2C_AUTOCR_TRIGSEL_Pos)) +#define SMBUS_GRP1_RTC_WUT_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0xBUL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is RTC_WUT_TRG */ #endif /* SMBUS_TRIG_GRP1 */ #define SMBUS_GRP2_GPDMA_CH0_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x00000000U)) /*!< HW Trigger signal is GPDMA_CH0_TRG */ -#define SMBUS_GRP2_GPDMA_CH1_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x1U << I2C_AUTOCR_TRIGSEL_Pos)) +#define SMBUS_GRP2_GPDMA_CH1_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x1UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is GPDMA_CH1_TRG */ -#define SMBUS_GRP2_GPDMA_CH2_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x2U << I2C_AUTOCR_TRIGSEL_Pos)) +#define SMBUS_GRP2_GPDMA_CH2_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x2UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is GPDMA_CH2_TRG */ -#define SMBUS_GRP2_GPDMA_CH3_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x3U << I2C_AUTOCR_TRIGSEL_Pos)) +#define SMBUS_GRP2_GPDMA_CH3_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x3UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is GPDMA_CH3_TRG */ -#define SMBUS_GRP2_EXTI5_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x4U << I2C_AUTOCR_TRIGSEL_Pos)) +#define SMBUS_GRP2_EXTI5_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x4UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is EXTI5_TRG */ -#define SMBUS_GRP2_EXTI8_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x5U << I2C_AUTOCR_TRIGSEL_Pos)) +#define SMBUS_GRP2_EXTI8_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x5UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is EXTI8_TRG */ -#define SMBUS_GRP2_LPTIM1_CH1_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x6U << I2C_AUTOCR_TRIGSEL_Pos)) +#define SMBUS_GRP2_LPTIM1_CH1_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x6UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is LPTIM1_CH1_TRG */ #if defined(COMP1) -#define SMBUS_GRP2_COMP1_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x8U << I2C_AUTOCR_TRIGSEL_Pos)) +#define SMBUS_GRP2_COMP1_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x8UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is COMP1_TRG */ #endif /* COMP1 */ #if defined(COMP2) -#define SMBUS_GRP2_COMP2_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x9U << I2C_AUTOCR_TRIGSEL_Pos)) +#define SMBUS_GRP2_COMP2_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x9UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is COMP2_TRG */ #endif /* COMP2 */ -#define SMBUS_GRP2_RTC_ALRA_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0xAU << I2C_AUTOCR_TRIGSEL_Pos)) +#define SMBUS_GRP2_RTC_ALRA_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0xAUL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is RTC_ALRA_TRG */ -#define SMBUS_GRP2_RTC_WUT_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0xBU << I2C_AUTOCR_TRIGSEL_Pos)) +#define SMBUS_GRP2_RTC_WUT_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0xBUL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is RTC_WUT_TRG */ /** * @} diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_spi_ex.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_spi_ex.h index 7537de2d39..c0e7db0993 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_spi_ex.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_spi_ex.h @@ -87,57 +87,57 @@ typedef struct /* HW Trigger signal is GPDMA_CH0_TRG */ #define SPI_GRP1_GPDMA_CH0_TCF_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x00000000U)) /* HW Trigger signal is GPDMA_CH1_TRG */ -#define SPI_GRP1_GPDMA_CH1_TCF_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x1U << SPI_AUTOCR_TRIGSEL_Pos)) +#define SPI_GRP1_GPDMA_CH1_TCF_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x1UL << SPI_AUTOCR_TRIGSEL_Pos)) /* HW Trigger signal is GPDMA_CH2_TRG */ -#define SPI_GRP1_GPDMA_CH2_TCF_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x2U << SPI_AUTOCR_TRIGSEL_Pos)) +#define SPI_GRP1_GPDMA_CH2_TCF_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x2UL << SPI_AUTOCR_TRIGSEL_Pos)) /* HW Trigger signal is GPDMA_CH3_TRG */ -#define SPI_GRP1_GPDMA_CH3_TCF_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x3U << SPI_AUTOCR_TRIGSEL_Pos)) +#define SPI_GRP1_GPDMA_CH3_TCF_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x3UL << SPI_AUTOCR_TRIGSEL_Pos)) /* HW Trigger signal is EXTI4_TRG */ -#define SPI_GRP1_EXTI4_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x4U << SPI_AUTOCR_TRIGSEL_Pos)) +#define SPI_GRP1_EXTI4_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x4UL << SPI_AUTOCR_TRIGSEL_Pos)) /* HW Trigger signal is EXTI9_TRG */ -#define SPI_GRP1_EXTI9_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x5U << SPI_AUTOCR_TRIGSEL_Pos)) +#define SPI_GRP1_EXTI9_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x5UL << SPI_AUTOCR_TRIGSEL_Pos)) /* HW Trigger signal is LPTIM1_CH1_TRG */ -#define SPI_GRP1_LPTIM1_CH1_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x6U << SPI_AUTOCR_TRIGSEL_Pos)) +#define SPI_GRP1_LPTIM1_CH1_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x6UL << SPI_AUTOCR_TRIGSEL_Pos)) #if defined(LPTIM2) /* HW Trigger signal is LPTIM2_CH1_TRG */ -#define SPI_GRP1_LPTIM2_CH1_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x7U << SPI_AUTOCR_TRIGSEL_Pos)) +#define SPI_GRP1_LPTIM2_CH1_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x7UL << SPI_AUTOCR_TRIGSEL_Pos)) #endif /* LPTIM2 */ #if defined(COMP1) /* HW Trigger signal is COMP1_TRG */ -#define SPI_GRP1_COMP1_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x8U << SPI_AUTOCR_TRIGSEL_Pos)) +#define SPI_GRP1_COMP1_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x8UL << SPI_AUTOCR_TRIGSEL_Pos)) #endif /* COMP1 */ #if defined(COMP2) /* HW Trigger signal is COMP2_TRG */ -#define SPI_GRP1_COMP2_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x9U << SPI_AUTOCR_TRIGSEL_Pos)) +#define SPI_GRP1_COMP2_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x9UL << SPI_AUTOCR_TRIGSEL_Pos)) #endif /* (COMP2) */ /* HW Trigger signal is RTC_ALRA_TRG */ -#define SPI_GRP1_RTC_ALRA_TRG (uint32_t)(SPI_TRIG_GRP1 | (0xAU << SPI_AUTOCR_TRIGSEL_Pos)) +#define SPI_GRP1_RTC_ALRA_TRG (uint32_t)(SPI_TRIG_GRP1 | (0xAUL << SPI_AUTOCR_TRIGSEL_Pos)) /* HW Trigger signal is RTC_WUT_TRG */ -#define SPI_GRP1_RTC_WUT_TRG (uint32_t)(SPI_TRIG_GRP1 | (0xBU << SPI_AUTOCR_TRIGSEL_Pos)) +#define SPI_GRP1_RTC_WUT_TRG (uint32_t)(SPI_TRIG_GRP1 | (0xBUL << SPI_AUTOCR_TRIGSEL_Pos)) #endif /* SPI_TRIG_GRP1 */ /* HW Trigger signal is GPDMA_CH0_TRG */ #define SPI_GRP2_GPDMA_CH0_TCF_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x00000000U)) /* HW Trigger signal is GPDMA_CH1_TRG */ -#define SPI_GRP2_GPDMA_CH1_TCF_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x1U << SPI_AUTOCR_TRIGSEL_Pos)) +#define SPI_GRP2_GPDMA_CH1_TCF_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x1UL << SPI_AUTOCR_TRIGSEL_Pos)) /* HW Trigger signal is GPDMA_CH2_TRG */ -#define SPI_GRP2_GPDMA_CH2_TCF_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x2U << SPI_AUTOCR_TRIGSEL_Pos)) +#define SPI_GRP2_GPDMA_CH2_TCF_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x2UL << SPI_AUTOCR_TRIGSEL_Pos)) /* HW Trigger signal is GPDMA_CH3_TRG */ -#define SPI_GRP2_GPDMA_CH3_TCF_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x3U << SPI_AUTOCR_TRIGSEL_Pos)) +#define SPI_GRP2_GPDMA_CH3_TCF_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x3UL << SPI_AUTOCR_TRIGSEL_Pos)) /* HW Trigger signal is EXTI4_TRG */ -#define SPI_GRP2_EXTI4_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x4U << SPI_AUTOCR_TRIGSEL_Pos)) +#define SPI_GRP2_EXTI4_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x4UL << SPI_AUTOCR_TRIGSEL_Pos)) /* HW Trigger signal is EXTI8_TRG */ -#define SPI_GRP2_EXTI8_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x5U << SPI_AUTOCR_TRIGSEL_Pos)) +#define SPI_GRP2_EXTI8_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x5UL << SPI_AUTOCR_TRIGSEL_Pos)) /* HW Trigger signal is LPTIM1_CH1_TRG */ -#define SPI_GRP2_LPTIM1_CH1_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x6U << SPI_AUTOCR_TRIGSEL_Pos)) +#define SPI_GRP2_LPTIM1_CH1_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x6UL << SPI_AUTOCR_TRIGSEL_Pos)) #if defined(COMP1) /* HW Trigger signal is COMP1_TRG */ -#define SPI_GRP2_COMP1_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x8U << SPI_AUTOCR_TRIGSEL_Pos)) +#define SPI_GRP2_COMP1_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x8UL << SPI_AUTOCR_TRIGSEL_Pos)) #endif /* COMP1 */ /* HW Trigger signal is RTC_ALRA_TRG */ -#define SPI_GRP2_RTC_ALRA_TRG (uint32_t)(SPI_TRIG_GRP2 | (0xAU << SPI_AUTOCR_TRIGSEL_Pos)) +#define SPI_GRP2_RTC_ALRA_TRG (uint32_t)(SPI_TRIG_GRP2 | (0xAUL << SPI_AUTOCR_TRIGSEL_Pos)) /* HW Trigger signal is RTC_WUT_TRG */ -#define SPI_GRP2_RTC_WUT_TRG (uint32_t)(SPI_TRIG_GRP2 | (0xBU << SPI_AUTOCR_TRIGSEL_Pos)) +#define SPI_GRP2_RTC_WUT_TRG (uint32_t)(SPI_TRIG_GRP2 | (0xBUL << SPI_AUTOCR_TRIGSEL_Pos)) /** * @} */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_tim.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_tim.h index bfe807ca31..c7be9984e0 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_tim.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_tim.h @@ -244,8 +244,10 @@ typedef struct { uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection This parameter can be a value of @ref TIM_Master_Mode_Selection */ +#if defined(TIM_CR2_MMS2) uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */ +#endif /* TIM_CR2_MMS2 */ uint32_t MasterSlaveMode; /*!< Master/slave mode selection This parameter can be a value of @ref TIM_Master_Slave_Mode @note When the Master/slave mode is enabled, the effect of @@ -296,6 +298,7 @@ typedef struct uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input.This parameter can be a value of @ref TIM_Break_Input_AF_Mode */ +#if defined(TIM_BDTR_BK2E) uint32_t Break2State; /*!< TIM Break2 State, This parameter can be a value of @ref TIM_Break2_Input_enable_disable */ uint32_t Break2Polarity; /*!< TIM Break2 input polarity, This parameter can be a value of @ref TIM_Break2_Polarity */ @@ -303,6 +306,7 @@ typedef struct uint32_t Break2Filter; /*!< TIM break2 input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input.This parameter can be a value of @ref TIM_Break2_Input_AF_Mode */ +#endif /*TIM_BDTR_BK2E */ uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state, This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ @@ -349,8 +353,12 @@ typedef enum HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ +#if defined(TIM_CCER_CC5E) HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, /*!< The active channel is 5 */ +#endif /* TIM_CCER_CC5E */ +#if defined(TIM_CCER_CC6E) HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, /*!< The active channel is 6 */ +#endif /* TIM_CCER_CC6E */ HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ } HAL_TIM_ActiveChannel; @@ -370,8 +378,13 @@ typedef struct This array is accessed by a @ref DMA_Handle_index */ HAL_LockTypeDef Lock; /*!< Locking object */ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ +#if defined(TIM1) __IO HAL_TIM_ChannelStateTypeDef ChannelState[6]; /*!< TIM channel operation state */ __IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /*!< TIM complementary channel operation state */ +#else + __IO HAL_TIM_ChannelStateTypeDef ChannelState[4]; /*!< TIM channel operation state */ + __IO HAL_TIM_ChannelStateTypeDef ChannelNState[1]; /*!< TIM complementary channel operation state */ +#endif /* TIM1 */ __IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */ #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) @@ -402,7 +415,9 @@ typedef struct void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */ void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation half complete Callback */ void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */ +#if defined(TIM_BDTR_BK2E) void (* Break2Callback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break2 Callback */ +#endif /* TIM_BDTR_BK2E */ void (* EncoderIndexCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Index Callback */ void (* DirectionChangeCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Direction Change Callback */ void (* IndexErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Index Error Callback */ @@ -443,7 +458,9 @@ typedef enum , HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ , HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */ , HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */ +#if defined(TIM_BDTR_BK2E) , HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */ +#endif /* TIM_BDTR_BK2E */ , HAL_TIM_ENCODER_INDEX_CB_ID = 0x1CU /*!< TIM Encoder Index Callback ID */ , HAL_TIM_DIRECTION_CHANGE_CB_ID = 0x1DU /*!< TIM Direction Change Callback ID */ , HAL_TIM_INDEX_ERROR_CB_ID = 0x1EU /*!< TIM Index Error Callback ID */ @@ -472,8 +489,10 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to */ #define TIM_CLEARINPUTSOURCE_NONE 0xFFFFFFFFU /*!< OCREF_CLR is disabled */ #define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */ +#if defined(COMP1) && defined(COMP2) #define TIM_CLEARINPUTSOURCE_COMP1 0x00000000U /*!< OCREF_CLR_INT is connected to COMP1 output */ #define TIM_CLEARINPUTSOURCE_COMP2 TIM_AF2_OCRSEL_0 /*!< OCREF_CLR_INT is connected to COMP2 output */ +#endif /* COMP1 && COMP2 */ /** * @} */ @@ -499,9 +518,13 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to #define TIM_DMABASE_CCR3 0x0000000FU #define TIM_DMABASE_CCR4 0x00000010U #define TIM_DMABASE_BDTR 0x00000011U +#if defined(TIM_CCER_CC5E) #define TIM_DMABASE_CCR5 0x00000012U +#endif /* TIM_CCER_CC5E */ +#if defined(TIM_CCER_CC6E) #define TIM_DMABASE_CCR6 0x00000013U #define TIM_DMABASE_CCMR3 0x00000014U +#endif /* TIM_CCER_CC6E */ #define TIM_DMABASE_DTR2 0x00000015U #define TIM_DMABASE_ECR 0x00000016U #define TIM_DMABASE_TISEL 0x00000017U @@ -523,7 +546,9 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to #define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */ #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */ #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */ +#if defined(TIM_EGR_B2G) #define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G /*!< A break 2 event is generated */ +#endif /* TIM_EGR_B2G */ /** * @} */ @@ -786,12 +811,18 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to #define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */ #define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */ #define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */ +#if defined(TIM_SR_CC5IF) #define TIM_FLAG_CC5 TIM_SR_CC5IF /*!< Capture/Compare 5 interrupt flag */ +#endif /* TIM_SR_CC5IF */ +#if defined(TIM_SR_CC6IF) #define TIM_FLAG_CC6 TIM_SR_CC6IF /*!< Capture/Compare 6 interrupt flag */ +#endif /* TIM_SR_CC6IF */ #define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */ #define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */ #define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */ +#if defined(TIM_SR_B2IF) #define TIM_FLAG_BREAK2 TIM_SR_B2IF /*!< Break 2 interrupt flag */ +#endif /* TIM_SR_B2IF */ #define TIM_FLAG_SYSTEM_BREAK TIM_SR_SBIF /*!< System Break interrupt flag */ #define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */ #define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */ @@ -812,8 +843,12 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to #define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */ #define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */ #define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */ +#if defined(TIM_CCER_CC5E) #define TIM_CHANNEL_5 0x00000010U /*!< Compare channel 5 identifier */ +#endif /* TIM_CCER_CC5E */ +#if defined(TIM_CCER_CC6E) #define TIM_CHANNEL_6 0x00000014U /*!< Compare channel 6 identifier */ +#endif /* TIM_CCER_CC6E */ #define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */ /** * @} @@ -828,14 +863,21 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to #define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */ #define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */ #define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */ +#if defined(TIM1) #define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */ #define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */ +#endif /* TIM1 */ +#if defined(TIM3) || defined(TIM2) #define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */ -#define TIM_CLOCKSOURCE_ITR4 TIM_TS_ITR4 /*!< External clock source mode 1 (ITR4) */ -#define TIM_CLOCKSOURCE_ITR5 TIM_TS_ITR5 /*!< External clock source mode 1 (ITR5) */ -#define TIM_CLOCKSOURCE_ITR6 TIM_TS_ITR6 /*!< External clock source mode 1 (ITR6) */ +#endif /* TIM3 */ +#if defined(TIM4) +#define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */ +#endif /* TIM4 */ #define TIM_CLOCKSOURCE_ITR7 TIM_TS_ITR7 /*!< External clock source mode 1 (ITR7) */ #define TIM_CLOCKSOURCE_ITR8 TIM_TS_ITR8 /*!< External clock source mode 1 (ITR8) */ +#if defined(USB_OTG_HS) || defined(USB_DRD_FS) +#define TIM_CLOCKSOURCE_ITR11 TIM_TS_ITR11 /*!< External clock source mode 1 (ITR11) */ +#endif /* USB_OTG_HS || USB_DRD_FS */ /** * @} */ @@ -938,6 +980,7 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @} */ +#if defined(TIM_BDTR_BK2E) /** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable * @{ */ @@ -964,6 +1007,7 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to /** * @} */ +#endif /* TIM_BDTR_BK2E */ /** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable * @{ @@ -974,6 +1018,7 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @} */ +#if defined(TIM_CCR5_CCR5) /** @defgroup TIM_Group_Channel5 TIM Group Channel 5 and Channel 1, 2 or 3 * @{ */ @@ -984,6 +1029,7 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to /** * @} */ +#endif /* TIM_CCR5_CCR5 */ /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection * @{ @@ -1001,6 +1047,7 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @} */ +#if defined(TIM_CR2_MMS2) /** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2) * @{ */ @@ -1023,6 +1070,7 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to /** * @} */ +#endif /* TIM_CR2_MMS2 */ /** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode * @{ @@ -1073,11 +1121,21 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to /** @defgroup TIM_Trigger_Selection TIM Trigger Selection * @{ */ +#if defined(TIM1) #define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */ #define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */ +#endif /* TIM1 */ +#if defined(TIM3) || defined(TIM2) #define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */ +#endif /* TIM3 */ +#if defined(TIM4) +#define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */ +#endif /* TIM4 */ #define TIM_TS_ITR7 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 7 (ITR7) */ #define TIM_TS_ITR8 (TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 8 (ITR8) */ +#if defined(USB_OTG_HS) || defined(USB_DRD_FS) +#define TIM_TS_ITR11 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 11 (ITR11) */ +#endif /* USB_OTG_HS || USB_DRD_FS */ #define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */ #define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */ #define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */ @@ -1203,6 +1261,7 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @retval None */ #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +#if defined(TIM1) #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ @@ -1232,6 +1291,32 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \ } while(0) #else +#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ + (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ + (__HANDLE__)->Base_MspInitCallback = NULL; \ + (__HANDLE__)->Base_MspDeInitCallback = NULL; \ + (__HANDLE__)->IC_MspInitCallback = NULL; \ + (__HANDLE__)->IC_MspDeInitCallback = NULL; \ + (__HANDLE__)->OC_MspInitCallback = NULL; \ + (__HANDLE__)->OC_MspDeInitCallback = NULL; \ + (__HANDLE__)->PWM_MspInitCallback = NULL; \ + (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ + (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ + (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ + (__HANDLE__)->Encoder_MspInitCallback = NULL; \ + (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ + (__HANDLE__)->HallSensor_MspInitCallback = NULL; \ + (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \ + } while(0) +#endif /* TIM1 */ +#else +#if defined(TIM1) #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ @@ -1246,6 +1331,17 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ } while(0) +#else +#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ + (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ + } while(0) +#endif /* TIM1 */ #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /** @@ -1383,12 +1479,12 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag - * @arg TIM_FLAG_CC5: Compare 5 interrupt flag - * @arg TIM_FLAG_CC6: Compare 6 interrupt flag + * @arg TIM_FLAG_CC5: Compare 5 interrupt flag (*) + * @arg TIM_FLAG_CC6: Compare 6 interrupt flag (*) * @arg TIM_FLAG_COM: Commutation interrupt flag * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag * @arg TIM_FLAG_BREAK: Break interrupt flag - * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag + * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag (*) * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag @@ -1398,6 +1494,7 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @arg TIM_FLAG_DIR: Direction change interrupt flag * @arg TIM_FLAG_IERR: Index error interrupt flag * @arg TIM_FLAG_TERR: Transition error interrupt flag + * (*) Value not defined for all devices * @retval The new state of __FLAG__ (TRUE or FALSE). */ #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) @@ -1411,12 +1508,12 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag - * @arg TIM_FLAG_CC5: Compare 5 interrupt flag - * @arg TIM_FLAG_CC6: Compare 6 interrupt flag + * @arg TIM_FLAG_CC5: Compare 5 interrupt flag (*) + * @arg TIM_FLAG_CC6: Compare 6 interrupt flag (*) * @arg TIM_FLAG_COM: Commutation interrupt flag * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag * @arg TIM_FLAG_BREAK: Break interrupt flag - * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag + * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag (*) * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag @@ -1426,6 +1523,7 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @arg TIM_FLAG_DIR: Direction change interrupt flag * @arg TIM_FLAG_IERR: Index error interrupt flag * @arg TIM_FLAG_TERR: Transition error interrupt flag + * (*) Value not defined for all devices * @retval The new state of __FLAG__ (TRUE or FALSE). */ #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) @@ -1633,11 +1731,13 @@ mode. * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*) + * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*) + * (*) Value not defined for all devices * @param __COMPARE__ specifies the Capture Compare register new value. * @retval None */ +#if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E) #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ @@ -1645,6 +1745,13 @@ mode. ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\ ((__HANDLE__)->Instance->CCR6 = (__COMPARE__))) +#else +#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ + ((__HANDLE__)->Instance->CCR4 = (__COMPARE__))) +#endif /* TIM_CCER_CC5E && TIM_CCER_CC6E */ /** * @brief Get the TIM Capture Compare Register value on runtime. @@ -1655,10 +1762,12 @@ mode. * @arg TIM_CHANNEL_2: get capture/compare 2 register value * @arg TIM_CHANNEL_3: get capture/compare 3 register value * @arg TIM_CHANNEL_4: get capture/compare 4 register value - * @arg TIM_CHANNEL_5: get capture/compare 5 register value - * @arg TIM_CHANNEL_6: get capture/compare 6 register value + * @arg TIM_CHANNEL_5: get capture/compare 5 register value (*) + * @arg TIM_CHANNEL_6: get capture/compare 6 register value (*) + * (*) Value not defined for all devices * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) */ +#if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E) #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ @@ -1666,6 +1775,13 @@ mode. ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\ ((__HANDLE__)->Instance->CCR6)) +#else +#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\ + ((__HANDLE__)->Instance->CCR4)) +#endif /* TIM_CCER_CC5E && TIM_CCER_CC6E */ /** * @brief Set the TIM Output compare preload. @@ -1676,10 +1792,12 @@ mode. * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*) + * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*) + * (*) Value not defined for all devices * @retval None */ +#if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E) #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ @@ -1687,6 +1805,13 @@ mode. ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\ ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE)) +#else +#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ + ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE)) +#endif /* TIM_CCER_CC5E && TIM_CCER_CC6E */ /** * @brief Reset the TIM Output compare preload. @@ -1697,10 +1822,12 @@ mode. * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*) + * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*) + * (*) Value not defined for all devices * @retval None */ +#if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E) #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\ @@ -1708,6 +1835,13 @@ mode. ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) :\ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) :\ ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE)) +#else +#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\ + ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE)) +#endif /* TIM_CCER_CC5E && TIM_CCER_CC6E */ /** * @brief Enable fast mode for a given channel. @@ -1718,14 +1852,16 @@ mode. * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*) + * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*) + * (*) Value not defined for all devices * @note When fast mode is enabled an active edge on the trigger input acts * like a compare match on CCx output. Delay to sample the trigger * input and to activate CCx output is reduced to 3 clock cycles. * @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode. * @retval None */ +#if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E) #define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\ @@ -1733,6 +1869,13 @@ mode. ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) :\ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) :\ ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE)) +#else +#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\ + ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE)) +#endif /* TIM_CCER_CC5E && TIM_CCER_CC6E */ /** * @brief Disable fast mode for a given channel. @@ -1743,14 +1886,16 @@ mode. * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*) + * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*) + * (*) Value not defined for all devices * @note When fast mode is disabled CCx output behaves normally depending * on counter and CCRx values even when the trigger is ON. The minimum * delay to activate CCx output when an active edge occurs on the * trigger input is 5 clock cycles. * @retval None */ +#if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E) #define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\ @@ -1758,6 +1903,13 @@ mode. ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) :\ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) :\ ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE)) +#else +#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\ + ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE)) +#endif /* TIM_CCER_CC5E && TIM_CCER_CC6E */ /** * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register. @@ -1825,8 +1977,14 @@ mode. */ /* The counter of a timer instance is disabled only if all the CCx and CCxN channels have been disabled */ -#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) +#if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E) +#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E | \ + TIM_CCER_CC5E | TIM_CCER_CC6E)) #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE | TIM_CCER_CC4NE)) +#else +#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) +#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE)) +#endif /* TIM_CCER_CC5E && TIM_CCER_CC6E */ /** * @} */ @@ -1836,11 +1994,17 @@ mode. /** @defgroup TIM_Private_Macros TIM Private Macros * @{ */ +#if defined(COMP1) && defined(COMP2) #define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \ ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP1) || \ ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP2) || \ ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE)) +#else +#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \ + ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE)) +#endif /* COMP1 && COMP2 */ +#if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E) #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ ((__BASE__) == TIM_DMABASE_CR2) || \ ((__BASE__) == TIM_DMABASE_SMCR) || \ @@ -1866,10 +2030,40 @@ mode. ((__BASE__) == TIM_DMABASE_AF2) || \ ((__BASE__) == TIM_DMABASE_TISEL) || \ ((__BASE__) == TIM_DMABASE_DTR2) || \ - ((__BASE__) == TIM_DMABASE_ECR) || \ + ((__BASE__) == TIM_DMABASE_ECR) || \ ((__BASE__) == TIM_DMABASE_OR)) +#else +#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ + ((__BASE__) == TIM_DMABASE_CR2) || \ + ((__BASE__) == TIM_DMABASE_SMCR) || \ + ((__BASE__) == TIM_DMABASE_DIER) || \ + ((__BASE__) == TIM_DMABASE_SR) || \ + ((__BASE__) == TIM_DMABASE_EGR) || \ + ((__BASE__) == TIM_DMABASE_CCMR1) || \ + ((__BASE__) == TIM_DMABASE_CCMR2) || \ + ((__BASE__) == TIM_DMABASE_CCER) || \ + ((__BASE__) == TIM_DMABASE_CNT) || \ + ((__BASE__) == TIM_DMABASE_PSC) || \ + ((__BASE__) == TIM_DMABASE_ARR) || \ + ((__BASE__) == TIM_DMABASE_RCR) || \ + ((__BASE__) == TIM_DMABASE_CCR1) || \ + ((__BASE__) == TIM_DMABASE_CCR2) || \ + ((__BASE__) == TIM_DMABASE_CCR3) || \ + ((__BASE__) == TIM_DMABASE_CCR4) || \ + ((__BASE__) == TIM_DMABASE_BDTR) || \ + ((__BASE__) == TIM_DMABASE_AF1) || \ + ((__BASE__) == TIM_DMABASE_AF2) || \ + ((__BASE__) == TIM_DMABASE_TISEL) || \ + ((__BASE__) == TIM_DMABASE_DTR2) || \ + ((__BASE__) == TIM_DMABASE_ECR) || \ + ((__BASE__) == TIM_DMABASE_OR)) +#endif /* TIM_CCER_CC5E && TIM_CCER_CC6E */ +#if defined(TIM_EGR_B2G) #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) +#else +#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFF00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) +#endif /* TIM_EGR_B2G */ #define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \ ((__MODE__) == TIM_COUNTERMODE_DOWN) || \ @@ -1918,9 +2112,13 @@ mode. ((__PRESCALER__) == TIM_ICPSC_DIV4) || \ ((__PRESCALER__) == TIM_ICPSC_DIV8)) +#if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E) #define IS_TIM_CCX_CHANNEL(__INSTANCE__, __CHANNEL__) (IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) && \ ((__CHANNEL__) != (TIM_CHANNEL_5)) && \ ((__CHANNEL__) != (TIM_CHANNEL_6))) +#else +#define IS_TIM_CCX_CHANNEL(__INSTANCE__, __CHANNEL__) (IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__)) +#endif /* TIM_CCER_CC5E && TIM_CCER_CC6E */ #define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \ ((__MODE__) == TIM_OPMODE_REPETITIVE)) @@ -1937,6 +2135,7 @@ mode. #define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) +#if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E) #define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ ((__CHANNEL__) == TIM_CHANNEL_2) || \ ((__CHANNEL__) == TIM_CHANNEL_3) || \ @@ -1944,19 +2143,29 @@ mode. ((__CHANNEL__) == TIM_CHANNEL_5) || \ ((__CHANNEL__) == TIM_CHANNEL_6) || \ ((__CHANNEL__) == TIM_CHANNEL_ALL)) +#else +#define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ + ((__CHANNEL__) == TIM_CHANNEL_2) || \ + ((__CHANNEL__) == TIM_CHANNEL_3) || \ + ((__CHANNEL__) == TIM_CHANNEL_4) || \ + ((__CHANNEL__) == TIM_CHANNEL_ALL)) +#endif /* TIM_CCER_CC5E &&TIM_CCER_CC6E */ #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ ((__CHANNEL__) == TIM_CHANNEL_2)) -#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? \ - (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : \ - ((__PERIOD__) > 0U)) +#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? \ + ((READ_BIT((__HANDLE__)->Instance->CR1, TIM_CR1_DITHEN) == 0U) ? \ + (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : \ + (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x000FFFEFU))) : \ + ((__PERIOD__) > 0U )) #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ ((__CHANNEL__) == TIM_CHANNEL_2) || \ ((__CHANNEL__) == TIM_CHANNEL_3) || \ ((__CHANNEL__) == TIM_CHANNEL_4)) +#if defined(TIM4) #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ @@ -1966,8 +2175,44 @@ mode. ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11)) +#elif defined(TIM1) +#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)) +#else +#if defined(USB_OTG_HS) || defined(USB_DRD_FS) +#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11)) +#else /* (USB_OTG_HS) || (USB_DRD_FS) */ +#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)) +#endif +#endif /* TIM4 */ #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \ ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \ @@ -2015,6 +2260,7 @@ mode. ((__AFMODE__) == TIM_BREAK_AFMODE_BIDIRECTIONAL)) +#if defined(TIM_BDTR_BK2E) #define IS_TIM_BREAK2_STATE(__STATE__) (((__STATE__) == TIM_BREAK2_ENABLE) || \ ((__STATE__) == TIM_BREAK2_DISABLE)) @@ -2024,11 +2270,14 @@ mode. #define IS_TIM_BREAK2_AFMODE(__AFMODE__) (((__AFMODE__) == TIM_BREAK2_AFMODE_INPUT) || \ ((__AFMODE__) == TIM_BREAK2_AFMODE_BIDIRECTIONAL)) +#endif /* TIM_BDTR_BK2E */ #define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \ ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE)) +#if defined(TIM_CCR5_CCR5) #define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U)) +#endif /* TIM_CCR5_CCR5 */ #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \ ((__SOURCE__) == TIM_TRGO_ENABLE) || \ @@ -2040,6 +2289,7 @@ mode. ((__SOURCE__) == TIM_TRGO_OC4REF) || \ ((__SOURCE__) == TIM_TRGO_ENCODER_CLK)) +#if defined(TIM_CR2_MMS2) #define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET) || \ ((__SOURCE__) == TIM_TRGO2_ENABLE) || \ ((__SOURCE__) == TIM_TRGO2_UPDATE) || \ @@ -2057,6 +2307,7 @@ mode. ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \ ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \ ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING)) +#endif /* TIM_CR2_MMS2 */ #define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \ ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE)) @@ -2087,12 +2338,34 @@ mode. ((__MODE__) == TIM_OCMODE_DIRECTION_OUTPUT) || \ ((__MODE__) == TIM_OCMODE_PULSE_ON_COMPARE)) -#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ - ((__SELECTION__) == TIM_TS_ITR1) || \ - ((__SELECTION__) == TIM_TS_ITR2) || \ - ((__SELECTION__) == TIM_TS_ITR7) || \ - ((__SELECTION__) == TIM_TS_ITR8) || \ +#if defined(TIM4) +#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_ITR11) || \ + ((__SELECTION__) == TIM_TS_NONE)) +#elif defined(TIM1) +#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_NONE)) +#else +#if defined(USB_OTG_HS) || defined(USB_DRD_FS) +#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_ITR11) || \ + ((__SELECTION__) == TIM_TS_NONE)) +#else /* (USB_OTG_HS) || (USB_DRD_FS)*/ +#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_NONE)) +#endif /* (USB_OTG_HS) || (USB_DRD_FS)*/ +#endif /* TIM4 */ #define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \ ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ @@ -2175,6 +2448,7 @@ mode. ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) +#if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E) #define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\ (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\ @@ -2191,21 +2465,38 @@ mode. ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__)) :\ ((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__))) -#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ - (__HANDLE__)->ChannelState[0] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[1] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[2] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[3] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[4] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[5] = \ - (__CHANNEL_STATE__); \ - } while(0) +#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__)\ + do {\ + (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__); \ + } while(0) +#else +#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\ + (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\ + (__HANDLE__)->ChannelState[3]) +#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\ + ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__))) + +#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__)\ + do {\ + (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__);\ + (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__);\ + (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__);\ + (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__);\ + } while(0) +#endif /* TIM_CCER_CC5E && TIM_CCER_CC6E */ + +#if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E) #define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\ (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\ @@ -2218,16 +2509,24 @@ mode. ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\ ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__))) -#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ - (__HANDLE__)->ChannelNState[0] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelNState[1] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelNState[2] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelNState[3] = \ - (__CHANNEL_STATE__); \ - } while(0) +#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__)\ + do {\ + (__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__); \ + } while(0) +#else +#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\ + (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\ + HAL_TIM_CHANNEL_STATE_READY) + +#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ + (((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__))) + +#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) \ + (((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__))) +#endif /* TIM_CCER_CC5E && TIM_CCER_CC6E */ /** * @} diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_tim_ex.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_tim_ex.h index d4f95b7c90..37e8c11000 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_tim_ex.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_tim_ex.h @@ -106,6 +106,7 @@ typedef struct /** @defgroup TIMEx_Remap TIM Extended Remapping * @{ */ +#if defined(TIM1) #define TIM_TIM1_ETR_GPIO 0x00000000UL /*!< TIM1_ETR is not connected to I/O */ #define TIM_TIM1_ETR_COMP1 TIM_AF1_ETRSEL_0 /*!< TIM1_ETR is connected to COMP1 output */ #define TIM_TIM1_ETR_COMP2 TIM_AF1_ETRSEL_1 /*!< TIM1_ETR is connected to COMP2 output */ @@ -113,22 +114,48 @@ typedef struct #define TIM_TIM1_ETR_ADC4_AWD1 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC4 AWD1 */ #define TIM_TIM1_ETR_ADC4_AWD2 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2) /*!< TIM1_ETR is connected to ADC4 AWD2 */ #define TIM_TIM1_ETR_ADC4_AWD3 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC4 AWD3 */ +#endif /* TIM1 */ #define TIM_TIM2_ETR_GPIO 0x00000000UL /*!< TIM2_ETR is not connected to I/O */ +#if defined(COMP1) && defined(COMP2) #define TIM_TIM2_ETR_COMP1 TIM_AF1_ETRSEL_0 /*!< TIM2_ETR is connected to COMP1 output */ #define TIM_TIM2_ETR_COMP2 TIM_AF1_ETRSEL_1 /*!< TIM2_ETR is connected to COMP2 output */ +#endif /* COMP1 && COMP2 */ #define TIM_TIM2_ETR_HSI TIM_AF1_ETRSEL_2 /*!< TIM2_ETR is connected to HSI */ +#if defined(TIM3) #define TIM_TIM2_ETR_TIM3_ETR TIM_AF1_ETRSEL_3 /*!< TIM2_ETR is connected to TIM3 ETR */ +#endif /* TIM3 */ +#if defined(TIM4) +#define TIM_TIM2_ETR_TIM4_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to TIM4 ETR */ +#endif /* TIM4 */ #define TIM_TIM2_ETR_LSE (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to LSE */ +#if defined(TIM2_ETR_ADC4_SUPPORT) +#define TIM_TIM2_ETR_ADC4_AWD1 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2) /*!< TIM2_ETR is connected to ADC4 AWD1 */ +#define TIM_TIM2_ETR_ADC4_AWD2 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to ADC4 AWD2 */ +#define TIM_TIM2_ETR_ADC4_AWD3 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1) /*!< TIM2_ETR is connected to ADC4 AWD3 */ +#endif /* TIM2_ETR_ADC4_SUPPORT */ +#if defined(TIM3) #define TIM_TIM3_ETR_GPIO 0x00000000UL /*!< TIM3_ETR is not connected to I/O */ #define TIM_TIM3_ETR_COMP1 TIM_AF1_ETRSEL_0 /*!< TIM3_ETR is connected to COMP1 output */ #define TIM_TIM3_ETR_COMP2 TIM_AF1_ETRSEL_1 /*!< TIM3_ETR is connected to COMP2 output */ #define TIM_TIM3_ETR_HSI TIM_AF1_ETRSEL_2 /*!< TIM3_ETR is connected to HSI */ #define TIM_TIM3_ETR_TIM2_ETR TIM_AF1_ETRSEL_3 /*!< TIM3_ETR is connected to TIM2 ETR */ +#if defined(TIM4) +#define TIM_TIM3_ETR_TIM4_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_0) /*!< TIM3_ETR is connected to TIM4 ETR */ +#endif /* TIM4 */ #define TIM_TIM3_ETR_ADC4_AWD1 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1| TIM_AF1_ETRSEL_0) /*!< TIM3_ETR is connected to ADC4 AWD1 */ #define TIM_TIM3_ETR_ADC4_AWD2 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2) /*!< TIM3_ETR is connected to ADC4 AWD2 */ #define TIM_TIM3_ETR_ADC4_AWD3 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) /*!< TIM3_ETR is connected to ADC4 AWD3 */ +#endif /* TIM3 */ + +#if defined(TIM4) +#define TIM_TIM4_ETR_GPIO 0x00000000UL /*!< TIM4_ETR is not connected to I/O */ +#define TIM_TIM4_ETR_COMP1 TIM_AF1_ETRSEL_0 /*!< TIM4_ETR is connected to COMP1 output */ +#define TIM_TIM4_ETR_COMP2 TIM_AF1_ETRSEL_1 /*!< TIM4_ETR is connected to COMP2 output */ +#define TIM_TIM4_ETR_HSI TIM_AF1_ETRSEL_2 /*!< TIM4_ETR is connected to HSI */ +#define TIM_TIM4_ETR_TIM3_ETR TIM_AF1_ETRSEL_3 /*!< TIM4_ETR is connected to TIM3 ETR */ +#endif /* TIM4 */ /** * @} */ @@ -137,7 +164,9 @@ typedef struct * @{ */ #define TIM_BREAKINPUT_BRK 0x00000001U /*!< Timer break input */ +#if defined(TIM_BDTR_BK2E) #define TIM_BREAKINPUT_BRK2 0x00000002U /*!< Timer break2 input */ +#endif /* TIM_BDTR_BK2E */ /** * @} */ @@ -146,8 +175,10 @@ typedef struct * @{ */ #define TIM_BREAKINPUTSOURCE_BKIN 0x00000001U /*!< An external source (GPIO) is connected to the BKIN pin */ +#if defined(COMP1) && defined(COMP2) #define TIM_BREAKINPUTSOURCE_COMP1 0x00000002U /*!< The COMP1 output is connected to the break input */ #define TIM_BREAKINPUTSOURCE_COMP2 0x00000004U /*!< The COMP2 output is connected to the break input */ +#endif /* COMP1 && COMP2 */ /** * @} */ @@ -173,24 +204,33 @@ typedef struct /** @defgroup TIMEx_Timer_Input_Selection TIM Extended Timer input selection * @{ */ +#if defined(TIM1) #define TIM_TIM1_TI1_GPIO 0x00000000UL /*!< TIM1_TI1 is connected to GPIO */ #define TIM_TIM1_TI1_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM1_TI1 is connected to COMP1 OUT */ #define TIM_TIM1_TI1_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM1_TI1 is connected to COMP2 OUT */ #define TIM_TIM1_TI2_GPIO 0x00000000UL /*!< TIM1_TI2 is connected to GPIO */ #define TIM_TIM1_TI3_GPIO 0x00000000UL /*!< TIM1_TI3 is connected to GPIO */ #define TIM_TIM1_TI4_GPIO 0x00000000UL /*!< TIM1_TI4 is connected to GPIO */ +#endif /* TIM1 */ #define TIM_TIM2_TI1_GPIO 0x00000000UL /*!< TIM2_TI1 is connected to GPIO */ +#if defined(COMP1) && defined(COMP2) #define TIM_TIM2_TI1_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM2_TI1 is connected to COMP1 OUT */ #define TIM_TIM2_TI1_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM2_TI1 is connected to COMP2 OUT */ +#endif /* COMP1 && COMP2 */ #define TIM_TIM2_TI2_GPIO 0x00000000UL /*!< TIM2_TI2 is connected to GPIO */ +#if defined(COMP1) && defined(COMP2) #define TIM_TIM2_TI2_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM2_TI2 is connected to COMP1 OUT */ #define TIM_TIM2_TI2_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM2_TI2 is connected to COMP2 OUT */ +#endif /* COMP1 && COMP2 */ #define TIM_TIM2_TI3_GPIO 0x00000000UL /*!< TIM2_TI3 is connected to GPIO */ #define TIM_TIM2_TI4_GPIO 0x00000000UL /*!< TIM2_TI4 is connected to GPIO */ +#if defined(COMP1) && defined(COMP2) #define TIM_TIM2_TI4_COMP1 TIM_TISEL_TI4SEL_0 /*!< TIM2_TI4 is connected to COMP1 OUT */ #define TIM_TIM2_TI4_COMP2 TIM_TISEL_TI4SEL_1 /*!< TIM2_TI4 is connected to COMP2 OUT */ +#endif /* COMP1 && COMP2 */ +#if defined(TIM3) #define TIM_TIM3_TI1_GPIO 0x00000000UL /*!< TIM3_TI1 is connected to GPIO */ #define TIM_TIM3_TI1_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM3_TI1 is connected to COMP1 OUT */ #define TIM_TIM3_TI1_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM3_TI1 is connected to COMP2 OUT */ @@ -199,6 +239,18 @@ typedef struct #define TIM_TIM3_TI2_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM3_TI2 is connected to COMP2 OUT */ #define TIM_TIM3_TI3_GPIO 0x00000000UL /*!< TIM3_TI3 is connected to GPIO */ #define TIM_TIM3_TI4_GPIO 0x00000000UL /*!< TIM3_TI4 is connected to GPIO */ +#endif /* TIM3 */ + +#if defined(TIM4) +#define TIM_TIM4_TI1_GPIO 0x00000000UL /*!< TIM4_TI1 is connected to GPIO */ +#define TIM_TIM4_TI1_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM4_TI1 is connected to COMP1 OUT */ +#define TIM_TIM4_TI1_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM4_TI1 is connected to COMP2 OUT */ +#define TIM_TIM4_TI2_GPIO 0x00000000UL /*!< TIM4_TI2 is connected to GPIO */ +#define TIM_TIM4_TI2_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM4_TI2 is connected to COMP1 OUT */ +#define TIM_TIM4_TI2_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM4_TI2 is connected to COMP2 OUT */ +#define TIM_TIM4_TI3_GPIO 0x00000000UL /*!< TIM4_TI3 is connected to GPIO */ +#define TIM_TIM4_TI4_GPIO 0x00000000UL /*!< TIM4_TI4 is connected to GPIO */ +#endif /* TIM4 */ #define TIM_TIM16_TI1_GPIO 0x00000000UL /*!< TIM16_TI1 is connected to GPIO */ #define TIM_TIM16_TI1_MCO TIM_TISEL_TI1SEL_1 /*!< TIM16_TI1 is connected to MCO */ @@ -393,12 +445,21 @@ typedef struct * @{ */ #define IS_TIM_REMAP(__REMAP__) ((((__REMAP__) & 0xFFFC3FFFU) == 0x00000000U)) + +#if defined(TIM_BDTR_BK2E) #define IS_TIM_BREAKINPUT(__BREAKINPUT__) (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || \ ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2)) +#else +#define IS_TIM_BREAKINPUT(__BREAKINPUT__) ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) +#endif /* TIM_BDTR_BK2E */ +#if defined(COMP1) && defined(COMP2) #define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2)) +#else +#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) ((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) +#endif /* COMP1 && COMP2 */ #define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \ ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE)) @@ -406,12 +467,70 @@ typedef struct #define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW) || \ ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH)) +#if !defined(TIM1) +#define IS_TIM_TISEL(__TISEL__) ((((__TISEL__) & 0xFFFFFFF0U) == 0x00000000U)) +#else #define IS_TIM_TISEL(__TISEL__) ((((__TISEL__) & 0xF0F0F0F0U) == 0x00000000U)) +#endif /* !TIM1 */ #define IS_TIM_TISEL_TIX_INSTANCE(INSTANCE, CHANNEL) \ - (IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) && ((CHANNEL) < TIM_CHANNEL_5)) + (IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) && ((CHANNEL) <= TIM_CHANNEL_4)) -#if defined(TIM3) +#if defined(TIM4) && defined(TIM3) +#define IS_TIM_CLOCKSOURCE_INSTANCE(INSTANCE, __CLOCK__) \ + ((((INSTANCE) == TIM1) && \ + (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) \ + || \ + (((INSTANCE) == TIM2) && \ + (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11))) \ + || \ + (((INSTANCE) == TIM3) && \ + (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) \ + || \ + (((INSTANCE) == TIM4) && \ + (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)))) +#elif defined(TIM3) #define IS_TIM_CLOCKSOURCE_INSTANCE(INSTANCE, __CLOCK__) \ ((((INSTANCE) == TIM1) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ @@ -448,7 +567,7 @@ typedef struct ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)))) -#else +#elif defined(TIM1) #define IS_TIM_CLOCKSOURCE_INSTANCE(INSTANCE, __CLOCK__) \ ((((INSTANCE) == TIM1) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ @@ -473,9 +592,80 @@ typedef struct ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)))) +#else +#if defined(USB_OTG_HS) || defined(USB_DRD_FS) +#define IS_TIM_CLOCKSOURCE_INSTANCE(INSTANCE, __CLOCK__) \ + (((INSTANCE) == TIM2) && \ + (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11))) +#else /* (USB_OTG_HS) || (USB_DRD_FS)*/ +#define IS_TIM_CLOCKSOURCE_INSTANCE(INSTANCE, __CLOCK__) \ + (((INSTANCE) == TIM2) && \ + (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) +#endif /* (USB_OTG_HS) || (USB_DRD_FS)*/ #endif /* TIM3 */ -#if defined(TIM3) +#if defined(TIM4) && defined(TIM3) +#define IS_TIM_TRIGGER_INSTANCE(INSTANCE, __SELECTION__) \ + ((((INSTANCE) == TIM1) && \ + (((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + ((__SELECTION__) == TIM_TS_TI1FP1) || \ + ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_ETRF) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8))) \ + || \ + (((INSTANCE) == TIM2) && \ + (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + ((__SELECTION__) == TIM_TS_TI1FP1) || \ + ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_ETRF) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_ITR11))) \ + || \ + (((INSTANCE) == TIM3) && \ + (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + ((__SELECTION__) == TIM_TS_TI1FP1) || \ + ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_ETRF) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8))) \ + || \ + (((INSTANCE) == TIM4) && \ + (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + ((__SELECTION__) == TIM_TS_TI1FP1) || \ + ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_ETRF) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8)))) +#elif defined(TIM3) #define IS_TIM_TRIGGER_INSTANCE(INSTANCE, __SELECTION__) \ ((((INSTANCE) == TIM1) && \ (((__SELECTION__) == TIM_TS_ITR1) || \ @@ -506,7 +696,7 @@ typedef struct ((__SELECTION__) == TIM_TS_ETRF) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8)))) -#else +#elif defined(TIM1) #define IS_TIM_TRIGGER_INSTANCE(INSTANCE, __SELECTION__) \ ((((INSTANCE) == TIM1) && \ (((__SELECTION__) == TIM_TS_ITR1) || \ @@ -527,9 +717,64 @@ typedef struct ((__SELECTION__) == TIM_TS_ETRF) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8)))) +#else +#if defined(USB_OTG_HS) || defined(USB_DRD_FS) +#define IS_TIM_TRIGGER_INSTANCE(INSTANCE, __SELECTION__) \ + (((INSTANCE) == TIM2) && \ + (((__SELECTION__) == TIM_TS_TI1F_ED) || \ + ((__SELECTION__) == TIM_TS_TI1FP1) || \ + ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_ETRF) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_ITR11))) +#else /* (USB_OTG_HS) || (USB_DRD_FS)*/ +#define IS_TIM_TRIGGER_INSTANCE(INSTANCE, __SELECTION__) \ + (((INSTANCE) == TIM2) && \ + (((__SELECTION__) == TIM_TS_TI1F_ED) || \ + ((__SELECTION__) == TIM_TS_TI1FP1) || \ + ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_ETRF) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8))) +#endif /* (USB_OTG_HS) || (USB_DRD_FS)*/ #endif /* TIM3 */ -#if defined(TIM3) +#if defined(TIM4) && defined(TIM3) +#define IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(INSTANCE, __SELECTION__) \ + ((((INSTANCE) == TIM1) && \ + (((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_NONE))) \ + || \ + (((INSTANCE) == TIM2) && \ + (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_ITR11) || \ + ((__SELECTION__) == TIM_TS_NONE))) \ + || \ + (((INSTANCE) == TIM3) && \ + (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_NONE))) \ + || \ + (((INSTANCE) == TIM4) && \ + (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_NONE)))) +#elif defined(TIM3) #define IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(INSTANCE, __SELECTION__) \ ((((INSTANCE) == TIM1) && \ (((__SELECTION__) == TIM_TS_ITR1) || \ @@ -551,7 +796,7 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_NONE)))) -#else +#elif defined(TIM1) #define IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(INSTANCE, __SELECTION__) \ ((((INSTANCE) == TIM1) && \ (((__SELECTION__) == TIM_TS_ITR1) || \ @@ -566,6 +811,21 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_NONE)))) +#else +#if defined(USB_OTG_HS) || defined(USB_DRD_FS) +#define IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(INSTANCE, __SELECTION__) \ + (((INSTANCE) == TIM2) && \ + (((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_ITR11) || \ + ((__SELECTION__) == TIM_TS_NONE))) +#else /* (USB_OTG_HS) || (USB_DRD_FS) */ +#define IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(INSTANCE, __SELECTION__) \ + (((INSTANCE) == TIM2) && \ + (((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_NONE))) +#endif /* (USB_OTG_HS) || (USB_DRD_FS) */ #endif /* TIM3 */ #define IS_TIM_OC_CHANNEL_MODE(__MODE__, __CHANNEL__) \ @@ -719,7 +979,9 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig); +#if defined(TIM_CCR5_CCR5) HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels); +#endif /* TIM_CCR5_CCR5 */ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel); @@ -756,7 +1018,9 @@ HAL_StatusTypeDef HAL_TIMEx_DisableEncoderFirstIndex(TIM_HandleTypeDef *htim); void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim); void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim); void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim); +#if defined(TIM_BDTR_BK2E) void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim); +#endif /* TIM_BDTR_BK2E */ void HAL_TIMEx_EncoderIndexCallback(TIM_HandleTypeDef *htim); void HAL_TIMEx_DirectionChangeCallback(TIM_HandleTypeDef *htim); void HAL_TIMEx_IndexErrorCallback(TIM_HandleTypeDef *htim); diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_uart.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_uart.h index 672a232fd1..f954d959cc 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_uart.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_uart.h @@ -47,12 +47,10 @@ typedef struct { uint32_t BaudRate; /*!< This member configures the UART communication baud rate. The baud rate register is computed using the following formula: - LPUART: - ======= + @note For LPUART : Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate))) - where lpuart_ker_ck_pres is the UART input clock divided by a prescaler - UART: - ===== + where lpuart_ker_ck_pres is the UART input clock divided by a prescaler. + @note For UART : - If oversampling is 16 or in LIN mode, Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate))) - If oversampling is 8, @@ -306,7 +304,6 @@ typedef enum HAL_UART_ABORT_COMPLETE_CB_ID = 0x05U, /*!< UART Abort Complete Callback ID */ HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< UART Abort Transmit Complete Callback ID */ HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< UART Abort Receive Complete Callback ID */ - HAL_UART_WAKEUP_CB_ID = 0x08U, /*!< UART Wakeup Callback ID */ HAL_UART_RX_FIFO_FULL_CB_ID = 0x09U, /*!< UART Rx Fifo Full Callback ID */ HAL_UART_TX_FIFO_EMPTY_CB_ID = 0x0AU, /*!< UART Tx Fifo Empty Callback ID */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_uart_ex.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_uart_ex.h index 2768570d6b..af0a7bd999 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_uart_ex.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_uart_ex.h @@ -244,8 +244,6 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, * @{ */ -void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart); - void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart); void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart); @@ -304,6 +302,99 @@ HAL_StatusTypeDef HAL_UARTEx_ClearConfigAutonomousMode(UART_HandleTypeDef *huart * @param __CLOCKSOURCE__ output variable. * @retval UART clocking source, written in __CLOCKSOURCE__. */ +#if defined(USART3) +#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK2: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ + case RCC_USART2CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART2CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART2CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART2CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + switch(__HAL_RCC_GET_USART3_SOURCE()) \ + { \ + case RCC_USART3CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART3CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART3CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART3CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == LPUART1) \ + { \ + switch(__HAL_RCC_GET_LPUART1_SOURCE()) \ + { \ + case RCC_LPUART1CLKSOURCE_PCLK7: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK7; \ + break; \ + case RCC_LPUART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_LPUART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_LPUART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) +#else #if defined(USART2) #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ @@ -426,6 +517,7 @@ HAL_StatusTypeDef HAL_UARTEx_ClearConfigAutonomousMode(UART_HandleTypeDef *huart } \ } while(0U) #endif /* USART2 */ +#endif /* USART3 */ /** @brief Report the UART mask to apply to retrieve the received data * according to the word length and to the parity bits activation. diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_usart.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_usart.h index 7613822ef7..7193941bc0 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_usart.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_usart.h @@ -550,10 +550,10 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin */ #define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)\ (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\ - ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR1 |= (1UL << ((__INTERRUPT__) & USART_IT_MASK))): \ ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\ - ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK)))) + ((__HANDLE__)->Instance->CR2 |= (1UL << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 |= (1UL << ((__INTERRUPT__) & USART_IT_MASK)))) /** @brief Disable the specified USART interrupt. * @param __HANDLE__ specifies the USART Handle. @@ -575,10 +575,10 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin */ #define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)\ (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\ - ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR1 &= ~ (1UL << ((__INTERRUPT__) & USART_IT_MASK))): \ ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\ - ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK)))) + ((__HANDLE__)->Instance->CR2 &= ~ (1UL << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ (1UL << ((__INTERRUPT__) & USART_IT_MASK)))) /** @brief Check whether the specified USART interrupt has occurred or not. * @param __HANDLE__ specifies the USART Handle. @@ -725,6 +725,78 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @param __CLOCKSOURCE__ output variable. * @retval the USART clocking source, written in __CLOCKSOURCE__. */ +#if defined(USART3) +#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK2: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK2; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ + case RCC_USART2CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART2CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART2CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART2CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + switch(__HAL_RCC_GET_USART3_SOURCE()) \ + { \ + case RCC_USART3CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART3CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART3CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART3CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) +#else #if defined(USART2) #define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ @@ -805,6 +877,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin } \ } while(0U) #endif /* USART2 */ +#endif /* USART3 */ /** @brief Check USART Baud rate. * @param __BAUDRATE__ Baudrate specified by the user. diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_adc.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_adc.h index 6ce70f66e0..7dcd465edc 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_adc.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_adc.h @@ -250,20 +250,37 @@ extern "C" { /* ADC internal channels related definitions */ +#if defined(STM32WBA62xx) || defined(STM32WBA63xx) || defined(STM32WBA64xx) || defined(STM32WBA65xx) || defined (STM32WBA6Mxx) /* Internal voltage reference VrefInt */ -#define VREFINT_CAL_ADDR ((uint16_t*) (0x0BF907A5UL)) /* Internal voltage reference, address of +#define VREFINT_CAL_ADDR ((const uint16_t*) (0x0BFA07A5UL)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */ +#else +/* Internal voltage reference VrefInt */ +#define VREFINT_CAL_ADDR ((const uint16_t*) (0x0BF907A5UL)) /* Internal voltage reference, address of + parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC + (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */ +#endif /* STM32WBA62xx || STM32WBA63xx || STM32WBA64xx || STM32WBA65xx || STM32WBA6Mxx */ #define VREFINT_CAL_VREF ( 3000UL) /* Analog voltage reference (Vref+) value with which VrefInt has been calibrated in production (tolerance: +-10 mV) (unit: mV). */ +#if defined(STM32WBA62xx) || defined(STM32WBA63xx) || defined(STM32WBA64xx) || defined(STM32WBA65xx) || defined (STM32WBA6Mxx) +/* Temperature sensor */ +#define TEMPSENSOR_CAL1_ADDR ((const uint16_t*) (0x0BFA0710UL)) /* Address of parameter TS_CAL1: On this series, + temperature sensor ADC raw data acquired at temperature 30 DegC + (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL2_ADDR ((const uint16_t*) (0x0BFA0742UL)) /* Address of parameter TS_CAL2: On this series, + temperature sensor ADC raw data acquired at temperature 130 DegC + (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ +#else /* Temperature sensor */ -#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x0BF90710UL)) /* Address of parameter TS_CAL1: On this series, +#define TEMPSENSOR_CAL1_ADDR ((const uint16_t*) (0x0BF90710UL)) /* Address of parameter TS_CAL1: On this series, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ -#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x0BF90742UL)) /* Address of parameter TS_CAL2: On this series, +#define TEMPSENSOR_CAL2_ADDR ((const uint16_t*) (0x0BF90742UL)) /* Address of parameter TS_CAL2: On this series, temperature sensor ADC raw data acquired at temperature 130 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ +#endif /* STM32WBA62xx || STM32WBA63xx || STM32WBA64xx || STM32WBA65xx || STM32WBA6Mxx */ #define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_bus.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_bus.h index de7f7862e1..af5a823e3d 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_bus.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_bus.h @@ -70,7 +70,12 @@ extern "C" { * @{ */ #define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU +#if defined(LPDMA1) +#define LL_AHB1_GRP1_PERIPH_LPDMA1 RCC_AHB1ENR_LPDMA1EN +#endif +#if defined(GPDMA1) #define LL_AHB1_GRP1_PERIPH_GPDMA1 RCC_AHB1ENR_GPDMA1EN +#endif #define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHB1ENR_FLASHEN #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN #define LL_AHB1_GRP1_PERIPH_TSC RCC_AHB1ENR_TSCEN @@ -90,7 +95,20 @@ extern "C" { #define LL_AHB2_GRP1_PERIPH_GPIOA RCC_AHB2ENR_GPIOAEN #define LL_AHB2_GRP1_PERIPH_GPIOB RCC_AHB2ENR_GPIOBEN #define LL_AHB2_GRP1_PERIPH_GPIOC RCC_AHB2ENR_GPIOCEN +#if defined(GPIOD) +#define LL_AHB2_GRP1_PERIPH_GPIOD RCC_AHB2ENR_GPIODEN +#endif /* GPIOD */ +#if defined(GPIOE) +#define LL_AHB2_GRP1_PERIPH_GPIOE RCC_AHB2ENR_GPIOEEN +#endif /* GPIOE */ +#if defined(GPIOG) +#define LL_AHB2_GRP1_PERIPH_GPIOG RCC_AHB2ENR_GPIOGEN +#endif /* GPIOG */ #define LL_AHB2_GRP1_PERIPH_GPIOH RCC_AHB2ENR_GPIOHEN +#if defined(USB_OTG_HS) +#define LL_AHB2_GRP1_PERIPH_OTG RCC_AHB2ENR_OTGEN +#define LL_AHB2_GRP1_PERIPH_OTGHSPHY RCC_AHB2ENR_OTGHSPHYEN +#endif /* USB_OTG_HS */ #define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN #define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN #define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN @@ -134,13 +152,25 @@ extern "C" { #if defined(TIM3) #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR1_TIM3EN #endif /* TIM3 */ +#if defined(TIM4) +#define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR1_TIM4EN +#endif /* TIM4 */ #if defined(WWDG) #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR1_WWDGEN #endif /* WWDG */ +#if defined(SPI2) +#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR1_SPI2EN +#endif /* SPI2 */ #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR1_USART2EN +#if defined(USART3) +#define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR1_USART3EN +#endif /* USART3 */ #if defined(I2C1) #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR1_I2C1EN #endif /* I2C1 */ +#if defined(I2C2) +#define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR1_I2C2EN +#endif /* I2C2 */ /** * @} */ @@ -150,6 +180,9 @@ extern "C" { * @{ */ #define LL_APB1_GRP2_PERIPH_ALL 0xFFFFFFFFU +#if defined(I2C4) +#define LL_APB1_GRP2_PERIPH_I2C4 RCC_APB1ENR2_I2C4EN +#endif /* I2C4 */ #if defined(LPTIM2) #define LL_APB1_GRP2_PERIPH_LPTIM2 RCC_APB1ENR2_LPTIM2EN #endif /* LPTIM2 */ @@ -191,6 +224,9 @@ extern "C" { #if defined(COMP1) #define LL_APB7_GRP1_PERIPH_COMP RCC_APB7ENR_COMPEN #endif /* COMP1 */ +#if defined(VREFBUF) +#define LL_APB7_GRP1_PERIPH_VREF RCC_APB7ENR_VREFEN +#endif /* VREFBUF */ #define LL_APB7_GRP1_PERIPH_RTCAPB RCC_APB7ENR_RTCAPBEN /** * @} @@ -211,7 +247,12 @@ extern "C" { */ /** * @brief Enable AHB1 peripherals clock. +#if defined(LPDMA1) + * @rmtoll AHB1ENR LPDMA1EN LL_AHB1_GRP1_EnableClock\n +#endif +#if defined(GPDMA1) * @rmtoll AHB1ENR GPDMA1EN LL_AHB1_GRP1_EnableClock\n +#endif * AHB1ENR FLASHEN LL_AHB1_GRP1_EnableClock\n * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n * AHB1ENR TSCEN LL_AHB1_GRP1_EnableClock\n @@ -221,7 +262,12 @@ extern "C" { * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_ALL * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH +#if defined(LPDMA1) + * @arg @ref LL_AHB1_GRP1_PERIPH_LPDMA1 (*) +#endif +#if defined(GPDMA1) * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 (*) +#endif * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG @@ -242,7 +288,12 @@ __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) /** * @brief Check if AHB1 peripheral clock is enabled or not +#if defined(LPDMA1) + * @rmtoll AHB1ENR LPDMA1EN LL_AHB1_GRP1_IsEnabledClock +#endif +#if defined(GPDMA1) * @rmtoll AHB1ENR GPDMA1EN LL_AHB1_GRP1_IsEnabledClock +#endif * AHB1ENR FLASHEN LL_AHB1_GRP1_IsEnabledClock\n * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n * AHB1ENR TSCEN LL_AHB1_GRP1_IsEnabledClock\n @@ -251,7 +302,12 @@ __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) * AHB1ENR SRAM1EN LL_AHB1_GRP1_IsEnabledClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_ALL +#if defined(LPDMA1) + * @arg @ref LL_AHB1_GRP1_PERIPH_LPDMA1 (*) +#endif +#if defined(GPDMA1) * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 (*) +#endif * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) @@ -269,7 +325,12 @@ __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) /** * @brief Disable AHB1 peripherals clock. +#if defined(LPDMA1) + * @rmtoll AHB1ENR LPDMA1EN LL_AHB1_GRP1_DisableClock +#endif +#if defined(GPDMA1) * @rmtoll AHB1ENR GPDMA1EN LL_AHB1_GRP1_DisableClock +#endif * AHB1ENR FLASHEN LL_AHB1_GRP1_DisableClock\n * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n * AHB1ENR TSCEN LL_AHB1_GRP1_DisableClock\n @@ -279,7 +340,12 @@ __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_ALL * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH +#if defined(LPDMA1) + * @arg @ref LL_AHB1_GRP1_PERIPH_LPDMA1 (*) +#endif +#if defined(GPDMA1) * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 (*) +#endif * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG @@ -296,13 +362,23 @@ __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) /** * @brief Force AHB1 peripherals reset. +#if defined(LPDMA1) + * @rmtoll AHB1RSTR LPDMA1RSTR LL_AHB1_GRP1_ForceReset\n +#endif +#if defined(GPDMA1) * @rmtoll AHB1RSTR GPDMA1RSTR LL_AHB1_GRP1_ForceReset\n +#endif * AHB1RSTR CRCRSTR LL_AHB1_GRP1_ForceReset\n * AHB1RSTR TSCRSTR LL_AHB1_GRP1_ForceReset\n * AHB1RSTR RAMCFGRSTR LL_AHB1_GRP1_ForceReset * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_ALL +#if defined(LPDMA1) + * @arg @ref LL_AHB1_GRP1_PERIPH_LPDMA1 (*) +#endif +#if defined(GPDMA1) * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 (*) +#endif * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) @@ -316,13 +392,23 @@ __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) /** * @brief Release AHB1 peripherals reset. +#if defined(LPDMA1) + * @rmtoll AHB1RSTR LPDMA1RSTR LL_AHB1_GRP1_ReleaseReset\n +#endif +#if defined(GPDMA1) * @rmtoll AHB1RSTR GPDMA1RSTR LL_AHB1_GRP1_ReleaseReset\n +#endif * AHB1RSTR CRCRSTR LL_AHB1_GRP1_ReleaseReset\n * AHB1RSTR TSCRSTR LL_AHB1_GRP1_ReleaseReset\n * AHB1RSTR RAMCFGRSTR LL_AHB1_GRP1_ReleaseReset\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_ALL +#if defined(LPDMA1) + * @arg @ref LL_AHB1_GRP1_PERIPH_LPDMA1 (*) +#endif +#if defined(GPDMA1) * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 (*) +#endif * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) @@ -336,7 +422,12 @@ __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) /** * @brief Enable AHB1 peripheral clocks in Sleep and Stop modes +#if defined(LPDMA1) + * @rmtoll AHB1SMENR LPDMA1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n +#endif +#if defined(GPDMA1) * @rmtoll AHB1SMENR GPDMA1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n +#endif * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_EnableClockStopSleep\n * AHB1SMENR CRCSMEN LL_AHB1_GRP1_EnableClockStopSleep\n * AHB1SMENR TSCSMEN LL_AHB1_GRP1_EnableClockStopSleep\n @@ -345,7 +436,12 @@ __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_EnableClockStopSleep * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_ALL +#if defined(LPDMA1) + * @arg @ref LL_AHB1_GRP1_PERIPH_LPDMA1 (*) +#endif +#if defined(GPDMA1) * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 (*) +#endif * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH * @arg @ref LL_AHB1_GRP1_PERIPH_CRC @@ -368,7 +464,12 @@ __STATIC_INLINE void LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs) /** * @brief Check if AHB1 peripheral clocks in Sleep and Stop modes is enabled or not +#if defined(LPDMA1) + * @rmtoll AHB1SMENR LPDMA1SMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n +#endif +#if defined(GPDMA1) * @rmtoll AHB1SMENR GPDMA1SMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n +#endif * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n * AHB1SMENR CRCSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n * AHB1SMENR TSCSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n @@ -377,7 +478,12 @@ __STATIC_INLINE void LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs) * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_IsEnabledClockStopSleep * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_ALL +#if defined(LPDMA1) + * @arg @ref LL_AHB1_GRP1_PERIPH_LPDMA1 (*) +#endif +#if defined(GPDMA1) * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 (*) +#endif * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH * @arg @ref LL_AHB1_GRP1_PERIPH_CRC @@ -396,7 +502,12 @@ __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClockStopSleep(uint32_t Periphs) /** * @brief Disable AHB1 peripheral clocks in Sleep and Stop modes +#if defined(LPDMA1) + * @rmtoll AHB1SMENR LPDMA1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n +#endif +#if defined(GPDMA1) * @rmtoll AHB1SMENR GPDMA1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n +#endif * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_DisableClockStopSleep\n * AHB1SMENR CRCSMEN LL_AHB1_GRP1_DisableClockStopSleep\n * AHB1SMENR TSCSMEN LL_AHB1_GRP1_DisableClockStopSleep\n @@ -405,7 +516,12 @@ __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClockStopSleep(uint32_t Periphs) * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_DisableClockStopSleep * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_ALL +#if defined(LPDMA1) + * @arg @ref LL_AHB1_GRP1_PERIPH_LPDMA1 (*) +#endif +#if defined(GPDMA1) * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 (*) +#endif * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH * @arg @ref LL_AHB1_GRP1_PERIPH_CRC @@ -434,7 +550,20 @@ __STATIC_INLINE void LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs) * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_EnableClock\n * AHB2ENR GPIOBEN LL_AHB2_GRP1_EnableClock\n * AHB2ENR GPIOCEN LL_AHB2_GRP1_EnableClock\n +#if defined(GPIOD) + * AHB2ENR GPIODEN LL_AHB2_GRP1_EnableClock\n +#endif +#if defined(GPIOE) + * AHB2ENR GPIOEEN LL_AHB2_GRP1_EnableClock\n +#endif +#if defined(GPIOG) + * AHB2ENR GPIOGEN LL_AHB2_GRP1_EnableClock\n +#endif * AHB2ENR GPIOHEN LL_AHB2_GRP1_EnableClock\n +#if defined(USB_OTG_HS) + * AHB2ENR OTGEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR OTGHSPHYEN LL_AHB2_GRP1_EnableClock\n +#endif * AHB2ENR AESEN LL_AHB2_GRP1_EnableClock\n * AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock\n * AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock\n @@ -447,7 +576,20 @@ __STATIC_INLINE void LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs) * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC +#if defined(GPIOD) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*) +#endif +#if defined(GPIOE) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*) +#endif +#if defined(GPIOG) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*) +#endif * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH +#if defined(USB_OTG_HS) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTG (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTGHSPHY (*) +#endif * @arg @ref LL_AHB2_GRP1_PERIPH_AES * @arg @ref LL_AHB2_GRP1_PERIPH_HASH * @arg @ref LL_AHB2_GRP1_PERIPH_RNG @@ -473,7 +615,20 @@ __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_IsEnabledClock\n * AHB2ENR GPIOBEN LL_AHB2_GRP1_IsEnabledClock\n * AHB2ENR GPIOCEN LL_AHB2_GRP1_IsEnabledClock\n +#if defined(GPIOD) + * AHB2ENR GPIODEN LL_AHB2_GRP1_IsEnabledClock\n +#endif +#if defined(GPIOE) + * AHB2ENR GPIOEEN LL_AHB2_GRP1_IsEnabledClock\n +#endif +#if defined(GPIOG) + * AHB2ENR GPIOGEN LL_AHB2_GRP1_IsEnabledClock\n +#endif * AHB2ENR GPIOHEN LL_AHB2_GRP1_IsEnabledClock\n +#if defined(USB_OTG_HS) + * AHB2ENR OTGEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR OTGHSPHYEN LL_AHB2_GRP1_IsEnabledClock\n +#endif * AHB2ENR AESEN LL_AHB2_GRP1_IsEnabledClock\n * AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock\n * AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock\n @@ -486,7 +641,20 @@ __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC +#if defined(GPIOD) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*) +#endif +#if defined(GPIOE) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*) +#endif +#if defined(GPIOG) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*) +#endif * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH +#if defined(USB_OTG_HS) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTG (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTGHSPHY (*) +#endif * @arg @ref LL_AHB2_GRP1_PERIPH_AES * @arg @ref LL_AHB2_GRP1_PERIPH_HASH * @arg @ref LL_AHB2_GRP1_PERIPH_RNG @@ -508,7 +676,20 @@ __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_DisableClock\n * AHB2ENR GPIOBEN LL_AHB2_GRP1_DisableClock\n * AHB2ENR GPIOCEN LL_AHB2_GRP1_DisableClock\n +#if defined(GPIOD) + * AHB2ENR GPIODEN LL_AHB2_GRP1_DisableClock\n +#endif +#if defined(GPIOE) + * AHB2ENR GPIOEEN LL_AHB2_GRP1_DisableClock\n +#endif +#if defined(GPIOG) + * AHB2ENR GPIOGEN LL_AHB2_GRP1_DisableClock\n +#endif * AHB2ENR GPIOHEN LL_AHB2_GRP1_DisableClock\n +#if defined(USB_OTG_HS) + * AHB2ENR OTGEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR OTGHSPHYEN LL_AHB2_GRP1_DisableClock\n +#endif * AHB2ENR AESEN LL_AHB2_GRP1_DisableClock\n * AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock\n * AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock\n @@ -521,7 +702,20 @@ __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC +#if defined(GPIOD) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*) +#endif +#if defined(GPIOE) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*) +#endif +#if defined(GPIOG) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*) +#endif * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH +#if defined(USB_OTG_HS) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTG (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTGHSPHY (*) +#endif * @arg @ref LL_AHB2_GRP1_PERIPH_AES * @arg @ref LL_AHB2_GRP1_PERIPH_HASH * @arg @ref LL_AHB2_GRP1_PERIPH_RNG @@ -543,7 +737,19 @@ __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs) * @rmtoll AHB2RSTR GPIOARST LL_AHB2_GRP1_ForceReset\n * AHB2RSTR GPIOBRST LL_AHB2_GRP1_ForceReset\n * AHB2RSTR GPIOCRST LL_AHB2_GRP1_ForceReset\n +#if defined(GPIOD) + * AHB2RSTR GPIODRST LL_AHB2_GRP1_ForceReset\n +#endif +#if defined(GPIOE) + * AHB2RSTR GPIOERST LL_AHB2_GRP1_ForceReset\n +#endif +#if defined(GPIOG) + * AHB2RSTR GPIOGRST LL_AHB2_GRP1_ForceReset\n +#endif * AHB2RSTR GPIOHRST LL_AHB2_GRP1_ForceReset\n +#if defined(USB_OTG_HS) + * AHB2RSTR OTGRST LL_AHB2_GRP1_ForceReset\n +#endif * AHB2RSTR AESRST LL_AHB2_GRP1_ForceReset\n * AHB2RSTR HASHRST LL_AHB2_GRP1_ForceReset\n * AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset\n @@ -555,7 +761,19 @@ __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs) * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC +#if defined(GPIOD) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*) +#endif +#if defined(GPIOE) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*) +#endif +#if defined(GPIOG) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*) +#endif * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH +#if defined(USB_OTG_HS) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTG (*) +#endif * @arg @ref LL_AHB2_GRP1_PERIPH_AES * @arg @ref LL_AHB2_GRP1_PERIPH_HASH * @arg @ref LL_AHB2_GRP1_PERIPH_RNG @@ -576,7 +794,19 @@ __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs) * @rmtoll AHB2RSTR GPIOARST LL_AHB2_GRP1_ReleaseReset\n * AHB2RSTR GPIOBRST LL_AHB2_GRP1_ReleaseReset\n * AHB2RSTR GPIOCRST LL_AHB2_GRP1_ReleaseReset\n +#if defined(GPIOD) + * AHB2RSTR GPIODRST LL_AHB2_GRP1_ReleaseReset\n +#endif +#if defined(GPIOE) + * AHB2RSTR GPIOERST LL_AHB2_GRP1_ReleaseReset\n +#endif +#if defined(GPIOG) + * AHB2RSTR GPIOGRST LL_AHB2_GRP1_ReleaseReset\n +#endif * AHB2RSTR GPIOHRST LL_AHB2_GRP1_ReleaseReset\n +#if defined(USB_OTG_HS) + * AHB2RSTR OTGRST LL_AHB2_GRP1_ReleaseReset\n +#endif * AHB2RSTR AESRST LL_AHB2_GRP1_ReleaseReset\n * AHB2RSTR HASHRST LL_AHB2_GRP1_ReleaseReset\n * AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset\n @@ -589,7 +819,19 @@ __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs) * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC +#if defined(GPIOD) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*) +#endif +#if defined(GPIOE) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*) +#endif +#if defined(GPIOG) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*) +#endif * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH +#if defined(USB_OTG_HS) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTG (*) +#endif * @arg @ref LL_AHB2_GRP1_PERIPH_AES * @arg @ref LL_AHB2_GRP1_PERIPH_HASH * @arg @ref LL_AHB2_GRP1_PERIPH_RNG @@ -610,7 +852,20 @@ __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs) * @rmtoll AHB2SMENR GPIOASMEN LL_AHB2_GRP1_EnableClockStopSleep\n * AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_EnableClockStopSleep\n * AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_EnableClockStopSleep\n +#if defined(GPIOD) + * AHB2SMENR GPIODSMEN LL_AHB2_GRP1_EnableClockStopSleep\n +#endif +#if defined(GPIOE) + * AHB2SMENR GPIOESMEN LL_AHB2_GRP1_EnableClockStopSleep\n +#endif +#if defined(GPIOG) + * AHB2SMENR GPIOGSMEN LL_AHB2_GRP1_EnableClockStopSleep\n +#endif * AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_EnableClockStopSleep\n +#if defined(USB_OTG_HS) + * AHB2SMENR OTGSMEN LL_AHB2_GRP1_EnableClockStopSleep\n + * AHB2SMENR OTGHSPHYSMEN LL_AHB2_GRP1_EnableClockStopSleep\n +#endif * AHB2SMENR AESSMEN LL_AHB2_GRP1_EnableClockStopSleep\n * AHB2SMENR HASHSMEN LL_AHB2_GRP1_EnableClockStopSleep\n * AHB2SMENR RNGSMEN LL_AHB2_GRP1_EnableClockStopSleep\n @@ -621,7 +876,20 @@ __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs) * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC +#if defined(GPIOD) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*) +#endif +#if defined(GPIOE) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*) +#endif +#if defined(GPIOG) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*) +#endif * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH +#if defined(USB_OTG_HS) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTG (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTGHSPHY (*) +#endif * @arg @ref LL_AHB2_GRP1_PERIPH_AES * @arg @ref LL_AHB2_GRP1_PERIPH_HASH * @arg @ref LL_AHB2_GRP1_PERIPH_RNG @@ -646,7 +914,20 @@ __STATIC_INLINE void LL_AHB2_GRP1_EnableClockStopSleep(uint32_t Periphs) * @rmtoll AHB2SMENR GPIOASMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n * AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n * AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n +#if defined(GPIOD) + * AHB2SMENR GPIODSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n +#endif +#if defined(GPIOE) + * AHB2SMENR GPIOESMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n +#endif +#if defined(GPIOG) + * AHB2SMENR GPIOGSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n +#endif * AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n +#if defined(USB_OTG_HS) + * AHB2SMENR OTGSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n + * AHB2SMENR OTGHSPHYSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n +#endif * AHB2SMENR AESSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n * AHB2SMENR HASHSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n * AHB2SMENR RNGSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n @@ -657,7 +938,20 @@ __STATIC_INLINE void LL_AHB2_GRP1_EnableClockStopSleep(uint32_t Periphs) * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC +#if defined(GPIOD) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*) +#endif +#if defined(GPIOE) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*) +#endif +#if defined(GPIOG) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*) +#endif * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH +#if defined(USB_OTG_HS) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTG (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTGHSPHY (*) +#endif * @arg @ref LL_AHB2_GRP1_PERIPH_AES * @arg @ref LL_AHB2_GRP1_PERIPH_HASH * @arg @ref LL_AHB2_GRP1_PERIPH_RNG @@ -678,7 +972,20 @@ __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClockStopSleep(uint32_t Periphs) * @rmtoll AHB2SMENR GPIOASMEN LL_AHB2_GRP1_DisableClockStopSleep\n * AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_DisableClockStopSleep\n * AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_DisableClockStopSleep\n +#if defined(GPIOD) + * AHB2SMENR GPIODSMEN LL_AHB2_GRP1_DisableClockStopSleep\n +#endif +#if defined(GPIOE) + * AHB2SMENR GPIOESMEN LL_AHB2_GRP1_DisableClockStopSleep\n +#endif +#if defined(GPIOG) + * AHB2SMENR GPIOGSMEN LL_AHB2_GRP1_DisableClockStopSleep\n +#endif * AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_DisableClockStopSleep\n +#if defined(USB_OTG_HS) + * AHB2SMENR OTGSMEN LL_AHB2_GRP1_DisableClockStopSleep\n + * AHB2SMENR OTGHSPHYSMEN LL_AHB2_GRP1_DisableClockStopSleep\n +#endif * AHB2SMENR AESSMEN LL_AHB2_GRP1_DisableClockStopSleep\n * AHB2SMENR HASHSMEN LL_AHB2_GRP1_DisableClockStopSleep\n * AHB2SMENR RNGSMEN LL_AHB2_GRP1_DisableClockStopSleep\n @@ -689,7 +996,20 @@ __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClockStopSleep(uint32_t Periphs) * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC +#if defined(GPIOD) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*) +#endif +#if defined(GPIOE) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*) +#endif +#if defined(GPIOG) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*) +#endif * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH +#if defined(USB_OTG_HS) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTG (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTGHSPHY (*) +#endif * @arg @ref LL_AHB2_GRP1_PERIPH_AES * @arg @ref LL_AHB2_GRP1_PERIPH_HASH * @arg @ref LL_AHB2_GRP1_PERIPH_RNG @@ -999,20 +1319,44 @@ __STATIC_INLINE void LL_AHB5_GRP1_DisableClockStopSleep(uint32_t Periphs) * @brief Enable APB1 peripherals clock. * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_EnableClock\n * APB1ENR1 TIM3EN LL_APB1_GRP1_EnableClock\n +#if defined(TIM4) + * APB1ENR1 TIM4EN LL_APB1_GRP1_EnableClock\n +#endif #if defined(WWDG) * APB1ENR1 WWDGEN LL_APB1_GRP1_EnableClock\n +#endif +#if defined(SPI2) + * APB1ENR1 SPI2EN LL_APB1_GRP1_EnableClock\n #endif * APB1ENR1 USART2EN LL_APB1_GRP1_EnableClock\n +#if defined(USART3) + * APB1ENR1 USART3EN LL_APB1_GRP1_EnableClock\n +#endif * APB1ENR1 I2C1EN LL_APB1_GRP1_EnableClock\n +#if defined(I2C2) + * APB1ENR1 I2C2EN LL_APB1_GRP1_EnableClock +#endif * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP1_PERIPH_ALL * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) +#if defined(TIM4) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) +#endif #if defined(WWDG) * @arg @ref LL_APB1_GRP1_PERIPH_WWDG (*) +#endif +#if defined(SPI2) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) #endif * @arg @ref LL_APB1_GRP1_PERIPH_USART2 +#if defined(USART3) + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) +#endif * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 (*) +#if defined(I2C2) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) +#endif * * (*) value not defined in all devices. * @retval None @@ -1028,10 +1372,20 @@ __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) /** * @brief Enable APB1 peripherals clock. +#if defined(I2C4) + * @rmtoll APB1ENR2 I2C4EN LL_APB1_GRP2_EnableClock\n +#endif * APB1ENR2 LPTIM2EN LL_APB1_GRP2_EnableClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP2_PERIPH_ALL +#if defined(I2C4) + * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*) +#endif * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 +#if defined(I2C4) + * + * (*) value not defined in all devices. +#endif * @retval None */ __STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs) @@ -1047,20 +1401,44 @@ __STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs) * @brief Check if APB1 peripheral clock is enabled or not * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_IsEnabledClock\n * APB1ENR1 TIM3EN LL_APB1_GRP1_IsEnabledClock\n +#if defined(TIM4) + * APB1ENR1 TIM4EN LL_APB1_GRP1_IsEnabledClock\n +#endif #if defined(WWDG) * APB1ENR1 WWDGEN LL_APB1_GRP1_IsEnabledClock\n +#endif +#if defined(SPI2) + * APB1ENR1 SPI2EN LL_APB1_GRP1_IsEnabledClock\n #endif * APB1ENR1 USART2EN LL_APB1_GRP1_IsEnabledClock\n +#if defined(USART3) + * APB1ENR1 USART3EN LL_APB1_GRP1_IsEnabledClock\n +#endif * APB1ENR1 I2C1EN LL_APB1_GRP1_IsEnabledClock\n +#if defined(I2C2) + * APB1ENR1 I2C2EN LL_APB1_GRP1_IsEnabledClock +#endif * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP1_PERIPH_ALL * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) +#if defined(TIM4) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) +#endif #if defined(WWDG) * @arg @ref LL_APB1_GRP1_PERIPH_WWDG (*) +#endif +#if defined(SPI2) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) #endif * @arg @ref LL_APB1_GRP1_PERIPH_USART2 +#if defined(USART3) + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) +#endif * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 (*) +#if defined(I2C2) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) +#endif * * (*) value not defined in all devices. * @retval State of Periphs (1 or 0). @@ -1072,10 +1450,20 @@ __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) /** * @brief Check if APB1 peripheral clock is enabled or not +#if defined(I2C4) + * @rmtoll APB1ENR2 I2C4EN LL_APB1_GRP2_IsEnabledClock\n +#endif * APB1ENR2 LPTIM2EN LL_APB1_GRP2_IsEnabledClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP2_PERIPH_ALL +#if defined(I2C4) + * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*) +#endif * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 +#if defined(I2C4) + * + * (*) value not defined in all devices. +#endif * @retval State of Periphs (1 or 0). */ __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs) @@ -1087,18 +1475,42 @@ __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs) * @brief Disable APB1 peripherals clock. * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_DisableClock\n * APB1ENR1 TIM3EN LL_APB1_GRP1_DisableClock\n +#if defined(TIM4) + * APB1ENR1 TIM4EN LL_APB1_GRP1_DisableClock\n +#endif * APB1ENR1 WWDGEN LL_APB1_GRP1_DisableClock\n +#if defined(SPI2) + * APB1ENR1 SPI2EN LL_APB1_GRP1_DisableClock\n +#endif * APB1ENR1 USART2EN LL_APB1_GRP1_DisableClock\n +#if defined(USART3) + * APB1ENR1 USART3EN LL_APB1_GRP1_DisableClock\n +#endif * APB1ENR1 I2C1EN LL_APB1_GRP1_DisableClock\n +#if defined(I2C2) + * APB1ENR1 I2C2EN LL_APB1_GRP1_DisableClock +#endif * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP1_PERIPH_ALL * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) +#if defined(TIM4) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) +#endif #if defined(WWDG) * @arg @ref LL_APB1_GRP1_PERIPH_WWDG (*) +#endif +#if defined(SPI2) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) #endif * @arg @ref LL_APB1_GRP1_PERIPH_USART2 +#if defined(USART3) + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) +#endif * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 (*) +#if defined(I2C2) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) +#endif * * (*) value not defined in all devices. * @retval None @@ -1110,10 +1522,20 @@ __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) /** * @brief Disable APB1 peripherals clock. +#if defined(I2C4) + * @rmtoll APB1ENR2 I2C4EN LL_APB1_GRP2_DisableClock\n +#endif * APB1ENR2 LPTIM2EN LL_APB1_GRP2_DisableClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP2_PERIPH_ALL +#if defined(I2C4) + * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*) +#endif * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 +#if defined(I2C4) + * + * (*) value not defined in all devices. +#endif * @retval None */ __STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs) @@ -1125,14 +1547,38 @@ __STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs) * @brief Force APB1 peripherals reset. * @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ForceReset\n * APB1RSTR1 TIM3RST LL_APB1_GRP1_ForceReset\n +#if defined(TIM4) + * APB1RSTR1 TIM4RST LL_APB1_GRP1_ForceReset\n +#endif +#if defined(SPI2) + * APB1RSTR1 SPI2RST LL_APB1_GRP1_ForceReset\n +#endif * APB1RSTR1 USART2RST LL_APB1_GRP1_ForceReset\n +#if defined(USART3) + * APB1RSTR1 USART3RST LL_APB1_GRP1_ForceReset\n +#endif * APB1RSTR1 I2C1RST LL_APB1_GRP1_ForceReset\n +#if defined(I2C2) + * APB1RSTR1 I2C2RST LL_APB1_GRP1_ForceReset +#endif * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP1_PERIPH_ALL * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) +#if defined(TIM4) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) +#endif +#if defined(SPI2) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) +#endif * @arg @ref LL_APB1_GRP1_PERIPH_USART2 +#if defined(USART3) + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) +#endif * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 (*) +#if defined(I2C2) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) +#endif * * (*) value not defined in all devices. * @retval None @@ -1144,10 +1590,20 @@ __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) /** * @brief Force APB1 peripherals reset. +#if defined(I2C4) + * @rmtoll APB1RSTR2 I2C4RST LL_APB1_GRP2_ForceReset\n +#endif * APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ForceReset * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP2_PERIPH_ALL +#if defined(I2C4) + * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*) +#endif * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 +#if defined(I2C4) + * + * (*) value not defined in all devices. +#endif * @retval None */ __STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs) @@ -1159,14 +1615,38 @@ __STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs) * @brief Release APB1 peripherals reset. * @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ReleaseReset\n * APB1RSTR1 TIM3RST LL_APB1_GRP1_ReleaseReset\n +#if defined(TIM4) + * APB1RSTR1 TIM4RST LL_APB1_GRP1_ReleaseReset\n +#endif +#if defined(SPI2) + * APB1RSTR1 SPI2RST LL_APB1_GRP1_ReleaseReset\n +#endif * APB1RSTR1 USART2RST LL_APB1_GRP1_ReleaseReset\n +#if defined(USART3) + * APB1RSTR1 USART3RST LL_APB1_GRP1_ReleaseReset\n +#endif * APB1RSTR1 I2C1RST LL_APB1_GRP1_ReleaseReset\n +#if defined(I2C2) + * APB1RSTR1 I2C2RST LL_APB1_GRP1_ReleaseReset +#endif * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP1_PERIPH_ALL * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) +#if defined(TIM4) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) +#endif +#if defined(SPI2) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) +#endif * @arg @ref LL_APB1_GRP1_PERIPH_USART2 +#if defined(USART3) + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) +#endif * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 (*) +#if defined(I2C2) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) +#endif * * (*) value not defined in all devices. * @retval None @@ -1178,10 +1658,20 @@ __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) /** * @brief Release APB1 peripherals reset. +#if defined(I2C4) + * @rmtoll APB1RSTR2 I2C4RST LL_APB1_GRP2_ReleaseReset\n +#endif * APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ReleaseReset * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP2_PERIPH_ALL +#if defined(I2C4) + * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*) +#endif * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 +#if defined(I2C4) + * + * (*) value not defined in all devices. +#endif * @retval None */ __STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs) @@ -1193,20 +1683,44 @@ __STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs) * @brief Enable APB1 peripheral clocks in Sleep and Stop modes * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_EnableClockStopSleep\n * APB1SMENR1 TIM3SMEN LL_APB1_GRP1_EnableClockStopSleep\n +#if defined(TIM4) + * APB1SMENR1 TIM4SMEN LL_APB1_GRP1_EnableClockStopSleep\n +#endif #if defined(WWDG) * APB1SMENR1 WWDGSMEN LL_APB1_GRP1_EnableClockStopSleep\n +#endif +#if defined(SPI2) + * APB1SMENR1 SPI2SMEN LL_APB1_GRP1_EnableClockStopSleep\n #endif * APB1SMENR1 USART2SMEN LL_APB1_GRP1_EnableClockStopSleep\n +#if defined(USART3) + * APB1SMENR1 USART3SMEN LL_APB1_GRP1_EnableClockStopSleep\n +#endif * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_EnableClockStopSleep\n +#if defined(I2C2) + * APB1SMENR1 I2C2SMEN LL_APB1_GRP1_EnableClockStopSleep +#endif * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP1_PERIPH_ALL * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) +#if defined(TIM4) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) +#endif #if defined(WWDG) * @arg @ref LL_APB1_GRP1_PERIPH_WWDG (*) +#endif +#if defined(SPI2) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) #endif * @arg @ref LL_APB1_GRP1_PERIPH_USART2 +#if defined(USART3) + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) +#endif * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 (*) +#if defined(I2C2) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) +#endif * * (*) value not defined in all devices. * @retval None @@ -1224,20 +1738,44 @@ __STATIC_INLINE void LL_APB1_GRP1_EnableClockStopSleep(uint32_t Periphs) * @brief Check if APB1 peripheral clocks in Sleep and Stop modes is enabled or not * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n * APB1SMENR1 TIM3SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n +#if defined(TIM4) + * APB1SMENR1 TIM4SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n +#endif #if defined(WWDG) * APB1SMENR1 WWDGSMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n +#endif +#if defined(SPI2) + * APB1SMENR1 SPI2SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n #endif * APB1SMENR1 USART2SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n +#if defined(USART3) + * APB1SMENR1 USART3SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n +#endif * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n +#if defined(I2C2) + * APB1SMENR1 I2C2SMEN LL_APB1_GRP1_IsEnabledClockStopSleep +#endif * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP1_PERIPH_ALL * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) +#if defined(TIM4) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) +#endif #if defined(WWDG) * @arg @ref LL_APB1_GRP1_PERIPH_WWDG (*) +#endif +#if defined(SPI2) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) #endif * @arg @ref LL_APB1_GRP1_PERIPH_USART2 +#if defined(USART3) + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) +#endif * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 (*) +#if defined(I2C2) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) +#endif * * (*) value not defined in all devices. * @retval State of Periphs (1 or 0). @@ -1251,20 +1789,44 @@ __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClockStopSleep(uint32_t Periphs) * @brief Disable APB1 peripheral clocks in Sleep and Stop modes * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_DisableClockStopSleep\n * APB1SMENR1 TIM3SMEN LL_APB1_GRP1_DisableClockStopSleep\n +#if defined(TIM4) + * APB1SMENR1 TIM4SMEN LL_APB1_GRP1_DisableClockStopSleep\n +#endif #if defined(WWDG) * APB1SMENR1 WWDGSMEN LL_APB1_GRP1_DisableClockStopSleep\n +#endif +#if defined(SPI2) + * APB1SMENR1 SPI2SMEN LL_APB1_GRP1_DisableClockStopSleep\n #endif * APB1SMENR1 USART2SMEN LL_APB1_GRP1_DisableClockStopSleep\n +#if defined(USART3) + * APB1SMENR1 USART3SMEN LL_APB1_GRP1_DisableClockStopSleep\n +#endif * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_DisableClockStopSleep\n +#if defined(I2C2) + * APB1SMENR1 I2C2SMEN LL_APB1_GRP1_DisableClockStopSleep +#endif * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP1_PERIPH_ALL * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) +#if defined(TIM4) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) +#endif #if defined(WWDG) * @arg @ref LL_APB1_GRP1_PERIPH_WWDG (*) +#endif +#if defined(SPI2) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) #endif * @arg @ref LL_APB1_GRP1_PERIPH_USART2 +#if defined(USART3) + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) +#endif * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 (*) +#if defined(I2C2) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) +#endif * * (*) value not defined in all devices. * @retval None @@ -1276,10 +1838,20 @@ __STATIC_INLINE void LL_APB1_GRP1_DisableClockStopSleep(uint32_t Periphs) /** * @brief Enable APB1 peripheral clocks in Sleep and Stop modes +#if defined(I2C4) + * @rmtoll APB1SMENR2 I2C4SMEN LL_APB1_GRP2_EnableClockStopSleep\n +#endif * APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_EnableClockStopSleep * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP2_PERIPH_ALL +#if defined(I2C4) + * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*) +#endif * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 +#if defined(I2C4) + * + * (*) value not defined in all devices. +#endif * @retval None */ __STATIC_INLINE void LL_APB1_GRP2_EnableClockStopSleep(uint32_t Periphs) @@ -1293,10 +1865,20 @@ __STATIC_INLINE void LL_APB1_GRP2_EnableClockStopSleep(uint32_t Periphs) /** * @brief Check if APB1 peripheral clocks in Sleep and Stop modes is enabled or not +#if defined(I2C4) + * @rmtoll APB1SMENR2 I2C4SMEN LL_APB1_GRP2_IsEnabledClockStopSleep\n +#endif * APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_IsEnabledClockStopSleep * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP2_PERIPH_ALL +#if defined(I2C4) + * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*) +#endif * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 +#if defined(I2C4) + * + * (*) value not defined in all devices. +#endif * @retval State of Periphs (1 or 0). */ __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClockStopSleep(uint32_t Periphs) @@ -1306,9 +1888,20 @@ __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClockStopSleep(uint32_t Periphs) /** * @brief Disable APB1 peripheral clocks in Sleep and Stop modes +#if defined(I2C4) + * @rmtoll APB1SMENR2 I2C4SMEN LL_APB1_GRP2_DisableClockStopSleep\n +#endif * APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_DisableClockStopSleep * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP2_PERIPH_ALL +#if defined(I2C4) + * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*) +#endif +#if defined(I2C4) + * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 + * + * (*) value not defined in all devices. +#endif * @retval None */ __STATIC_INLINE void LL_APB1_GRP2_DisableClockStopSleep(uint32_t Periphs) @@ -1550,6 +2143,9 @@ __STATIC_INLINE void LL_APB2_GRP1_DisableClockStopSleep(uint32_t Periphs) * APB7ENR I2C3EN LL_APB7_GRP1_EnableClock\n * APB7ENR LPTIM1EN LL_APB7_GRP1_EnableClock\n * APB7ENR COMPEN LL_APB7_GRP1_EnableClock\n +#if defined(VREFBUF) + * APB7ENR VREFEN LL_APB7_GRP1_EnableClock\n +#endif * APB7ENR RTCAPBEN LL_APB7_GRP1_EnableClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB7_GRP1_PERIPH_ALL @@ -1559,6 +2155,9 @@ __STATIC_INLINE void LL_APB2_GRP1_DisableClockStopSleep(uint32_t Periphs) * @arg @ref LL_APB7_GRP1_PERIPH_I2C3 * @arg @ref LL_APB7_GRP1_PERIPH_LPTIM1 * @arg @ref LL_APB7_GRP1_PERIPH_COMP (*) +#if defined(VREFBUF) + * @arg @ref LL_APB7_GRP1_PERIPH_VREF (*) +#endif * @arg @ref LL_APB7_GRP1_PERIPH_RTCAPB * * (*) value not defined in all devices. @@ -1581,6 +2180,9 @@ __STATIC_INLINE void LL_APB7_GRP1_EnableClock(uint32_t Periphs) * APB7ENR I2C3EN LL_APB7_GRP1_IsEnabledClock\n * APB7ENR LPTIM1EN LL_APB7_GRP1_IsEnabledClock\n * APB7ENR COMPEN LL_APB7_GRP1_IsEnabledClock\n +#if defined(VREFBUF) + * APB7ENR VREFEN LL_APB7_GRP1_IsEnabledClock\n +#endif * APB7ENR RTCAPBEN LL_APB7_GRP1_IsEnabledClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB7_GRP1_PERIPH_ALL @@ -1590,6 +2192,9 @@ __STATIC_INLINE void LL_APB7_GRP1_EnableClock(uint32_t Periphs) * @arg @ref LL_APB7_GRP1_PERIPH_I2C3 * @arg @ref LL_APB7_GRP1_PERIPH_LPTIM1 * @arg @ref LL_APB7_GRP1_PERIPH_COMP (*) +#if defined(VREFBUF) + * @arg @ref LL_APB7_GRP1_PERIPH_VREF (*) +#endif * @arg @ref LL_APB7_GRP1_PERIPH_RTCAPB * * (*) value not defined in all devices. @@ -1608,6 +2213,9 @@ __STATIC_INLINE uint32_t LL_APB7_GRP1_IsEnabledClock(uint32_t Periphs) * APB7ENR I2C3EN LL_APB7_GRP1_DisableClock\n * APB7ENR LPTIM1EN LL_APB7_GRP1_DisableClock\n * APB7ENR COMPEN LL_APB7_GRP1_DisableClock\n +#if defined(VREFBUF) + * APB7ENR VREFEN LL_APB7_GRP1_DisableClock\n +#endif * APB7ENR RTCAPBEN LL_APB7_GRP1_DisableClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB7_GRP1_PERIPH_ALL @@ -1617,6 +2225,9 @@ __STATIC_INLINE uint32_t LL_APB7_GRP1_IsEnabledClock(uint32_t Periphs) * @arg @ref LL_APB7_GRP1_PERIPH_I2C3 * @arg @ref LL_APB7_GRP1_PERIPH_LPTIM1 * @arg @ref LL_APB7_GRP1_PERIPH_COMP (*) +#if defined(VREFBUF) + * @arg @ref LL_APB7_GRP1_PERIPH_VREF (*) +#endif * @arg @ref LL_APB7_GRP1_PERIPH_RTCAPB * * (*) value not defined in all devices. @@ -1635,6 +2246,9 @@ __STATIC_INLINE void LL_APB7_GRP1_DisableClock(uint32_t Periphs) * APB7RSTR I2C3RST LL_APB7_GRP1_ForceReset\n * APB7RSTR LPTIM1RST LL_APB7_GRP1_ForceReset\n * APB7RSTR COMPRST LL_APB7_GRP1_ForceReset\n +#if defined(VREFBUF) + * APB7RSTR VREFRST LL_APB7_GRP1_ForceReset +#endif * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB7_GRP1_PERIPH_ALL * @arg @ref LL_APB7_GRP1_PERIPH_SYSCFG @@ -1643,6 +2257,9 @@ __STATIC_INLINE void LL_APB7_GRP1_DisableClock(uint32_t Periphs) * @arg @ref LL_APB7_GRP1_PERIPH_I2C3 * @arg @ref LL_APB7_GRP1_PERIPH_LPTIM1 * @arg @ref LL_APB7_GRP1_PERIPH_COMP (*) +#if defined(VREFBUF) + * @arg @ref LL_APB7_GRP1_PERIPH_VREF (*) +#endif * * (*) value not defined in all devices. * @retval None @@ -1660,6 +2277,9 @@ __STATIC_INLINE void LL_APB7_GRP1_ForceReset(uint32_t Periphs) * APB7RSTR I2C3RST LL_APB7_GRP1_ReleaseReset\n * APB7RSTR LPTIM1RST LL_APB7_GRP1_ReleaseReset\n * APB7RSTR COMPRST LL_APB7_GRP1_ReleaseReset\n +#if defined(VREFBUF) + * APB7RSTR VREFRST LL_APB7_GRP1_ReleaseReset +#endif * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB7_GRP1_PERIPH_ALL * @arg @ref LL_APB7_GRP1_PERIPH_SYSCFG @@ -1668,6 +2288,9 @@ __STATIC_INLINE void LL_APB7_GRP1_ForceReset(uint32_t Periphs) * @arg @ref LL_APB7_GRP1_PERIPH_I2C3 * @arg @ref LL_APB7_GRP1_PERIPH_LPTIM1 * @arg @ref LL_APB7_GRP1_PERIPH_COMP (*) +#if defined(VREFBUF) + * @arg @ref LL_APB7_GRP1_PERIPH_VREF (*) +#endif * * (*) value not defined in all devices. * @retval None @@ -1685,6 +2308,9 @@ __STATIC_INLINE void LL_APB7_GRP1_ReleaseReset(uint32_t Periphs) * APB7SMENR I2C3SMEN LL_APB7_GRP1_EnableClockStopSleep\n * APB7SMENR LPTIM1SMEN LL_APB7_GRP1_EnableClockStopSleep\n * APB7SMENR COMPSMEN LL_APB7_GRP1_EnableClockStopSleep\n +#if defined(VREFBUF) + * APB7SMENR VREFSMEN LL_APB7_GRP1_EnableClockStopSleep\n +#endif * APB7SMENR RTCAPBSMEN LL_APB7_GRP1_EnableClockStopSleep * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB7_GRP1_PERIPH_ALL @@ -1694,6 +2320,9 @@ __STATIC_INLINE void LL_APB7_GRP1_ReleaseReset(uint32_t Periphs) * @arg @ref LL_APB7_GRP1_PERIPH_I2C3 * @arg @ref LL_APB7_GRP1_PERIPH_LPTIM1 * @arg @ref LL_APB7_GRP1_PERIPH_COMP (*) +#if defined(VREFBUF) + * @arg @ref LL_APB7_GRP1_PERIPH_VREF (*) +#endif * @arg @ref LL_APB7_GRP1_PERIPH_RTCAPB * * (*) value not defined in all devices. @@ -1717,6 +2346,9 @@ __STATIC_INLINE void LL_APB7_GRP1_EnableClockStopSleep(uint32_t Periphs) * APB7SMENR I2C3SMEN LL_APB7_GRP1_IsEnabledClockStopSleep\n * APB7SMENR LPTIM1SMEN LL_APB7_GRP1_IsEnabledClockStopSleep\n * APB7SMENR COMPSMEN LL_APB7_GRP1_IsEnabledClockStopSleep\n +#if defined(VREFBUF) + * APB7SMENR VREFSMEN LL_APB7_GRP1_IsEnabledClockStopSleep\n +#endif * APB7SMENR RTCAPBSMEN LL_APB7_GRP1_IsEnabledClockStopSleep * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB7_GRP1_PERIPH_ALL @@ -1726,6 +2358,9 @@ __STATIC_INLINE void LL_APB7_GRP1_EnableClockStopSleep(uint32_t Periphs) * @arg @ref LL_APB7_GRP1_PERIPH_I2C3 * @arg @ref LL_APB7_GRP1_PERIPH_LPTIM1 * @arg @ref LL_APB7_GRP1_PERIPH_COMP (*) +#if defined(VREFBUF) + * @arg @ref LL_APB7_GRP1_PERIPH_VREF (*) +#endif * @arg @ref LL_APB7_GRP1_PERIPH_RTCAPB * * (*) value not defined in all devices. @@ -1744,6 +2379,9 @@ __STATIC_INLINE uint32_t LL_APB7_GRP1_IsEnabledClockStopSleep(uint32_t Periphs) * APB7SMENR I2C3SMEN LL_APB7_GRP1_DisableClockStopSleep\n * APB7SMENR LPTIM1SMEN LL_APB7_GRP1_DisableClockStopSleep\n * APB7SMENR COMPSMEN LL_APB7_GRP1_DisableClockStopSleep\n +#if defined(VREFBUF) + * APB7SMENR VREFSMEN LL_APB7_GRP1_DisableClockStopSleep\n +#endif * APB7SMENR RTCAPBSMEN LL_APB7_GRP1_DisableClockStopSleep * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB7_GRP1_PERIPH_ALL @@ -1753,6 +2391,9 @@ __STATIC_INLINE uint32_t LL_APB7_GRP1_IsEnabledClockStopSleep(uint32_t Periphs) * @arg @ref LL_APB7_GRP1_PERIPH_I2C3 * @arg @ref LL_APB7_GRP1_PERIPH_LPTIM1 * @arg @ref LL_APB7_GRP1_PERIPH_COMP (*) +#if defined(VREFBUF) + * @arg @ref LL_APB7_GRP1_PERIPH_VREF (*) +#endif * @arg @ref LL_APB7_GRP1_PERIPH_RTCAPB * * (*) value not defined in all devices. diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_comp.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_comp.h index 081cf9da75..be55c3c8f7 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_comp.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_comp.h @@ -344,7 +344,7 @@ typedef struct * @arg @ref LL_COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON * @retval None */ -__STATIC_INLINE void LL_COMP_SetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COMMON, uint32_t WindowMode) +__STATIC_INLINE void LL_COMP_SetCommonWindowMode(const COMP_Common_TypeDef *COMPxy_COMMON, uint32_t WindowMode) { /* Note: On this STM32 series, window mode can be set from any instance */ /* of the pair of comparator instances. */ @@ -403,7 +403,7 @@ __STATIC_INLINE uint32_t LL_COMP_GetCommonWindowMode(const COMP_Common_TypeDef * * @arg @ref LL_COMP_WINDOWOUTPUT_COMP2 * @retval None */ -__STATIC_INLINE void LL_COMP_SetCommonWindowOutput(COMP_Common_TypeDef *COMPxy_COMMON, uint32_t WindowOutput) +__STATIC_INLINE void LL_COMP_SetCommonWindowOutput(const COMP_Common_TypeDef *COMPxy_COMMON, uint32_t WindowOutput) { register __IO uint32_t *preg = __COMP_PTR_REG_OFFSET(COMPxy_COMMON->CSR_ODD, (WindowOutput & LL_COMP_WINDOWMODE_COMPX_REGOFFSET_MASK)); diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_cortex.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_cortex.h index aa1db7a068..3a4997eb02 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_cortex.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_cortex.h @@ -946,13 +946,13 @@ __STATIC_INLINE void LL_MPU_ConfigAttributes(uint32_t AttIndex, uint32_t Attrib if (AttIndex < LL_MPU_ATTRIBUTES_NUMBER4) { /* Modify Attr field of MPU_MAIR0 accordingly */ - MODIFY_REG(MPU->MAIR0, (0xFFU << (AttIndex * 8U)), (Attributes << (AttIndex * 8U))); + MODIFY_REG(MPU->MAIR0, (0xFFUL << (AttIndex * 8U)), (Attributes << (AttIndex * 8U))); } /* When selected index is in range [4;7] */ else { /* Modify Attr field of MPU_MAIR1 accordingly */ - MODIFY_REG(MPU->MAIR1, (0xFFU << ((AttIndex - 4U) * 8U)), (Attributes << ((AttIndex - 4U) * 8U))); + MODIFY_REG(MPU->MAIR1, (0xFFUL << ((AttIndex - 4U) * 8U)), (Attributes << ((AttIndex - 4U) * 8U))); } } @@ -979,13 +979,13 @@ __STATIC_INLINE void LL_MPU_ConfigAttributes_NS(uint32_t AttIndex, uint32_t Att if (AttIndex < LL_MPU_ATTRIBUTES_NUMBER4) { /* Modify Attr field of MPU_MAIR0_NS accordingly */ - MODIFY_REG(MPU_NS->MAIR0, (0xFFU << (AttIndex * 8U)), (Attributes << (AttIndex * 8U))); + MODIFY_REG(MPU_NS->MAIR0, (0xFFUL << (AttIndex * 8U)), (Attributes << (AttIndex * 8U))); } /* When selected index is in range [4;7] */ else { /* Modify Attr field of MPU_MAIR1_NS accordingly */ - MODIFY_REG(MPU_NS->MAIR1, (0xFFU << ((AttIndex - 4U) * 8U)), (Attributes << ((AttIndex - 4U) * 8U))); + MODIFY_REG(MPU_NS->MAIR1, (0xFFUL << ((AttIndex - 4U) * 8U)), (Attributes << ((AttIndex - 4U) * 8U))); } } #endif /* __ARM_FEATURE_CMSE */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_dma.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_dma.h index d6f86e9adc..8890519af7 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_dma.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_dma.h @@ -51,7 +51,7 @@ extern "C" { * @{ */ -#if defined (GPDMA1) +#if defined (GPDMA1) || defined (LPDMA1) /** @defgroup DMA_LL DMA * @{ @@ -128,13 +128,13 @@ typedef struct @ref LL_DMA_SetDataAlignment(). */ uint32_t SrcBurstLength; /*!< This field specify the source burst length of transfer in bytes. - Programming this field is mandatory for all available DMA channels. + Programming this field is not mandatory for LPDMA channels. This parameter must be a value between Min_Data = 1 and Max_Data = 64. This feature can be modified afterwards using unitary function @ref LL_DMA_SetSrcBurstLength(). */ uint32_t DestBurstLength; /*!< This field specify the destination burst length of transfer in bytes. - Programming this field is mandatory for all available DMA channels. + Programming this field is not mandatory for LPDMA channels. This parameter must be a value between Min_Data = 1 and Max_Data = 64. This feature can be modified afterwards using unitary function @ref LL_DMA_SetDestBurstLength(). */ @@ -206,37 +206,37 @@ typedef struct @ref LL_DMA_SetTransferEventMode(). */ uint32_t DestHWordExchange; /*!< This field specify the destination half word exchange. - Programming this field is mandatory for all available DMA channels. + Programming this field is not mandatory for LPDMA channels. This parameter can be a value of @ref DMA_LL_EC_DEST_HALFWORD_EXCHANGE. This feature can be modified afterwards using unitary function @ref LL_DMA_SetDestHWordExchange(). */ uint32_t DestByteExchange; /*!< This field specify the destination byte exchange. - Programming this field is mandatory for all available DMA channels. + Programming this field is not mandatory for LPDMA channels. This parameter can be a value of @ref DMA_LL_EC_DEST_BYTE_EXCHANGE. This feature can be modified afterwards using unitary function @ref LL_DMA_SetDestByteExchange(). */ uint32_t SrcByteExchange; /*!< This field specify the source byte exchange. - Programming this field is mandatory for all available DMA channels. + Programming this field is not mandatory for LPDMA channels. This parameter can be a value of @ref DMA_LL_EC_SRC_BYTE_EXCHANGE. This feature can be modified afterwards using unitary function @ref LL_DMA_SetSrcByteExchange(). */ uint32_t SrcAllocatedPort; /*!< This field specify the source allocated port. - Programming this field is mandatory for all available DMA channels. + Programming this field is not mandatory for LPDMA channels. This parameter can be a value of @ref DMA_LL_EC_SOURCE_ALLOCATED_PORT. This feature can be modified afterwards using unitary function @ref LL_DMA_SetSrcAllocatedPort(). */ uint32_t DestAllocatedPort; /*!< This field specify the destination allocated port. - Programming this field is mandatory for all available DMA channels. + Programming this field is not mandatory for LPDMA channels. This parameter can be a value of @ref DMA_LL_EC_DESTINATION_ALLOCATED_PORT. This feature can be modified afterwards using unitary function @ref LL_DMA_SetDestAllocatedPort(). */ uint32_t LinkAllocatedPort; /*!< This field specify the linked-list allocated port. - Programming this field is mandatory for all available DMA channels. + Programming this field is not mandatory for LPDMA channels. This parameter can be a value of @ref DMA_LL_EC_LINKED_LIST_ALLOCATED_PORT. This feature can be modified afterwards using unitary function @ref LL_DMA_SetLinkAllocatedPort(). */ @@ -281,7 +281,7 @@ typedef struct @ref LL_DMA_SetLinkStepMode(). */ uint32_t LinkAllocatedPort; /*!< This field specify the linked-list allocated port. - Programming this field is mandatory for all available DMA channels. + Programming this field is not mandatory for LPDMA channels. This parameter can be a value of @ref DMA_LL_EC_LINKED_LIST_ALLOCATED_PORT. This feature can be modified afterwards using unitary function @ref LL_DMA_SetLinkAllocatedPort(). */ @@ -305,6 +305,16 @@ typedef struct CTR1 register in UpdateRegisters fields if it is not enabled in the previous node. + If the node to be created is for LPDMA channels, there is no need to fill + the following fields for CTR1 register : + - DestAllocatedPort. + - DestHWordExchange. + - DestByteExchange. + - DestBurstLength. + - SrcAllocatedPort. + - SrcByteExchange. + - SrcBurstLength. + */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) uint32_t DestSecure; /*!< This field specify the destination secure. @@ -517,8 +527,14 @@ typedef struct /** @defgroup DMA_LL_EC_LINKED_LIST_ALLOCATED_PORT Linked List Allocated Port * @{ */ +#if defined(GPDMA1) #define LL_DMA_LINK_ALLOCATED_PORT0 0x00000000U /*!< Linked List Allocated Port 0 */ #define LL_DMA_LINK_ALLOCATED_PORT1 DMA_CCR_LAP /*!< Linked List Allocated Port 1 */ +#endif /* GPDMA1 */ +#if defined(LPDMA1) +#define LL_DMA_LINK_ALLOCATED_PORT0 0x00000000U /*!< Kept for porting purpose */ +#define LL_DMA_LINK_ALLOCATED_PORT1 LL_DMA_LINK_ALLOCATED_PORT0 /*!< Kept for porting purpose */ +#endif /* LPDMA1 */ /** * @} */ @@ -564,8 +580,14 @@ typedef struct /** @defgroup DMA_LL_EC_SOURCE_ALLOCATED_PORT Source Allocated Port * @{ */ +#if defined(GPDMA1) #define LL_DMA_SRC_ALLOCATED_PORT0 0x00000000U /*!< Source Allocated Port 0 */ #define LL_DMA_SRC_ALLOCATED_PORT1 DMA_CTR1_SAP /*!< Source Allocated Port 1 */ +#endif /* GPDMA1 */ +#if defined(LPDMA1) +#define LL_DMA_SRC_ALLOCATED_PORT0 0x00000000U /*!< Kept for porting purpose */ +#define LL_DMA_SRC_ALLOCATED_PORT1 LL_DMA_SRC_ALLOCATED_PORT0 /*!< Kept for porting purpose */ +#endif /* LPDMA1 */ /** * @} */ @@ -573,8 +595,14 @@ typedef struct /** @defgroup DMA_LL_EC_DESTINATION_ALLOCATED_PORT Destination Allocated Port * @{ */ +#if defined(GPDMA1) #define LL_DMA_DEST_ALLOCATED_PORT0 0x00000000U /*!< Destination Allocated Port 0 */ #define LL_DMA_DEST_ALLOCATED_PORT1 DMA_CTR1_DAP /*!< Destination Allocated Port 1 */ +#endif /* GPDMA1 */ +#if defined(LPDMA1) +#define LL_DMA_DEST_ALLOCATED_PORT0 0x00000000U /*!< Kept for porting purpose */ +#define LL_DMA_DEST_ALLOCATED_PORT1 LL_DMA_DEST_ALLOCATED_PORT0 /*!< Kept for porting purpose */ +#endif /* LPDMA1 */ /** * @} */ @@ -613,10 +641,12 @@ typedef struct If src data width > dest data width : => Left Aligned Right Truncated down to the destination data width */ +#if defined(GPDMA1) #define LL_DMA_DATA_PACK_UNPACK DMA_CTR1_PAM_1 /*!< If src data width < dest data width : => Packed at the destination data width If src data width > dest data width : => Unpacked at the destination data width */ +#endif /* GPDMA1 */ /** * @} */ @@ -697,9 +727,16 @@ typedef struct /** @defgroup DMA_LL_EC_TRANSFER_DIRECTION Transfer Direction * @{ */ +#if defined(GPDMA1) #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CTR2_SWREQ /*!< Memory to memory direction */ #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CTR2_DREQ /*!< Memory to peripheral direction */ +#endif /* GPDMA1 */ +#if defined(LPDMA1) +#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CTR2_SWREQ /*!< Memory to memory direction */ +#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Kept for porting purpose */ +#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH LL_DMA_DIRECTION_PERIPH_TO_MEMORY /*!< Kept for porting purpose */ +#endif /* LPDMA1 */ /** * @} */ @@ -737,7 +774,12 @@ typedef struct /** @defgroup DMA_LL_EC_LINKEDLIST_NODE_TYPE Linked list node type * @{ */ +#if defined(LPDMA1) +#define LL_DMA_LPDMA_LINEAR_NODE 0x00U /*!< LPDMA node : linear addressing node */ +#endif /* LPDMA1 */ +#if defined(GPDMA1) #define LL_DMA_GPDMA_LINEAR_NODE 0x01U /*!< GPDMA node : linear addressing node */ +#endif /* GPDMA1 */ /** * @} @@ -765,6 +807,48 @@ typedef struct /** @defgroup DMA_LL_EC_REQUEST_SELECTION Request Selection * @{ */ +#if defined (LPDMA1) +/* LPDMA1 requests */ +#define LL_LPDMA1_REQUEST_ADC4 0U /*!< LPDMA1 HW request is ADC4 */ + +#define LL_LPDMA1_REQUEST_SPI3_RX 3U /*!< LPDMA1 HW request is SPI3_RX */ +#define LL_LPDMA1_REQUEST_SPI3_TX 4U /*!< LPDMA1 HW request is SPI3_TX */ +#define LL_LPDMA1_REQUEST_I2C1_RX 5U /*!< LPDMA1 HW request is I2C1_RX */ +#define LL_LPDMA1_REQUEST_I2C1_TX 6U /*!< LPDMA1 HW request is I2C1_TX */ +#define LL_LPDMA1_REQUEST_I2C1_EVC 7U /*!< LPDMA1 HW request is I2C1_EVC */ +#define LL_LPDMA1_REQUEST_I2C3_RX 8U /*!< LPDMA1 HW request is I2C3_RX */ +#define LL_LPDMA1_REQUEST_I2C3_TX 9U /*!< LPDMA1 HW request is I2C3_TX */ +#define LL_LPDMA1_REQUEST_I2C3_EVC 10U /*!< LPDMA1 HW request is I2C3_EVC */ +#define LL_LPDMA1_REQUEST_USART1_RX 11U /*!< LPDMA1 HW request is USART1_RX */ +#define LL_LPDMA1_REQUEST_USART1_TX 12U /*!< LPDMA1 HW request is USART1_TX */ + +#define LL_LPDMA1_REQUEST_LPUART1_RX 15U /*!< LPDMA1 HW request is LPUART1_RX */ +#define LL_LPDMA1_REQUEST_LPUART1_TX 16U /*!< LPDMA1 HW request is LPUART1_TX */ +#define LL_LPDMA1_REQUEST_SAI1_A 17U /*!< LPDMA1 HW request is SAI1_A */ +#define LL_LPDMA1_REQUEST_SAI1_B 18U /*!< LPDMA1 HW request is SAI1_B */ + +#define LL_LPDMA1_REQUEST_TIM2_CH1 26U /*!< LPDMA1 HW request is TIM2_CH1 */ +#define LL_LPDMA1_REQUEST_TIM2_CH2 27U /*!< LPDMA1 HW request is TIM2_CH2 */ +#define LL_LPDMA1_REQUEST_TIM2_CH3 28U /*!< LPDMA1 HW request is TIM2_CH3 */ +#define LL_LPDMA1_REQUEST_TIM2_CH4 29U /*!< LPDMA1 HW request is TIM2_CH4 */ +#define LL_LPDMA1_REQUEST_TIM2_UP 30U /*!< LPDMA1 HW request is TIM2_UP */ +#define LL_LPDMA1_REQUEST_TIM16_CH1 31U /*!< LPDMA1 HW request is TIM16_CH1 */ +#define LL_LPDMA1_REQUEST_TIM16_UP 32U /*!< LPDMA1 HW request is TIM16_UP */ +#define LL_LPDMA1_REQUEST_TIM17_CH1 33U /*!< LPDMA1 HW request is TIM17_CH1 */ +#define LL_LPDMA1_REQUEST_TIM17_UP 34U /*!< LPDMA1 HW request is TIM17_UP */ + +#define LL_LPDMA1_REQUEST_AES_IN 35U /*!< LPDMA1 HW request is AES_IN */ +#define LL_LPDMA1_REQUEST_AES_OUT 36U /*!< LPDMA1 HW request is AES_OUT */ +#define LL_LPDMA1_REQUEST_HASH_IN 37U /*!< LPDMA1 HW request is HASH_IN */ +#define LL_LPDMA1_REQUEST_LPTIM1_IC1 38U /*!< LPDMA1 HW request is LPTIM1_IC1 */ +#define LL_LPDMA1_REQUEST_LPTIM1_IC2 39U /*!< LPDMA1 HW request is LPTIM1_IC2 */ +#define LL_LPDMA1_REQUEST_LPTIM1_UE 40U /*!< LPDMA1 HW request is LPTIM1_UE */ +#define LL_LPDMA1_REQUEST_LPTIM2_IC1 41U /*!< LPDMA1 HW request is LPTIM2_IC1 */ +#define LL_LPDMA1_REQUEST_LPTIM2_IC2 42U /*!< LPDMA1 HW request is LPTIM2_IC2 */ +#define LL_LPDMA1_REQUEST_LPTIM2_UE 46U /*!< LPDMA1 HW request is LPTIM2_UE */ + +#define LL_LPDMA1_REQUEST_XSPI1 44U /*!< LPDMA1 HW request is XSPI1 */ +#else /* GPDMA1 Hardware Requests */ #define LL_GPDMA1_REQUEST_ADC4 0U /*!< GPDMA1 HW request is ADC4 */ #if defined (SPI1) @@ -836,6 +920,32 @@ typedef struct #define LL_GPDMA1_REQUEST_LPTIM2_IC2 50U /*!< GPDMA1 HW request is LPTIM2_IC2 */ #define LL_GPDMA1_REQUEST_LPTIM2_UE 51U /*!< GPDMA1 HW request is LPTIM2_UE */ #endif /* LPTIM2 */ +#if defined (SPI2) +#define LL_GPDMA1_REQUEST_SPI2_RX 52U /*!< GPDMA1 HW request is SPI2_RX */ +#define LL_GPDMA1_REQUEST_SPI2_TX 53U /*!< GPDMA1 HW request is SPI2_TX */ +#endif /* SPI2 */ +#if defined (I2C2) +#define LL_GPDMA1_REQUEST_I2C2_RX 54U /*!< GPDMA1 HW request is I2C2_RX */ +#define LL_GPDMA1_REQUEST_I2C2_TX 55U /*!< GPDMA1 HW request is I2C2_TX */ +#define LL_GPDMA1_REQUEST_I2C2_EVC 56U /*!< GPDMA1 HW request is I2C2_EVC */ +#endif /* I2C2 */ +#if defined (I2C4) +#define LL_GPDMA1_REQUEST_I2C4_RX 57U /*!< GPDMA1 HW request is I2C4_RX */ +#define LL_GPDMA1_REQUEST_I2C4_TX 58U /*!< GPDMA1 HW request is I2C4_TX */ +#define LL_GPDMA1_REQUEST_I2C4_EVC 59U /*!< GPDMA1 HW request is I2C4_EVC */ +#endif /* I2C4 */ +#if defined (TIM4) +#define LL_GPDMA1_REQUEST_TIM4_CH1 60U /*!< GPDMA1 HW request is TIM4_CH1 */ +#define LL_GPDMA1_REQUEST_TIM4_CH2 61U /*!< GPDMA1 HW request is TIM4_CH2 */ +#define LL_GPDMA1_REQUEST_TIM4_CH3 62U /*!< GPDMA1 HW request is TIM4_CH3 */ +#define LL_GPDMA1_REQUEST_TIM4_CH4 63U /*!< GPDMA1 HW request is TIM4_CH4 */ +#define LL_GPDMA1_REQUEST_TIM4_UP 64U /*!< GPDMA1 HW request is TIM4_UP */ +#endif /* TIM4 */ +#if defined (USART3) +#define LL_GPDMA1_REQUEST_USART3_RX 65U /*!< GPDMA1 HW request is USART3_RX */ +#define LL_GPDMA1_REQUEST_USART3_TX 66U /*!< GPDMA1 HW request is USART3_TX */ +#endif /* USART3 */ +#endif /* LPDMA1 */ /** * @} */ @@ -843,6 +953,37 @@ typedef struct /** @defgroup DMA_LL_EC_TRIGGER_SELECTION Trigger Selection * @{ */ +#if defined (LPDMA1) +/* LPDMA1 Hardware Triggers */ +#define LL_LPDMA1_TRIGGER_EXTI_LINE0 0U /*!< LPDMA1 HW Trigger signal is EXTI_LINE0 */ +#define LL_LPDMA1_TRIGGER_EXTI_LINE1 1U /*!< LPDMA1 HW Trigger signal is EXTI_LINE1 */ +#define LL_LPDMA1_TRIGGER_EXTI_LINE2 2U /*!< LPDMA1 HW Trigger signal is EXTI_LINE2 */ +#define LL_LPDMA1_TRIGGER_EXTI_LINE3 3U /*!< LPDMA1 HW Trigger signal is EXTI_LINE3 */ +#define LL_LPDMA1_TRIGGER_EXTI_LINE4 4U /*!< LPDMA1 HW Trigger signal is EXTI_LINE4 */ +#define LL_LPDMA1_TRIGGER_EXTI_LINE5 5U /*!< LPDMA1 HW Trigger signal is EXTI_LINE5 */ +#define LL_LPDMA1_TRIGGER_EXTI_LINE6 6U /*!< LPDMA1 HW Trigger signal is EXTI_LINE6 */ +#define LL_LPDMA1_TRIGGER_EXTI_LINE7 7U /*!< LPDMA1 HW Trigger signal is EXTI_LINE7 */ +#define LL_LPDMA1_TRIGGER_TAMP_TRG1 8U /*!< LPDMA1 HW Trigger signal is TAMP_TRG1 */ +#define LL_LPDMA1_TRIGGER_TAMP_TRG2 9U /*!< LPDMA1 HW Trigger signal is TAMP_TRG2 */ +#define LL_LPDMA1_TRIGGER_TAMP_TRG3 10U /*!< LPDMA1 HW Trigger signal is TAMP_TRG3 */ +#define LL_LPDMA1_TRIGGER_LPTIM1_CH1 11U /*!< LPDMA1 HW Trigger signal is LPTIM1_CH1 */ +#define LL_LPDMA1_TRIGGER_LPTIM1_CH2 12U /*!< LPDMA1 HW Trigger signal is LPTIM1_CH2 */ +#define LL_LPDMA1_TRIGGER_LPTIM2_CH1 13U /*!< LPDMA1 HW Trigger signal is LPTIM2_CH1 */ +#define LL_LPDMA1_TRIGGER_LPTIM2_CH2 14U /*!< LPDMA1 HW Trigger signal is LPTIM2_CH2 */ +#define LL_LPDMA1_TRIGGER_RTC_ALRA_TRG 15U /*!< LPDMA1 HW Trigger signal is RTC_ALRA_TRG */ +#define LL_LPDMA1_TRIGGER_RTC_ALRB_TRG 16U /*!< LPDMA1 HW Trigger signal is RTC_ALRB_TRG */ +#define LL_LPDMA1_TRIGGER_RTC_WUT_TRG 17U /*!< LPDMA1 HW Trigger signal is RTC_WUT_TRG */ +#define LL_LPDMA1_TRIGGER_LPDMA1_CH0_TCF 18U /*!< LPDMA1 HW Trigger signal is LPDMA1_CH0_TCF */ +#define LL_LPDMA1_TRIGGER_LPDMA1_CH1_TCF 19U /*!< LPDMA1 HW Trigger signal is LPDMA1_CH1_TCF */ +#define LL_LPDMA1_TRIGGER_LPDMA1_CH2_TCF 20U /*!< LPDMA1 HW Trigger signal is LPDMA1_CH2_TCF */ +#define LL_LPDMA1_TRIGGER_LPDMA1_CH3_TCF 21U /*!< LPDMA1 HW Trigger signal is LPDMA1_CH3_TCF */ +#define LL_LPDMA1_TRIGGER_LPDMA1_CH4_TCF 22U /*!< LPDMA1 HW Trigger signal is LPDMA1_CH4_TCF */ +#define LL_LPDMA1_TRIGGER_LPDMA1_CH5_TCF 23U /*!< LPDMA1 HW Trigger signal is LPDMA1_CH5_TCF */ +#define LL_LPDMA1_TRIGGER_LPDMA1_CH6_TCF 24U /*!< LPDMA1 HW Trigger signal is LPDMA1_CH6_TCF */ +#define LL_LPDMA1_TRIGGER_LPDMA1_CH7_TCF 25U /*!< LPDMA1 HW Trigger signal is LPDMA1_CH7_TCF */ +#define LL_LPDMA1_TRIGGER_TIM2_TRGO 26U /*!< LPDMA1 HW Trigger signal is TIM2_TRGO */ +#define LL_LPDMA1_TRIGGER_ADC4_AWD1 27U /*!< LPDMA1 HW Trigger signal is ADC4_ADW1 */ +#else /* GPDMA1 Hardware Triggers */ #define LL_GPDMA1_TRIGGER_EXTI_LINE0 0U /*!< GPDMA1 HW Trigger signal is EXTI_LINE0 */ #define LL_GPDMA1_TRIGGER_EXTI_LINE1 1U /*!< GPDMA1 HW Trigger signal is EXTI_LINE1 */ @@ -883,6 +1024,10 @@ typedef struct #if defined (TIM3) #define LL_GPDMA1_TRIGGER_TIM3_TRGO 30U /*!< GPDMA1 HW Trigger signal is TIM3_TRGO */ #endif /* TIM3 */ +#if defined (TIM4) +#define LL_GPDMA1_TRIGGER_TIM4_TRGO 31U /*!< GPDMA1 HW Trigger signal is TIM4_TRGO */ +#endif /* TIM4 */ +#endif /* LPDMA1 */ /** * @} */ @@ -928,8 +1073,14 @@ typedef struct * @param __CHANNEL_INSTANCE__ DMAx_Channely. * @retval DMAx. */ +#if defined (GPDMA1) #define LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \ (GPDMA1) +#endif /* GPDMA1 */ +#if defined (LPDMA1) +#define LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \ + (LPDMA1) +#endif /* LPDMA1 */ /** * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y. @@ -952,6 +1103,7 @@ typedef struct * @param __CHANNEL__ LL_DMA_CHANNEL_y. * @retval DMAx_Channely. */ +#if defined (GPDMA1) #define LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_0))) \ ? GPDMA1_Channel0 : \ @@ -967,6 +1119,24 @@ typedef struct ? GPDMA1_Channel5 : \ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) \ ? GPDMA1_Channel6 : GPDMA1_Channel7) +#endif /* GPDMA1 */ +#if defined (LPDMA1) +#define LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ + ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)LPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_0))) \ + ? LPDMA1_Channel0 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)LPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) \ + ? LPDMA1_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)LPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) \ + ? LPDMA1_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)LPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) \ + ? LPDMA1_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)LPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) \ + ? LPDMA1_Channel4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)LPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) \ + ? LPDMA1_Channel5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)LPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) \ + ? LPDMA1_Channel6 : LPDMA1_Channel7) +#endif /* LPDMA1 */ /** * @} @@ -1216,8 +1386,14 @@ __STATIC_INLINE uint32_t LL_DMA_GetLinkedListBaseAddr(const DMA_TypeDef *DMAx, u __STATIC_INLINE void LL_DMA_ConfigControl(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) { uint32_t dma_base_addr = (uint32_t)DMAx; +#if defined(GPDMA1) MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, (DMA_CCR_PRIO | DMA_CCR_LAP | DMA_CCR_LSM), Configuration); +#endif /* GPDMA1 */ +#if defined(LPDMA1) + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, + (DMA_CCR_PRIO | DMA_CCR_LSM), Configuration); +#endif /* LPDMA1 */ } /** @@ -1273,6 +1449,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(const DMA_TypeDef *DMAx, return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PRIO)); } +#if defined(GPDMA1) /** * @brief Set linked-list allocated port. * @rmtoll CCR LAP LL_DMA_SetLinkAllocatedPort @@ -1321,6 +1498,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetLinkAllocatedPort(const DMA_TypeDef *DMAx, ui return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_LAP)); } +#endif /* GPDMA1 */ /** * @brief Set link step mode. * @note This API is used for all available DMA channels. @@ -1410,11 +1588,19 @@ __STATIC_INLINE uint32_t LL_DMA_GetLinkStepMode(const DMA_TypeDef *DMAx, uint32_ __STATIC_INLINE void LL_DMA_ConfigTransfer(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) { uint32_t dma_base_addr = (uint32_t)DMAx; +#if defined(GPDMA1) MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DAP | DMA_CTR1_DHX | DMA_CTR1_DBX | DMA_CTR1_SBX | DMA_CTR1_DINC | DMA_CTR1_SINC | \ DMA_CTR1_SAP | DMA_CTR1_PAM | DMA_CTR1_DDW_LOG2 | DMA_CTR1_SDW_LOG2, Configuration); +#endif /* GPDMA1 */ +#if defined(LPDMA1) + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, + DMA_CTR1_DINC | DMA_CTR1_SINC | DMA_CTR1_PAM | DMA_CTR1_DDW_LOG2 | \ + DMA_CTR1_SDW_LOG2, Configuration); +#endif /* LPDMA1 */ } +#if defined(GPDMA1) /** * @brief Configure source and destination burst length. * @rmtoll CTR1 DBL_1 LL_DMA_SetDestBurstLength\n @@ -1441,6 +1627,7 @@ __STATIC_INLINE void LL_DMA_ConfigBurstLength(const DMA_TypeDef *DMAx, uint32_t (DMA_CTR1_SBL_1 | DMA_CTR1_DBL_1), (((SrcBurstLength - 1U) << DMA_CTR1_SBL_1_Pos) & DMA_CTR1_SBL_1) | \ (((DestBurstLength - 1U) << DMA_CTR1_DBL_1_Pos) & DMA_CTR1_DBL_1)); } +#endif /* GPDMA1 */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** @@ -1614,6 +1801,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelSrcSecure(const DMA_TypeDef *DMA } #endif /* DMA_SECCFGR_SEC0 */ +#if defined(GPDMA1) /** * @brief Set destination allocated port. * @rmtoll CTR1 DAP LL_DMA_SetDestAllocatedPort @@ -1874,6 +2062,7 @@ __STATIC_INLINE void LL_DMA_SetDestIncMode(const DMA_TypeDef *DMAx, uint32_t Cha uint32_t dma_base_addr = (uint32_t)DMAx; MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DINC, DestInc); } +#endif /* GPDMA1 */ /** * @brief Get destination increment mode. * @note This API is used for all available DMA channels. @@ -1950,6 +2139,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetDestDataWidth(const DMA_TypeDef *DMAx, uint32 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DDW_LOG2)); } +#if defined(GPDMA1) /** * @brief Set source allocated port. * @rmtoll CTR1 SAP LL_DMA_SetSrcAllocatedPort @@ -1997,6 +2187,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetSrcAllocatedPort(const DMA_TypeDef *DMAx, uin uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SAP)); } +#endif /* GPDMA1 */ /** * @brief Set data alignment mode. @@ -2015,7 +2206,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetSrcAllocatedPort(const DMA_TypeDef *DMAx, uin * @param DataAlignment This parameter can be one of the following values: * @arg @ref LL_DMA_DATA_ALIGN_ZEROPADD * @arg @ref LL_DMA_DATA_ALIGN_SIGNEXTPADD - * @arg @ref LL_DMA_DATA_PACK_UNPACK + * @arg @ref LL_DMA_DATA_PACK_UNPACK (This value is not allowed for LPDMA channels) * @retval None. */ __STATIC_INLINE void LL_DMA_SetDataAlignment(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DataAlignment) @@ -2050,6 +2241,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetDataAlignment(const DMA_TypeDef *DMAx, uint32 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_PAM)); } +#if defined(GPDMA1) /** * @brief Set source burst length. * @rmtoll CTR1 SBL_1 LL_DMA_SetSrcBurstLength @@ -2095,6 +2287,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetSrcBurstLength(const DMA_TypeDef *DMAx, uint3 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SBL_1) >> DMA_CTR1_SBL_1_Pos) + 1U); } +#endif /* GPDMA1 */ /** * @brief Set source increment mode. @@ -2231,9 +2424,16 @@ __STATIC_INLINE uint32_t LL_DMA_GetSrcDataWidth(const DMA_TypeDef *DMAx, uint32_ __STATIC_INLINE void LL_DMA_ConfigChannelTransfer(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) { uint32_t dma_base_addr = (uint32_t)DMAx; +#if defined(GPDMA1) MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, (DMA_CTR2_TCEM | DMA_CTR2_TRIGPOL | DMA_CTR2_TRIGM | DMA_CTR2_DREQ | DMA_CTR2_SWREQ | DMA_CTR2_BREQ), Configuration); +#endif /* GPDMA1 */ +#if defined(LPDMA1) + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, + (DMA_CTR2_TCEM | DMA_CTR2_TRIGPOL | DMA_CTR2_TRIGM | DMA_CTR2_SWREQ | DMA_CTR2_BREQ), + Configuration); +#endif /* LPDMA1 */ } /** @@ -2418,8 +2618,14 @@ __STATIC_INLINE uint32_t LL_DMA_GetTriggerMode(const DMA_TypeDef *DMAx, uint32_t __STATIC_INLINE void LL_DMA_SetDataTransferDirection(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction) { uint32_t dma_base_addr = (uint32_t)DMAx; +#if defined(GPDMA1) MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_DREQ | DMA_CTR2_SWREQ, Direction); +#endif /* GPDMA1 */ +#if defined(LPDMA1) + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, + DMA_CTR2_SWREQ, Direction); +#endif /* LPDMA1 */ } /** @@ -2445,8 +2651,14 @@ __STATIC_INLINE void LL_DMA_SetDataTransferDirection(const DMA_TypeDef *DMAx, ui __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; +#if defined(GPDMA1) return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_DREQ | DMA_CTR2_SWREQ)); +#endif /* GPDMA1 */ +#if defined(LPDMA1) + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, + DMA_CTR2_SWREQ)); +#endif /* LPDMA1 */ } /** @@ -2581,6 +2793,40 @@ __STATIC_INLINE uint32_t LL_DMA_GetBlkHWRequest(const DMA_TypeDef *DMAx, uint32_ * @arg @ref LL_GPDMA1_REQUEST_TIM4_UP (*) * @arg @ref LL_GPDMA1_REQUEST_USART3_RX (*) * @arg @ref LL_GPDMA1_REQUEST_USART3_TX (*) + * @arg @ref LL_LPDMA1_REQUEST_ADC4 (*) + * @arg @ref LL_LPDMA1_REQUEST_SPI3_RX (*) + * @arg @ref LL_LPDMA1_REQUEST_SPI3_TX (*) + * @arg @ref LL_LPDMA1_REQUEST_I2C1_RX (*) + * @arg @ref LL_LPDMA1_REQUEST_I2C1_TX (*) + * @arg @ref LL_LPDMA1_REQUEST_I2C1_EVC (*) + * @arg @ref LL_LPDMA1_REQUEST_I2C3_RX (*) + * @arg @ref LL_LPDMA1_REQUEST_I2C3_TX (*) + * @arg @ref LL_LPDMA1_REQUEST_I2C3_EVC (*) + * @arg @ref LL_LPDMA1_REQUEST_USART1_RX (*) + * @arg @ref LL_LPDMA1_REQUEST_USART1_TX (*) + * @arg @ref LL_LPDMA1_REQUEST_LPUART1_RX (*) + * @arg @ref LL_LPDMA1_REQUEST_LPUART1_TX (*) + * @arg @ref LL_LPDMA1_REQUEST_SAI1_A (*) + * @arg @ref LL_LPDMA1_REQUEST_SAI1_B (*) + * @arg @ref LL_LPDMA1_REQUEST_TIM2_CH1 (*) + * @arg @ref LL_LPDMA1_REQUEST_TIM2_CH2 (*) + * @arg @ref LL_LPDMA1_REQUEST_TIM2_CH3 (*) + * @arg @ref LL_LPDMA1_REQUEST_TIM2_CH4 (*) + * @arg @ref LL_LPDMA1_REQUEST_TIM2_UP (*) + * @arg @ref LL_LPDMA1_REQUEST_TIM16_CH1 (*) + * @arg @ref LL_LPDMA1_REQUEST_TIM16_UP (*) + * @arg @ref LL_LPDMA1_REQUEST_TIM17_CH1 (*) + * @arg @ref LL_LPDMA1_REQUEST_TIM17_UP (*) + * @arg @ref LL_LPDMA1_REQUEST_AES_IN (*) + * @arg @ref LL_LPDMA1_REQUEST_AES_OUT (*) + * @arg @ref LL_LPDMA1_REQUEST_HASH_IN (*) + * @arg @ref LL_LPDMA1_REQUEST_LPTIM1_IC1 (*) + * @arg @ref LL_LPDMA1_REQUEST_LPTIM1_IC2 (*) + * @arg @ref LL_LPDMA1_REQUEST_LPTIM1_UE (*) + * @arg @ref LL_LPDMA1_REQUEST_LPTIM2_IC1 (*) + * @arg @ref LL_LPDMA1_REQUEST_LPTIM2_IC2 (*) + * @arg @ref LL_LPDMA1_REQUEST_LPTIM2_UE (*) + * @arg @ref LL_LPDMA1_REQUEST_XSPI1 (*) * @note (*) Availability depends on devices. * @retval None. */ @@ -2672,6 +2918,40 @@ __STATIC_INLINE void LL_DMA_SetPeriphRequest(const DMA_TypeDef *DMAx, uint32_t C * @arg @ref LL_GPDMA1_REQUEST_TIM4_UP (*) * @arg @ref LL_GPDMA1_REQUEST_USART3_RX (*) * @arg @ref LL_GPDMA1_REQUEST_USART3_TX (*) + * @arg @ref LL_LPDMA1_REQUEST_ADC4 (*) + * @arg @ref LL_LPDMA1_REQUEST_SPI3_RX (*) + * @arg @ref LL_LPDMA1_REQUEST_SPI3_TX (*) + * @arg @ref LL_LPDMA1_REQUEST_I2C1_RX (*) + * @arg @ref LL_LPDMA1_REQUEST_I2C1_TX (*) + * @arg @ref LL_LPDMA1_REQUEST_I2C1_EVC (*) + * @arg @ref LL_LPDMA1_REQUEST_I2C3_RX (*) + * @arg @ref LL_LPDMA1_REQUEST_I2C3_TX (*) + * @arg @ref LL_LPDMA1_REQUEST_I2C3_EVC (*) + * @arg @ref LL_LPDMA1_REQUEST_USART1_RX (*) + * @arg @ref LL_LPDMA1_REQUEST_USART1_TX (*) + * @arg @ref LL_LPDMA1_REQUEST_LPUART1_RX (*) + * @arg @ref LL_LPDMA1_REQUEST_LPUART1_TX (*) + * @arg @ref LL_LPDMA1_REQUEST_SAI1_A (*) + * @arg @ref LL_LPDMA1_REQUEST_SAI1_B (*) + * @arg @ref LL_LPDMA1_REQUEST_TIM2_CH1 (*) + * @arg @ref LL_LPDMA1_REQUEST_TIM2_CH2 (*) + * @arg @ref LL_LPDMA1_REQUEST_TIM2_CH3 (*) + * @arg @ref LL_LPDMA1_REQUEST_TIM2_CH4 (*) + * @arg @ref LL_LPDMA1_REQUEST_TIM2_UP (*) + * @arg @ref LL_LPDMA1_REQUEST_TIM16_CH1 (*) + * @arg @ref LL_LPDMA1_REQUEST_TIM16_UP (*) + * @arg @ref LL_LPDMA1_REQUEST_TIM17_CH1 (*) + * @arg @ref LL_LPDMA1_REQUEST_TIM17_UP (*) + * @arg @ref LL_LPDMA1_REQUEST_AES_IN (*) + * @arg @ref LL_LPDMA1_REQUEST_AES_OUT (*) + * @arg @ref LL_LPDMA1_REQUEST_HASH_IN (*) + * @arg @ref LL_LPDMA1_REQUEST_LPTIM1_IC1 (*) + * @arg @ref LL_LPDMA1_REQUEST_LPTIM1_IC2 (*) + * @arg @ref LL_LPDMA1_REQUEST_LPTIM1_UE (*) + * @arg @ref LL_LPDMA1_REQUEST_LPTIM2_IC1 (*) + * @arg @ref LL_LPDMA1_REQUEST_LPTIM2_IC2 (*) + * @arg @ref LL_LPDMA1_REQUEST_LPTIM2_UE (*) + * @arg @ref LL_LPDMA1_REQUEST_XSPI1 (*) * @note (*) Availability depends on devices. */ __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(const DMA_TypeDef *DMAx, uint32_t Channel) @@ -2726,6 +3006,34 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(const DMA_TypeDef *DMAx, uint3 * @arg @ref LL_GPDMA1_TRIGGER_TIM2_TRGO * @arg @ref LL_GPDMA1_TRIGGER_ADC4_AWD1 * @arg @ref LL_GPDMA1_TRIGGER_TIM3_TRGO (*) + * @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE0 (*) + * @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE1 (*) + * @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE2 (*) + * @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE3 (*) + * @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE4 (*) + * @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE5 (*) + * @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE6 (*) + * @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE7 (*) + * @arg @ref LL_LPDMA1_TRIGGER_TAMP_TRG1 (*) + * @arg @ref LL_LPDMA1_TRIGGER_TAMP_TRG2 (*) + * @arg @ref LL_LPDMA1_TRIGGER_TAMP_TRG3 (*) + * @arg @ref LL_LPDMA1_TRIGGER_LPTIM1_CH1 (*) + * @arg @ref LL_LPDMA1_TRIGGER_LPTIM1_CH2 (*) + * @arg @ref LL_LPDMA1_TRIGGER_LPTIM2_CH1 (*) + * @arg @ref LL_LPDMA1_TRIGGER_LPTIM2_CH2 (*) + * @arg @ref LL_LPDMA1_TRIGGER_RTC_ALRA_TRG (*) + * @arg @ref LL_LPDMA1_TRIGGER_RTC_ALRB_TRG (*) + * @arg @ref LL_LPDMA1_TRIGGER_RTC_WUT_TRG (*) + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH0_TCF (*) + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH1_TCF (*) + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH2_TCF (*) + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH3_TCF (*) + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH4_TCF (*) + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH5_TCF (*) + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH6_TCF (*) + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH7_TCF (*) + * @arg @ref LL_LPDMA1_TRIGGER_TIM2_TRGO (*) + * @arg @ref LL_LPDMA1_TRIGGER_ADC4_AWD1 (*) * @retval None. */ __STATIC_INLINE void LL_DMA_SetHWTrigger(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Trigger) @@ -2781,6 +3089,34 @@ __STATIC_INLINE void LL_DMA_SetHWTrigger(const DMA_TypeDef *DMAx, uint32_t Chann * @arg @ref LL_GPDMA1_TRIGGER_TIM2_TRGO * @arg @ref LL_GPDMA1_TRIGGER_ADC4_AWD1 * @arg @ref LL_GPDMA1_TRIGGER_TIM3_TRGO (*) + * @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE0 (*) + * @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE1 (*) + * @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE2 (*) + * @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE3 (*) + * @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE4 (*) + * @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE5 (*) + * @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE6 (*) + * @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE7 (*) + * @arg @ref LL_LPDMA1_TRIGGER_TAMP_TRG1 (*) + * @arg @ref LL_LPDMA1_TRIGGER_TAMP_TRG2 (*) + * @arg @ref LL_LPDMA1_TRIGGER_TAMP_TRG3 (*) + * @arg @ref LL_LPDMA1_TRIGGER_LPTIM1_CH1 (*) + * @arg @ref LL_LPDMA1_TRIGGER_LPTIM1_CH2 (*) + * @arg @ref LL_LPDMA1_TRIGGER_LPTIM2_CH1 (*) + * @arg @ref LL_LPDMA1_TRIGGER_LPTIM2_CH2 (*) + * @arg @ref LL_LPDMA1_TRIGGER_RTC_ALRA_TRG (*) + * @arg @ref LL_LPDMA1_TRIGGER_RTC_ALRB_TRG (*) + * @arg @ref LL_LPDMA1_TRIGGER_RTC_WUT_TRG (*) + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH0_TCF (*) + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH1_TCF (*) + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH2_TCF (*) + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH3_TCF (*) + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH4_TCF (*) + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH5_TCF (*) + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH6_TCF (*) + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH7_TCF (*) + * @arg @ref LL_LPDMA1_TRIGGER_TIM2_TRGO (*) + * @arg @ref LL_LPDMA1_TRIGGER_ADC4_AWD1 (*) */ __STATIC_INLINE uint32_t LL_DMA_GetHWTrigger(const DMA_TypeDef *DMAx, uint32_t Channel) { @@ -3443,6 +3779,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetLinkedListAddrOffset(const DMA_TypeDef *DMAx, DMA_CLLR_LA) >> DMA_CLLR_LA_Pos); } +#if defined(GPDMA1) /** * @brief Get FIFO level. * @rmtoll CSR FIFOL LL_DMA_GetFIFOLevel @@ -3464,6 +3801,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetFIFOLevel(const DMA_TypeDef *DMAx, uint32_t C return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_FIFOL) >> DMA_CSR_FIFOL_Pos); } +#endif /* GPDMA1 */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** @@ -4546,7 +4884,7 @@ void LL_DMA_DisconnectNextLinkNode(LL_DMA_LinkNodeTypeDef *pLinkNode, uint32 * @} */ -#endif /* GPDMA1 */ +#endif /* GPDMA1 || LPDMA1 */ /** * @} diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_exti.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_exti.h index a51c81b5d9..8c43ca0eab 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_exti.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_exti.h @@ -110,6 +110,12 @@ typedef struct #if defined(EXTI_IMR1_IM18) #define LL_EXTI_LINE_18 EXTI_IMR1_IM18 /*!< Extended line 18 */ #endif /* LL_EXTI_LINE_18 */ +#if defined(EXTI_IMR1_IM19) +#define LL_EXTI_LINE_19 EXTI_IMR1_IM19 /*!< Extended line 19 */ +#endif /* LL_EXTI_LINE_19 */ +#if defined(EXTI_IMR1_IM20) +#define LL_EXTI_LINE_20 EXTI_IMR1_IM20 /*!< Extended line 20 */ +#endif /* LL_EXTI_LINE_20 */ #define LL_EXTI_LINE_ALL_0_31 0x007FFFFFU /*!< ALL Extended line */ #if defined(USE_FULL_LL_DRIVER) @@ -120,9 +126,24 @@ typedef struct * @{ */ #define LL_EXTI_CONFIG_PORTA 0U /*!< EXTI PORT A */ +#if !defined (EXTI_EXTICR1_EXTI0) +#define LL_EXTI_CONFIG_PORTB EXTI_EXTICR2_EXTI4_0 /*!< EXTI PORT B */ +#define LL_EXTI_CONFIG_PORTC EXTI_EXTICR2_EXTI4_1 /*!< EXTI PORT C */ +#define LL_EXTI_CONFIG_PORTH (EXTI_EXTICR2_EXTI4_2|EXTI_EXTICR2_EXTI4_1|EXTI_EXTICR2_EXTI4_0) /*!< EXTI PORT H */ +#else /* !defined (EXTI_EXTICR1_EXTI0) */ #define LL_EXTI_CONFIG_PORTB EXTI_EXTICR1_EXTI0_0 /*!< EXTI PORT B */ #define LL_EXTI_CONFIG_PORTC EXTI_EXTICR1_EXTI0_1 /*!< EXTI PORT C */ +#if defined(GPIOD) +#define LL_EXTI_CONFIG_PORTD (EXTI_EXTICR1_EXTI0_1|EXTI_EXTICR1_EXTI0_0) /*!< EXTI PORT D */ +#endif /* GPIOD */ +#if defined(GPIOE) +#define LL_EXTI_CONFIG_PORTE EXTI_EXTICR1_EXTI0_2 /*!< EXTI PORT E */ +#endif /* GPIOE */ +#if defined(GPIOG) +#define LL_EXTI_CONFIG_PORTG (EXTI_EXTICR1_EXTI0_1|EXTI_EXTICR1_EXTI0_1) /*!< EXTI PORT G */ +#endif /* GPIOG */ #define LL_EXTI_CONFIG_PORTH (EXTI_EXTICR1_EXTI0_2|EXTI_EXTICR1_EXTI0_1|EXTI_EXTICR1_EXTI0_0) /*!< EXTI PORT H */ +#endif /* !defined (EXTI_EXTICR1_EXTI0) */ /** * @} */ @@ -1008,7 +1029,11 @@ __STATIC_INLINE void LL_EXTI_ClearRisingFlag_0_31(uint32_t ExtiLine) */ __STATIC_INLINE void LL_EXTI_SetEXTISource(uint32_t Port, uint32_t Line) { +#if defined (EXTI_EXTICR1_EXTI0) MODIFY_REG(EXTI->EXTICR[Line & 0x03U], EXTI_EXTICR1_EXTI0 << (Line >> LL_EXTI_REGISTER_PINPOS_SHFT), Port << (Line >> LL_EXTI_REGISTER_PINPOS_SHFT)); +#else /* defined (EXTI_EXTICR1_EXTI0) */ + MODIFY_REG(EXTI->EXTICR[Line & 0x03U], EXTI_EXTICR2_EXTI4 << (Line >> LL_EXTI_REGISTER_PINPOS_SHFT), Port << (Line >> LL_EXTI_REGISTER_PINPOS_SHFT)); +#endif /* defined (EXTI_EXTICR1_EXTI0) */ } /** @@ -1054,7 +1079,11 @@ __STATIC_INLINE void LL_EXTI_SetEXTISource(uint32_t Port, uint32_t Line) */ __STATIC_INLINE uint32_t LL_EXTI_GetEXTISource(uint32_t Line) { +#if defined (EXTI_EXTICR1_EXTI0) return (uint32_t)(READ_BIT(EXTI->EXTICR[Line & 0x03U], (EXTI_EXTICR1_EXTI0 << (Line >> LL_EXTI_REGISTER_PINPOS_SHFT))) >> (Line >> LL_EXTI_REGISTER_PINPOS_SHFT)); +#else /* defined (EXTI_EXTICR1_EXTI0) */ + return (uint32_t)(READ_BIT(EXTI->EXTICR[Line & 0x03U], (EXTI_EXTICR2_EXTI4 << (Line >> LL_EXTI_REGISTER_PINPOS_SHFT))) >> (Line >> LL_EXTI_REGISTER_PINPOS_SHFT)); +#endif /* defined (EXTI_EXTICR1_EXTI0) */ } /** * @} diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_gpio.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_gpio.h index 04d4907158..b37e6fcf32 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_gpio.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_gpio.h @@ -31,7 +31,7 @@ extern "C" { * @{ */ -#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOH) +#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOG) || defined (GPIOH) /** @defgroup GPIO_LL GPIO * @{ @@ -954,6 +954,70 @@ __STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask) WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask)); } +#if defined (STM32WBA62xx) || defined (STM32WBA63xx) || defined (STM32WBA64xx) || defined (STM32WBA65xx) || defined (STM32WBA6Mxx) +/** + * @brief Enable speed optimization for several pin of dedicated port. + * @note Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding + * datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must + * be kept at reset value. + * @note It must be used only if the I/O supply voltage is below 2.7 V. + * @rmtoll HSLVR HSLVy LL_GPIO_EnableHighSPeedLowVoltage + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval None + */ +__STATIC_INLINE void LL_GPIO_EnableHighSPeedLowVoltage(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + SET_BIT(GPIOx->HSLVR, PinMask); +} + +/** + * @brief Disable speed optimization for several pin of dedicated port. + * @note Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding + * datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must + * be kept at reset value. + * @note It must be used only if the I/O supply voltage is below 2.7 V. + * @rmtoll HSLVR HSLVy LL_GPIO_DisableHighSPeedLowVoltage + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval None + */ +__STATIC_INLINE void LL_GPIO_DisableHighSPeedLowVoltage(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + CLEAR_BIT(GPIOx->HSLVR, PinMask); +} + +#endif /* defined (STM32WBA62xx) || defined (STM32WBA63xx) || defined (STM32WBA64xx) || defined (STM32WBA65xx) || defined (STM32WBA6Mxx) */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** @@ -1073,7 +1137,7 @@ void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct); * @} */ -#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOH) */ +#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOG) || defined (GPIOH) */ /** * @} */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_i2c.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_i2c.h index 6c87e85166..61fc8b43bb 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_i2c.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_i2c.h @@ -31,7 +31,7 @@ extern "C" { * @{ */ -#if defined (I2C1) || defined (I2C3) +#if defined (I2C1) || defined (I2C2) || defined (I2C3) || defined (I2C4) /** @defgroup I2C_LL I2C * @{ @@ -355,9 +355,9 @@ typedef struct * @brief I2C Autonomous Trigger selection * @{ */ -#if defined(I2C1) -#define LL_I2C_TRIG_GRP1 (0x10000000U) /*!< Trigger Group for I2C1 */ -#endif /* I2C1 */ +#if (defined(I2C1) || defined(I2C2) || defined(I2C4)) +#define LL_I2C_TRIG_GRP1 (0x10000000U) /*!< Trigger Group for I2C1, I2C2, I2C4 */ +#endif /* I2C1, I2C2, I2C4 */ #define LL_I2C_TRIG_GRP2 (0x20000000U) /*!< Trigger Group for I2C3 */ #if defined(LL_I2C_TRIG_GRP1) @@ -2598,7 +2598,7 @@ void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct); * @} */ -#endif /* I2C1 || I2C3 */ +#endif /* I2C1 || I2C2 || I2C3 || I2C4 */ /** * @} diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_lptim.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_lptim.h index ee641e53ae..45334f6127 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_lptim.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_lptim.h @@ -69,20 +69,20 @@ static const uint8_t LL_LPTIM_SHIFT_TAB_CCxSEL[] = static const uint8_t LL_LPTIM_SHIFT_TAB_CCxE[] = { - LPTIM_CCMR1_CC1E_Pos, /* CC1E */ - LPTIM_CCMR1_CC2E_Pos /* CC2E */ + (uint8_t)LPTIM_CCMR1_CC1E_Pos, /* CC1E */ + (uint8_t)LPTIM_CCMR1_CC2E_Pos /* CC2E */ }; static const uint8_t LL_LPTIM_OFFSET_TAB_ICx[8][4] = { - {2, 7, 9, 13}, - {3, 5, 6, 8}, - {2, 3, 4, 5}, - {2, 2, 3, 3}, - {2, 2, 2, 2}, - {2, 2, 2, 2}, - {2, 2, 2, 2}, - {2, 2, 2, 2} + {2U, 7U, 9U, 13U}, + {3U, 5U, 6U, 8U}, + {2U, 3u, 4U, 5U}, + {2U, 2U, 3U, 3U}, + {2U, 2U, 2U, 2U}, + {2U, 2U, 2U, 2U}, + {2U, 2U, 2U, 2U}, + {2U, 2U, 2U, 2U} }; @@ -1175,7 +1175,8 @@ __STATIC_INLINE uint32_t LL_LPTIM_IC_GetPrescaler(const LPTIM_TypeDef *LPTIMx, u */ __STATIC_INLINE void LL_LPTIM_CC_SetChannelMode(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t CCMode) { - SET_BIT(LPTIMx->CCMR1, CCMode << LL_LPTIM_SHIFT_TAB_CCxSEL[Channel]); + MODIFY_REG(LPTIMx->CCMR1, LPTIM_CCMR1_CC1SEL << LL_LPTIM_SHIFT_TAB_CCxSEL[Channel], + CCMode << LL_LPTIM_SHIFT_TAB_CCxSEL[Channel]); } /** diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_lpuart.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_lpuart.h index bb1113b020..1a20a9fef6 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_lpuart.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_lpuart.h @@ -56,6 +56,10 @@ static const uint16_t LPUART_PRESCALER_TAB[] = (uint16_t)32, (uint16_t)64, (uint16_t)128, + (uint16_t)256, + (uint16_t)256, + (uint16_t)256, + (uint16_t)256, (uint16_t)256 }; /** diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_pwr.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_pwr.h index f708de97cf..bb1626a472 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_pwr.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_pwr.h @@ -57,7 +57,9 @@ extern "C" { #define LL_PWR_WUSCR_CWUF2 PWR_WUSCR_CWUF2 /*!< Clear Wakeup flag 2 */ #define LL_PWR_WUSCR_CWUF3 PWR_WUSCR_CWUF3 /*!< Clear Wakeup flag 3 */ #define LL_PWR_WUSCR_CWUF4 PWR_WUSCR_CWUF4 /*!< Clear Wakeup flag 4 */ +#if !defined(PWR_STOP3_SUPPORT) #define LL_PWR_WUSCR_CWUF5 PWR_WUSCR_CWUF5 /*!< Clear Wakeup flag 5 */ +#endif /* !defined(PWR_STOP3_SUPPORT) */ #define LL_PWR_WUSCR_CWUF6 PWR_WUSCR_CWUF6 /*!< Clear Wakeup flag 6 */ #define LL_PWR_WUSCR_CWUF7 PWR_WUSCR_CWUF7 /*!< Clear Wakeup flag 7 */ #define LL_PWR_WUSCR_CWUF8 PWR_WUSCR_CWUF8 /*!< Clear Wakeup flag 8 */ @@ -81,7 +83,9 @@ extern "C" { #define LL_PWR_WAKEUP_FLAG2 PWR_WUSR_WUF2 /*!< Wakeup flag 2 */ #define LL_PWR_WAKEUP_FLAG3 PWR_WUSR_WUF3 /*!< Wakeup flag 3 */ #define LL_PWR_WAKEUP_FLAG4 PWR_WUSR_WUF4 /*!< Wakeup flag 4 */ +#if !defined(PWR_STOP3_SUPPORT) #define LL_PWR_WAKEUP_FLAG5 PWR_WUSR_WUF5 /*!< Wakeup flag 5 */ +#endif /* !defined(PWR_STOP3_SUPPORT) */ #define LL_PWR_WAKEUP_FLAG6 PWR_WUSR_WUF6 /*!< Wakeup flag 6 */ #define LL_PWR_WAKEUP_FLAG7 PWR_WUSR_WUF7 /*!< Wakeup flag 7 */ #define LL_PWR_WAKEUP_FLAG8 PWR_WUSR_WUF8 /*!< Wakeup flag 8 */ @@ -94,6 +98,12 @@ extern "C" { */ #define LL_PWR_MODE_STOP0 0U /*!< Stop 0 mode */ #define LL_PWR_MODE_STOP1 PWR_CR1_LPMS_0 /*!< Stop 1 mode */ +#if defined(PWR_STOP2_SUPPORT) +#define LL_PWR_MODE_STOP2 PWR_CR1_LPMS_1 /*!< Stop 2 mode */ +#endif /* defined(PWR_STOP2_SUPPORT) */ +#if defined(PWR_STOP3_SUPPORT) +#define LL_PWR_MODE_STOP3 (PWR_CR1_LPMS_1 | PWR_CR1_LPMS_0) /*!< Stop 3 mode */ +#endif /* defined(PWR_STOP3_SUPPORT) */ #define LL_PWR_MODE_STANDBY PWR_CR1_LPMS_2 /*!< Standby mode */ /** * @} @@ -103,7 +113,21 @@ extern "C" { * @{ */ #define LL_PWR_SRAM1_SB_NO_RETENTION 0U /*!< SRAM1 no retention in Standby mode */ +#if defined(PWR_STOP2_SUPPORT) +#define LL_PWR_SRAM1_SB_PAGE1_RETENTION PWR_CR1_R1RSB1 /*!< SRAM1 page 1 retention in Standby mode */ +#if defined(PWR_STOP3_SUPPORT) +#define LL_PWR_SRAM1_SB_FULL_RETENTION PWR_CR1_R1RSB1 /*!< SRAM1 all pages retention in Standby mode */ +#else +#define LL_PWR_SRAM1_SB_PAGE2_RETENTION PWR_CR1_R1RSB2 /*!< SRAM1 page 2 retention in Standby mode */ +#define LL_PWR_SRAM1_SB_PAGE3_RETENTION PWR_CR1_R1RSB3 /*!< SRAM1 page 3 retention in Standby mode */ +#define LL_PWR_SRAM1_SB_PAGE4_RETENTION PWR_CR1_R1RSB4 /*!< SRAM1 page 4 retention in Standby mode */ +#define LL_PWR_SRAM1_SB_PAGE567_RETENTION PWR_CR1_R1RSB567 /*!< SRAM1 page 5-6-7 retention in Standby mode */ +#define LL_PWR_SRAM1_SB_FULL_RETENTION (PWR_CR1_R1RSB1 | PWR_CR1_R1RSB2 | PWR_CR1_R1RSB3 |\ + PWR_CR1_R1RSB4 | PWR_CR1_R1RSB567) +#endif /* defined(PWR_STOP3_SUPPORT) */ +#else/*!< SRAM1 all pages retention in Standby mode */ #define LL_PWR_SRAM1_SB_FULL_RETENTION PWR_CR1_R1RSB1 /*!< SRAM1 all pages retention in Standby mode */ +#endif /* defined(PWR_STOP2_SUPPORT) */ /** * @} */ @@ -112,11 +136,27 @@ extern "C" { * @{ */ #define LL_PWR_SRAM2_SB_NO_RETENTION 0U /*!< SRAM2 no retention in Standby mode */ +#if !defined(PWR_STOP3_SUPPORT) #define LL_PWR_SRAM2_SB_FULL_RETENTION PWR_CR1_R2RSB1 /*!< SRAM2 all pages retention in Standby mode */ +#else +#define LL_PWR_SRAM2_SB_PAGE1_RETENTION PWR_CR1_R2RSB1 /*!< SRAM2 page1 retention in Standby mode */ +#define LL_PWR_SRAM2_SB_PAGE2_RETENTION PWR_CR1_R2RSB2 /*!< SRAM2 page2 retention in Standby mode */ +#define LL_PWR_SRAM2_SB_FULL_RETENTION (PWR_CR1_R2RSB1 | PWR_CR1_R2RSB2) /*!< SRAM2 all pages retention in Standby mode */ +#endif /* !defined(PWR_STOP3_SUPPORT) */ /** * @} */ +#if defined(PWR_STOP3_SUPPORT) +/** @defgroup PWR_LL_EC_RTC_SB_RETENTION RTC and TAMP retention in Standby mode + * @{ + */ +#define LL_PWR_RTC_SB_NO_RETENTION 0U /*!< RTC and TAMP content not retained in Standby mode */ +#define LL_PWR_RTC_SB_FULL_RETENTION PWR_CR1_RTCRSB /*!< RTC and TAMP content retained in Standby mode */ +/** + * @} + */ + #endif /* defined(PWR_STOP3_SUPPORT) */ /** @defgroup PWR_LL_EC_RADIO_SB_RETENTION PWR RADIO SRAMs and Sleep Clock Retention in Standby Mode * @{ @@ -131,7 +171,18 @@ extern "C" { * @{ */ #define LL_PWR_SRAM1_STOP_NO_RETENTION 0U /*!< SRAM1 no retention in Stop mode */ +#if defined(PWR_STOP2_SUPPORT) && !defined(PWR_STOP3_SUPPORT) +#define LL_PWR_SRAM1_STOP_PAGE1_RETENTION PWR_CR2_SRAM1PDS1 /*!< SRAM1 page1 retention in Stop mode */ +#define LL_PWR_SRAM1_STOP_PAGE2_RETENTION PWR_CR2_SRAM1PDS2 /*!< SRAM1 page2 retention in Stop mode */ +#define LL_PWR_SRAM1_STOP_PAGE3_RETENTION PWR_CR2_SRAM1PDS3 /*!< SRAM1 page3 retention in Stop mode */ +#define LL_PWR_SRAM1_STOP_PAGE4_RETENTION PWR_CR2_SRAM1PDS4 /*!< SRAM1 page4 retention in Stop mode */ +#define LL_PWR_SRAM1_STOP_PAGE567_RETENTION PWR_CR2_SRAM1PDS567 /*!< SRAM1 page4 retention in Stop mode */ +#define LL_PWR_SRAM1_STOP_FULL_RETENTION (PWR_CR2_SRAM1PDS1 | PWR_CR2_SRAM1PDS2 | PWR_CR2_SRAM1PDS3 |\ + PWR_CR2_SRAM1PDS4 | PWR_CR2_SRAM1PDS567) +/*!< SRAM1 all pages retention in Stop mode */ +#else #define LL_PWR_SRAM1_STOP_FULL_RETENTION PWR_CR2_SRAM1PDS1 /*!< SRAM1 all pages retention in Stop mode */ +#endif /* defined(PWR_STOP2_SUPPORT) && !defined(PWR_STOP3_SUPPORT) */ /** * @} */ @@ -140,7 +191,13 @@ extern "C" { * @{ */ #define LL_PWR_SRAM2_STOP_NO_RETENTION 0U /*!< SRAM2 no retention in Stop mode */ +#if defined(PWR_STOP3_SUPPORT) +#define LL_PWR_SRAM2_STOP_PAGE1_RETENTION PWR_CR2_SRAM2PDS1 /*!< SRAM2 page1 retention in Stop mode */ +#define LL_PWR_SRAM2_STOP_PAGE2_RETENTION PWR_CR2_SRAM2PDS2 /*!< SRAM2 page2 retention in Stop mode */ +#define LL_PWR_SRAM2_STOP_FULL_RETENTION (PWR_CR2_SRAM2PDS1 | PWR_CR2_SRAM2PDS2) /*!< SRAM2 all pages retention in Stop mode */ +#else #define LL_PWR_SRAM2_STOP_FULL_RETENTION PWR_CR2_SRAM2PDS1 /*!< SRAM2 all pages retention in Stop mode */ +#endif /* defined(PWR_STOP3_SUPPORT) */ /** * @} */ @@ -154,6 +211,36 @@ extern "C" { * @} */ +#if defined(PWR_STOP2_SUPPORT) +#if defined(USB_OTG_HS) +/** @defgroup PWR_LL_EC_USB_OTG_HS_SRAM_STOP_RETENTION PWR USB_OTG_HS SRAM Retention in Stop Mode + * @{ + */ +#define LL_PWR_USB_OTG_HS_SRAM_STOP_NO_RETENTION 0U /*!< USB_OTG_HS SRAM no retention in Stop mode */ +#define LL_PWR_USB_OTG_HS_SRAM_STOP_FULL_RETENTION PWR_CR2_PRAMPDS /*!< USB_OTG_HS SRAM full retention in Stop mode */ +/** + * @} + */ +#else + /** @defgroup PWR_LL_EC_USB_SRAM_STOP_RETENTION PWR USB SRAM Retention in Stop Mode + * @{ + */ +#define LL_PWR_USB_SRAM_STOP_NO_RETENTION 0U /*!< USB SRAM no retention in Stop mode */ +#define LL_PWR_USB_SRAM_STOP_FULL_RETENTION PWR_CR2_PRAMPDS /*!< USB SRAM full retention in Stop mode */ +/** + * @} + */ +#endif /* defined(USB_OTG_HS) */ + +/** @defgroup PWR_LL_EC_PKARAM_STOP_RETENTION PWR PKA SRAM Retention in Stop Mode + * @{ + */ +#define LL_PWR_PKARAM_STOP_NO_RETENTION 0U /*!< PKA SRAM no retention in Stop mode */ +#define LL_PWR_PKARAM_STOP_FULL_RETENTION PWR_CR2_PKARAMPDS /*!< PKA SRAM full retention in Stop mode */ +/** + * @} + */ +#endif /* defined(PWR_STOP2_SUPPORT) */ /** @defgroup PWR_LL_EC_SMPS_PWM_MODE PWR SMPS PWM mode * @{ */ @@ -203,8 +290,14 @@ extern "C" { /** @defgroup PWR_LL_EC_VOLTAGE_SCALING_RANGE_SELECTION PWR Voltage scaling range selection * @{ */ +#if defined(PWR_STOP3_SUPPORT) +#define LL_PWR_REGU_VOLTAGE_SCALE1 PWR_VOSR_VOS_0 /*!< Voltage scaling range 1 (highest frequency) */ +#define LL_PWR_REGU_VOLTAGE_SCALE1_5 PWR_VOSR_VOS_1 /*!< Voltage scaling range 1.5 (highest frequency, lower power) */ +#define LL_PWR_REGU_VOLTAGE_SCALE2 0U /*!< Voltage scaling range 2 (lowest power) */ +#else #define LL_PWR_REGU_VOLTAGE_SCALE1 PWR_VOSR_VOS /*!< Voltage scaling range 1 (highest frequency) */ #define LL_PWR_REGU_VOLTAGE_SCALE2 0U /*!< Voltage scaling range 2 (lowest power) */ +#endif /* defined(PWR_STOP3_SUPPORT) */ /** * @} */ @@ -219,8 +312,10 @@ extern "C" { #define LL_PWR_PVDLEVEL_4 PWR_SVMCR_PVDLS_2 /*!< Voltage threshold detected by PVD 2.6 V */ #define LL_PWR_PVDLEVEL_5 (PWR_SVMCR_PVDLS_0 | PWR_SVMCR_PVDLS_2) /*!< Voltage threshold detected by PVD 2.8 V */ #define LL_PWR_PVDLEVEL_6 (PWR_SVMCR_PVDLS_1 | PWR_SVMCR_PVDLS_2) /*!< Voltage threshold detected by PVD 2.9 V */ +#if !defined(PWR_STOP3_SUPPORT) #define LL_PWR_PVDLEVEL_7 PWR_SVMCR_PVDLS /*!< External input analog voltage on PVD_IN pin, compared to internal VREFINT level */ +#endif /* !defined(PWR_STOP3_SUPPORT) */ /** * @} */ @@ -232,7 +327,9 @@ extern "C" { #define LL_PWR_WAKEUP_PIN2 PWR_WUCR1_WUPEN2 /*!< Wakeup pin 2 enable */ #define LL_PWR_WAKEUP_PIN3 PWR_WUCR1_WUPEN3 /*!< Wakeup pin 3 enable */ #define LL_PWR_WAKEUP_PIN4 PWR_WUCR1_WUPEN4 /*!< Wakeup pin 4 enable */ +#if !defined(PWR_STOP3_SUPPORT) #define LL_PWR_WAKEUP_PIN5 PWR_WUCR1_WUPEN5 /*!< Wakeup pin 5 enable */ +#endif /* !defined(PWR_STOP3_SUPPORT)*/ #define LL_PWR_WAKEUP_PIN6 PWR_WUCR1_WUPEN6 /*!< Wakeup pin 6 enable */ #define LL_PWR_WAKEUP_PIN7 PWR_WUCR1_WUPEN7 /*!< Wakeup pin 7 enable */ #define LL_PWR_WAKEUP_PIN8 PWR_WUCR1_WUPEN8 /*!< Wakeup pin 8 enable */ @@ -257,6 +354,11 @@ extern "C" { #define LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTA (uint32_t)(&(PWR->IORETENRA)) /*!< GPIO port A */ #define LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTB (uint32_t)(&(PWR->IORETENRB)) /*!< GPIO port B */ #define LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTC (uint32_t)(&(PWR->IORETENRC)) /*!< GPIO port C */ +#if defined(PWR_STOP2_SUPPORT) +#define LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTD (uint32_t)(&(PWR->IORETENRD)) /*!< GPIO port D */ +#define LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTE (uint32_t)(&(PWR->IORETENRE)) /*!< GPIO port E */ +#define LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTG (uint32_t)(&(PWR->IORETENRG)) /*!< GPIO port G */ +#endif /* defined(PWR_STOP2_SUPPORT) */ #define LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTH (uint32_t)(&(PWR->IORETENRH)) /*!< GPIO port H */ /** * @} @@ -268,6 +370,11 @@ extern "C" { #define LL_PWR_GPIO_STATE_RETENTION_STATUS_PORTA (uint32_t)(&(PWR->IORETRA)) /*!< GPIO port A */ #define LL_PWR_GPIO_STATE_RETENTION_STATUS_PORTB (uint32_t)(&(PWR->IORETRB)) /*!< GPIO port B */ #define LL_PWR_GPIO_STATE_RETENTION_STATUS_PORTC (uint32_t)(&(PWR->IORETRC)) /*!< GPIO port C */ +#if defined(PWR_STOP2_SUPPORT) +#define LL_PWR_GPIO_STATE_RETENTION_STATUS_PORTD (uint32_t)(&(PWR->IORETRD)) /*!< GPIO port D */ +#define LL_PWR_GPIO_STATE_RETENTION_STATUS_PORTE (uint32_t)(&(PWR->IORETRE)) /*!< GPIO port E */ +#define LL_PWR_GPIO_STATE_RETENTION_STATUS_PORTG (uint32_t)(&(PWR->IORETRG)) /*!< GPIO port G */ +#endif /* defined(PWR_STOP2_SUPPORT) */ #define LL_PWR_GPIO_STATE_RETENTION_STATUS_PORTH (uint32_t)(&(PWR->IORETRH)) /*!< GPIO port H */ /** * @} @@ -307,8 +414,10 @@ extern "C" { #define LL_PWR_WAKEUP_PIN3_SEC PWR_SECCFGR_WUP3SEC /*!< Wake up pin 3 secure mode */ #define LL_PWR_WAKEUP_PIN4_NSEC 0U /*!< Wake up pin 4 nsecure mode */ #define LL_PWR_WAKEUP_PIN4_SEC PWR_SECCFGR_WUP4SEC /*!< Wake up pin 4 secure mode */ +#if !defined(PWR_STOP3_SUPPORT) #define LL_PWR_WAKEUP_PIN5_NSEC 0U /*!< Wake up pin 5 nsecure mode */ #define LL_PWR_WAKEUP_PIN5_SEC PWR_SECCFGR_WUP5SEC /*!< Wake up pin 5 secure mode */ +#endif /* !defined(PWR_STOP3_SUPPORT) */ #define LL_PWR_WAKEUP_PIN6_NSEC 0U /*!< Wake up pin 6 nsecure mode */ #define LL_PWR_WAKEUP_PIN6_SEC PWR_SECCFGR_WUP6SEC /*!< Wake up pin 6 secure mode */ #define LL_PWR_WAKEUP_PIN7_NSEC 0U /*!< Wake up pin 7 nsecure mode */ @@ -378,6 +487,12 @@ extern "C" { * @param Mode This parameter can be one of the following values: * @arg @ref LL_PWR_MODE_STOP0 * @arg @ref LL_PWR_MODE_STOP1 +#if defined(PWR_STOP2_SUPPORT) + * @arg @ref LL_PWR_MODE_STOP2 +#endif +#if defined(PWR_STOP3_SUPPORT) + * @arg @ref LL_PWR_MODE_STOP3 +#endif * @arg @ref LL_PWR_MODE_STANDBY * @retval None */ @@ -392,6 +507,12 @@ __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t Mode) * @retval Returned value can be one of the following values: * @arg @ref LL_PWR_MODE_STOP0 * @arg @ref LL_PWR_MODE_STOP1 +#if defined(PWR_STOP2_SUPPORT) + * @arg @ref LL_PWR_MODE_STOP2 +#endif +#if defined(PWR_STOP3_SUPPORT) + * @arg @ref LL_PWR_MODE_STOP3 +#endif * @arg @ref LL_PWR_MODE_STANDBY */ __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void) @@ -402,52 +523,146 @@ __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void) /** * @brief Set the SRAM2 page(s) retention in Standby mode. * @rmtoll CR1 R2RSB1 LL_PWR_SetSRAM2SBRetention +#if defined(PWR_STOP3_SUPPORT) + * @rmtoll CR1 R2RSB2 LL_PWR_SetSRAM2SBRetention +#endif * @param SRAM2PageRetention This parameter can be one of the following values: * @arg @ref LL_PWR_SRAM2_SB_NO_RETENTION +#if defined(PWR_STOP3_SUPPORT) + * @arg @ref LL_PWR_SRAM2_SB_PAGE1_RETENTION + * @arg @ref LL_PWR_SRAM2_SB_PAGE2_RETENTION +#endif * @arg @ref LL_PWR_SRAM2_SB_FULL_RETENTION * @retval None */ __STATIC_INLINE void LL_PWR_SetSRAM2SBRetention(uint32_t SRAM2PageRetention) { +#if defined(PWR_STOP3_SUPPORT) + MODIFY_REG(PWR->CR1, (PWR_CR1_R2RSB1 | PWR_CR1_R2RSB2), SRAM2PageRetention); +#else MODIFY_REG(PWR->CR1, PWR_CR1_R2RSB1, SRAM2PageRetention); +#endif /* PWR_STOP3_SUPPORT */ } /** * @brief Get the SRAM2 page(s) retention in Standby mode. * @rmtoll CR1 R2RSB1 LL_PWR_GetSRAM2SBRetention +#if defined(PWR_STOP3_SUPPORT) + * @rmtoll CR1 R2RSB2 LL_PWR_SetSRAM2SBRetention +#endif * @retval Returned value can be one of the following values: * @arg @ref LL_PWR_SRAM2_SB_NO_RETENTION +#if defined(PWR_STOP3_SUPPORT) + * @arg @ref LL_PWR_SRAM2_SB_PAGE1_RETENTION + * @arg @ref LL_PWR_SRAM2_SB_PAGE2_RETENTION +#endif * @arg @ref LL_PWR_SRAM2_SB_FULL_RETENTION */ __STATIC_INLINE uint32_t LL_PWR_GetSRAM2SBRetention(void) { +#if defined(PWR_STOP3_SUPPORT) + return (READ_BIT(PWR->CR1, (PWR_CR1_R2RSB1 | PWR_CR1_R2RSB2))); +#else return (READ_BIT(PWR->CR1, PWR_CR1_R2RSB1)); +#endif /* PWR_STOP3_SUPPORT */ } /** * @brief Set the SRAM1 page(s) retention in Standby mode. * @rmtoll CR1 R1RSB1 LL_PWR_SetSRAM1SBRetention +#if defined(PWR_STOP2_SUPPORT) && !defined(PWR_STOP3_SUPPORT) + * @rmtoll CR1 R1RSB2 LL_PWR_SetSRAM1SBRetention + * @rmtoll CR1 R1RSB3 LL_PWR_SetSRAM1SBRetention + * @rmtoll CR1 R1RSB4 LL_PWR_SetSRAM1SBRetention + * @rmtoll CR1 R1RSB5 LL_PWR_SetSRAM1SBRetention + * @rmtoll CR1 R1RSB6 LL_PWR_SetSRAM1SBRetention + * @rmtoll CR1 R1RSB7 LL_PWR_SetSRAM1SBRetention +#endif * @param SRAM1PageRetention This parameter can be one of the following values: * @arg @ref LL_PWR_SRAM1_SB_NO_RETENTION +#if defined(PWR_STOP2_SUPPORT) + @arg @ref LL_PWR_SRAM1_SB_PAGE1_RETENTION +#if !defined(PWR_STOP3_SUPPORT) + @arg @ref LL_PWR_SRAM1_SB_PAGE2_RETENTION + @arg @ref LL_PWR_SRAM1_SB_PAGE3_RETENTION + @arg @ref LL_PWR_SRAM1_SB_PAGE4_RETENTION + @arg @ref LL_PWR_SRAM1_SB_PAGE567_RETENTION +#endif +#endif * @arg @ref LL_PWR_SRAM1_SB_FULL_RETENTION * @retval None */ __STATIC_INLINE void LL_PWR_SetSRAM1SBRetention(uint32_t SRAM1PageRetention) { +#if defined(PWR_STOP2_SUPPORT) && !defined(PWR_STOP3_SUPPORT) + MODIFY_REG(PWR->CR1, (PWR_CR1_R1RSB1 |PWR_CR1_R1RSB2 |PWR_CR1_R1RSB3 |\ + PWR_CR1_R1RSB4 | PWR_CR1_R1RSB567), SRAM1PageRetention); +#else MODIFY_REG(PWR->CR1, PWR_CR1_R1RSB1, SRAM1PageRetention); +#endif /* defined(PWR_STOP2_SUPPORT) && !defined(PWR_STOP3_SUPPORT) */ } /** * @brief Get the SRAM1 page(s) retention in Standby mode. * @rmtoll CR1 R1RSB1 LL_PWR_GetSRAM1SBRetention +#if defined(PWR_STOP2_SUPPORT) && !defined(PWR_STOP3_SUPPORT) + * @rmtoll CR1 R1RSB2 LL_PWR_GetSRAM1SBRetention + * @rmtoll CR1 R1RSB3 LL_PWR_GetSRAM1SBRetention + * @rmtoll CR1 R1RSB4 LL_PWR_GetSRAM1SBRetention + * @rmtoll CR1 R1RSB5 LL_PWR_GetSRAM1SBRetention + * @rmtoll CR1 R1RSB6 LL_PWR_GetSRAM1SBRetention + * @rmtoll CR1 R1RSB7 LL_PWR_GetSRAM1SBRetention +#endif * @retval Returned value can be one of the following values: * @arg @ref LL_PWR_SRAM1_SB_NO_RETENTION +#if defined(PWR_STOP2_SUPPORT) + @arg @ref LL_PWR_SRAM1_SB_PAGE1_RETENTION +#if !defined(PWR_STOP3_SUPPORT) + @arg @ref LL_PWR_SRAM1_SB_PAGE2_RETENTION + @arg @ref LL_PWR_SRAM1_SB_PAGE3_RETENTION + @arg @ref LL_PWR_SRAM1_SB_PAGE4_RETENTION + @arg @ref LL_PWR_SRAM1_SB_PAGE567_RETENTION +#endif +#endif +#if !defined(PWR_STOP3_SUPPORT) * @arg @ref LL_PWR_SRAM1_SB_FULL_RETENTION +#endif */ __STATIC_INLINE uint32_t LL_PWR_GetSRAM1SBRetention(void) { +#if defined(PWR_STOP2_SUPPORT) && !defined(PWR_STOP3_SUPPORT) + return (READ_BIT(PWR->CR1, (PWR_CR1_R1RSB1 |PWR_CR1_R1RSB2 |PWR_CR1_R1RSB3 |\ + PWR_CR1_R1RSB4 | PWR_CR1_R1RSB567))); +#else return (READ_BIT(PWR->CR1, PWR_CR1_R1RSB1)); +#endif /* defined(PWR_STOP2_SUPPORT) && !defined(PWR_STOP3_SUPPORT) */ +} +#if defined(PWR_STOP3_SUPPORT) +/** + * @brief Set the RTC/TAMP retention in Standby mode. + * @rmtoll CR1 RTCRSB LL_PWR_SetRTCSBRetention + * @param RadioRetention This parameter can be one of the following values: + * @arg @ref LL_PWR_RTC_SB_NO_RETENTION + * @arg @ref LL_PWR_RTC_SB_FULL_RETENTION + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetRTCSBRetention(uint32_t RtcRetention) +{ + MODIFY_REG(PWR->CR1, PWR_CR1_RTCRSB, RtcRetention); +} + +/** + * @brief Get the Radio retention in Standby mode. + * @rmtoll CR1 RTCRSB LL_PWR_GetRTCSBRetention + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_RTC_SB_NO_RETENTION + * @arg @ref LL_PWR_RTC_SB_FULL_RETENTION + */ +__STATIC_INLINE uint32_t LL_PWR_GetRTCSBRetention(void) +{ + return (READ_BIT(PWR->CR1, PWR_CR1_RTCRSB)); } +#endif /* defined(PWR_STOP3_SUPPORT) */ /** * @brief Set the Radio retention in Standby mode. @@ -508,39 +723,95 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledUltraLowPowerMode(void) /** * @brief Set the SRAM1 page(s) retention in Stop mode. * @rmtoll CR2 SRAM1PDS1 LL_PWR_SetSRAM1StopRetention +#if defined(PWR_STOP2_SUPPORT) && !defined(PWR_STOP3_SUPPORT) + * @rmtoll CR2 SRAM1PDS2 LL_PWR_SetSRAM1StopRetention + * @rmtoll CR2 SRAM1PDS3 LL_PWR_SetSRAM1StopRetention + * @rmtoll CR2 SRAM1PDS4 LL_PWR_SetSRAM1StopRetention + * @rmtoll CR2 SRAM1PDS567 LL_PWR_SetSRAM1StopRetention +#endif * @param SRAM1PageRetention This parameter can be one of the following values: * @arg @ref LL_PWR_SRAM1_STOP_NO_RETENTION +#if defined(PWR_STOP2_SUPPORT) + @arg @ref LL_PWR_SRAM1_STOP_PAGE1_RETENTION +#if !defined(PWR_STOP3_SUPPORT) + @arg @ref LL_PWR_SRAM1_STOP_PAGE2_RETENTION + @arg @ref LL_PWR_SRAM1_STOP_PAGE3_RETENTION + @arg @ref LL_PWR_SRAM1_STOP_PAGE4_RETENTION + @arg @ref LL_PWR_SRAM1_STOP_PAGE567_RETENTION +#endif +#endif * @arg @ref LL_PWR_SRAM1_STOP_FULL_RETENTION * @retval None */ __STATIC_INLINE void LL_PWR_SetSRAM1StopRetention(uint32_t SRAM1PageRetention) { +#if defined(PWR_STOP2_SUPPORT) && !defined(PWR_STOP3_SUPPORT) + MODIFY_REG(PWR->CR2, (PWR_CR2_SRAM1PDS1 | PWR_CR2_SRAM1PDS2 |\ + PWR_CR2_SRAM1PDS3 | PWR_CR2_SRAM1PDS4 | PWR_CR2_SRAM1PDS567), + ((~SRAM1PageRetention) & (PWR_CR2_SRAM1PDS1 | PWR_CR2_SRAM1PDS2 |\ + PWR_CR2_SRAM1PDS3 | PWR_CR2_SRAM1PDS4 | PWR_CR2_SRAM1PDS567))); +#else MODIFY_REG(PWR->CR2, PWR_CR2_SRAM1PDS1, ((~SRAM1PageRetention) & PWR_CR2_SRAM1PDS1)); +#endif /* defined(PWR_STOP2_SUPPORT) && !defined(PWR_STOP3_SUPPORT) */ } /** * @brief Get the SRAM1 page(s) retention in Stop mode. * @rmtoll CR2 SRAM1PDS1 LL_PWR_GetSRAM1StopRetention +#if defined(PWR_STOP2_SUPPORT) && !defined(PWR_STOP3_SUPPORT) + * @rmtoll CR2 SRAM1PDS2 LL_PWR_GetSRAM1StopRetention + * @rmtoll CR2 SRAM1PDS3 LL_PWR_GetSRAM1StopRetention + * @rmtoll CR2 SRAM1PDS4 LL_PWR_GetSRAM1StopRetention + * @rmtoll CR2 SRAM1PDS567 LL_PWR_GetSRAM1StopRetention +#endif * @retval Returned value can be one of the following values: * @arg @ref LL_PWR_SRAM1_STOP_NO_RETENTION +#if defined(PWR_STOP2_SUPPORT) + @arg @ref LL_PWR_SRAM1_STOP_PAGE1_RETENTION +#if !defined(PWR_STOP3_SUPPORT) + @arg @ref LL_PWR_SRAM1_STOP_PAGE2_RETENTION + @arg @ref LL_PWR_SRAM1_STOP_PAGE3_RETENTION + @arg @ref LL_PWR_SRAM1_STOP_PAGE4_RETENTION + @arg @ref LL_PWR_SRAM1_STOP_PAGE567_RETENTION +#endif +#endif * @arg @ref LL_PWR_SRAM1_STOP_FULL_RETENTION */ __STATIC_INLINE uint32_t LL_PWR_GetSRAM1StopRetention(void) { +#if defined(PWR_STOP2_SUPPORT) && !defined(PWR_STOP3_SUPPORT) + return ((~(READ_BIT(PWR->CR2, (PWR_CR2_SRAM1PDS1 | PWR_CR2_SRAM1PDS2 |\ + PWR_CR2_SRAM1PDS3 | PWR_CR2_SRAM1PDS4 | PWR_CR2_SRAM1PDS567)))) &\ + (PWR_CR2_SRAM1PDS1 | PWR_CR2_SRAM1PDS2 | PWR_CR2_SRAM1PDS3 |\ + PWR_CR2_SRAM1PDS4 | PWR_CR2_SRAM1PDS567)); +#else return ((~(READ_BIT(PWR->CR2, PWR_CR2_SRAM1PDS1))) & PWR_CR2_SRAM1PDS1); +#endif /* defined(PWR_STOP2_SUPPORT) && !defined(PWR_STOP3_SUPPORT) */ } /** * @brief Set the SRAM2 page(s) retention in Stop mode. * @rmtoll CR2 SRAM2PDS1 LL_PWR_SetSRAM2StopRetention +#if defined(PWR_STOP3_SUPPORT) + * @rmtoll CR2 SRAM2PDS2 LL_PWR_SetSRAM2StopRetention +#endif * @param SRAM2PageRetention This parameter can be one of the following values: * @arg @ref LL_PWR_SRAM2_STOP_NO_RETENTION +#if defined(PWR_STOP3_SUPPORT) + * @arg @ref LL_PWR_SRAM2_STOP_PAGE1_RETENTION + * @arg @ref LL_PWR_SRAM2_STOP_PAGE2_RETENTION +#endif * @arg @ref LL_PWR_SRAM2_STOP_FULL_RETENTION * @retval None */ __STATIC_INLINE void LL_PWR_SetSRAM2StopRetention(uint32_t SRAM2PageRetention) { +#if defined(PWR_STOP3_SUPPORT) + MODIFY_REG(PWR->CR2, (PWR_CR2_SRAM2PDS1 | PWR_CR2_SRAM2PDS2), + ((~SRAM2PageRetention) & (PWR_CR2_SRAM2PDS1 | PWR_CR2_SRAM2PDS2))); +#else MODIFY_REG(PWR->CR2, PWR_CR2_SRAM2PDS1, ((~SRAM2PageRetention) & PWR_CR2_SRAM2PDS1)); +#endif /* defined(PWR_STOP3_SUPPORT) */ } /** @@ -548,13 +819,22 @@ __STATIC_INLINE void LL_PWR_SetSRAM2StopRetention(uint32_t SRAM2PageRetention) * @rmtoll CR2 SRAM2PDS1 LL_PWR_GetSRAM2StopRetention * @retval Returned value can be one of the following values: * @arg @ref LL_PWR_SRAM2_STOP_NO_RETENTION +#if defined(PWR_STOP3_SUPPORT) + * @arg @ref LL_PWR_SRAM2_STOP_PAGE1_RETENTION + * @arg @ref LL_PWR_SRAM2_STOP_PAGE2_RETENTION +#endif * @arg @ref LL_PWR_SRAM2_STOP_FULL_RETENTION */ __STATIC_INLINE uint32_t LL_PWR_GetSRAM2StopRetention(void) { +#if defined(PWR_STOP3_SUPPORT) + return ((~(READ_BIT(PWR->CR2, (PWR_CR2_SRAM2PDS1 | PWR_CR2_SRAM2PDS2)))) & (PWR_CR2_SRAM2PDS1 | PWR_CR2_SRAM2PDS2)); +#else return ((~(READ_BIT(PWR->CR2, PWR_CR2_SRAM2PDS1))) & PWR_CR2_SRAM2PDS1); +#endif /* defined(PWR_STOP3_SUPPORT) */ } +#if defined (PWR_CR2_ICRAMPDS) /** * @brief Set the ICACHE SRAM page(s) retention in Stop mode. * @rmtoll CR2 ICRAMPDS LL_PWR_SetICacheRAMStopRetention @@ -583,6 +863,89 @@ __STATIC_INLINE uint32_t LL_PWR_GetICacheRAMStopRetention(void) { return ((~(READ_BIT(PWR->CR2, PWR_CR2_ICRAMPDS))) & PWR_CR2_ICRAMPDS); } +#endif /* PWR_CR2_ICRAMPDS */ + +#if defined(PWR_STOP2_SUPPORT) +#if defined(USB_OTG_HS) +/** + * @brief Set the USB_OTG_HS SRAM retention in Stop mode. + * @rmtoll CR2 PRAMPDS LL_PWR_SetOTGHSRAMStopRetention + * @param OTGHSRAMRetention This parameter can be one of the following values: + * @arg @ref LL_PWR_USB_OTG_HS_SRAM_STOP_NO_RETENTION + * @arg @ref LL_PWR_USB_OTG_HS_SRAM_STOP_FULL_RETENTION + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetOTGHSRAMStopRetention(uint32_t OTGHSRAMRetention) +{ + MODIFY_REG(PWR->CR2, PWR_CR2_PRAMPDS, ((~OTGHSRAMRetention) & PWR_CR2_PRAMPDS)); +} + +/** + * @brief Get the USB_OTG_HS SRAM retention in Stop mode. + * @rmtoll CR2 PRAMPDS LL_PWR_GetOTGHSRAMStopRetention + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_USB_OTG_HS_SRAM_STOP_NO_RETENTION + * @arg @ref LL_PWR_USB_OTG_HS_SRAM_STOP_FULL_RETENTION + */ +__STATIC_INLINE uint32_t LL_PWR_GetOTGHSRAMStopRetention(void) +{ + return ((~(READ_BIT(PWR->CR2, PWR_CR2_PRAMPDS))) & PWR_CR2_PRAMPDS); +} +#else + +#if defined(PWR_CR2_PRAMPDS) +/** + * @brief Set the USB SRAM retention in Stop mode. + * @rmtoll CR2 PRAMPDS LL_PWR_SetUSBRAMStopRetention + * @param USBRAMRetention This parameter can be one of the following values: + * @arg @ref LL_PWR_USB_SRAM_STOP_NO_RETENTION + * @arg @ref LL_PWR_USB_SRAM_STOP_FULL_RETENTION + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetUSBRAMStopRetention(uint32_t USBRAMRetention) +{ + MODIFY_REG(PWR->CR2, PWR_CR2_PRAMPDS, ((~USBRAMRetention) & PWR_CR2_PRAMPDS)); +} + +/** + * @brief Get the USB SRAM retention in Stop mode. + * @rmtoll CR2 PRAMPDS LL_PWR_GetUSBRAMStopRetention + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_USB_SRAM_STOP_NO_RETENTION + * @arg @ref LL_PWR_USB_SRAM_STOP_FULL_RETENTION + */ +__STATIC_INLINE uint32_t LL_PWR_GetUSBRAMStopRetention(void) +{ + return ((~(READ_BIT(PWR->CR2, PWR_CR2_PRAMPDS))) & PWR_CR2_PRAMPDS); +} +#endif /* defined(PWR_CR2_PRAMPDS) */ +#endif /* defined(USB_OTG_HS) */ + +/** + * @brief Set the PKA SRAM retention in Stop mode. + * @rmtoll CR2 PKARAMPDS LL_PWR_SetPKARAMStopRetention + * @param PKASRAMRetention This parameter can be one of the following values: + * @arg @ref LL_PWR_PKARAM_STOP_NO_RETENTION + * @arg @ref LL_PWR_PKARAM_STOP_FULL_RETENTION + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetPKARAMStopRetention(uint32_t PKASRAMRetention) +{ + MODIFY_REG(PWR->CR2, PWR_CR2_PKARAMPDS, ((~PKASRAMRetention) & PWR_CR2_PKARAMPDS)); +} + +/** + * @brief Get the PKA SRAM retention in Stop mode. + * @rmtoll CR2 PKARAMPDS LL_PWR_GetPKARAMStopRetention + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_PKARAM_STOP_NO_RETENTION + * @arg @ref LL_PWR_PKARAM_STOP_FULL_RETENTION + */ +__STATIC_INLINE uint32_t LL_PWR_GetPKARAMStopRetention(void) +{ + return ((~(READ_BIT(PWR->CR2, PWR_CR2_PKARAMPDS))) & PWR_CR2_PKARAMPDS); +} +#endif /* defined(PWR_STOP2_SUPPORT) */ /** * @brief Enable the flash memory fast wakeup from Stop mode (Stop 0, 1). @@ -708,6 +1071,9 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledFastSoftStart(void) * @rmtoll VOSR VOS LL_PWR_SetRegulVoltageScaling * @param VoltageScaling This parameter can be one of the following values: * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 +#if defined(PWR_STOP3_SUPPORT) + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1_5 +#endif * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 * @retval None */ @@ -721,12 +1087,222 @@ __STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling) * @rmtoll VOSR VOS LL_PWR_GetRegulVoltageScaling * @retval Returned value can be one of the following values: * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 +#if defined(PWR_STOP3_SUPPORT) + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1_5 +#endif * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 */ __STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void) { return (uint32_t)(READ_BIT(PWR->VOSR, PWR_VOSR_VOS)); } +#if defined(PWR_STOP2_SUPPORT) +#if defined(USB_OTG_HS) +/** + * @brief Set the clocked delay between VDD11USBDIS and VDD11USBRDY. + * @rmtoll VOSR VDD11USBSWDLY LL_PWR_SetVdd11UsbSwitchDelay + * @param Delay : Specifies the delay in system clock cycles. + * This parameter can be a value between 0 to 1023. + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetVdd11UsbSwitchDelay(uint32_t Delay) +{ + MODIFY_REG(PWR->VOSR, PWR_VOSR_VDD11USBSWDLY, (Delay << PWR_VOSR_VDD11USBSWDLY_Pos)); +} + +/** + * @brief Get the clocked delay between VDD11USBDIS and VDD11USBRDY. + * @rmtoll VOSR VDD11USBSWDLY LL_PWR_GetVdd11UsbSwitchDelay + * @retval Returned the delay in system clock cycles. + */ +__STATIC_INLINE uint32_t LL_PWR_GetVdd11UsbSwitchDelay(void) +{ + return (uint32_t)((READ_BIT(PWR->VOSR, PWR_VOSR_VDD11USBSWDLY) >> PWR_VOSR_VDD11USBSWDLY_Pos)); +} + +/** + * @brief Enable the VDD11 USB. + * @rmtoll VOSR VDD11USBDIS LL_PWR_EnableVdd11USB + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableVdd11USB(void) +{ + CLEAR_BIT(PWR->VOSR, PWR_VOSR_VDD11USBDIS); +} + +/** + * @brief Disable the VDD11 USB. + * @rmtoll VOSR VDD11USBDIS LL_PWR_DisableVdd11USB + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableVdd11USB(void) +{ + SET_BIT(PWR->VOSR, PWR_VOSR_VDD11USBDIS); +} + +/** + * @brief Check if the VDD11 USB is enabled. + * @rmtoll VOSR VDD11USBDIS LL_PWR_IsEnabledVdd11USB + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledVdd11USB(void) +{ + return ((READ_BIT(PWR->VOSR, PWR_VOSR_VDD11USBDIS) == (PWR_VOSR_VDD11USBDIS)) ? 0UL : 1UL); +} + +/** + * @brief Enable the USB booster. + * @rmtoll VOSR USBBOOSTEN LL_PWR_EnableUSBBooster + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableUSBBooster(void) +{ + SET_BIT(PWR->VOSR, PWR_VOSR_USBBOOSTEN); +} + +/** + * @brief Disable the USB booster. + * @rmtoll VOSR USBBOOSTEN LL_PWR_DisableUSBBooster + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableUSBBooster(void) +{ + CLEAR_BIT(PWR->VOSR, PWR_VOSR_USBBOOSTEN); +} + +/** + * @brief Check if the USB booster is enabled. + * @rmtoll VOSR USBBOOSTEN LL_PWR_IsEnabledUSBBooster + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBBooster(void) +{ + return ((READ_BIT(PWR->VOSR, PWR_VOSR_USBBOOSTEN) == (PWR_VOSR_USBBOOSTEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable the USB OTG_HS power. + * @rmtoll VOSR USBPWREN LL_PWR_EnableUSBPWR + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableUSBPWR(void) +{ + SET_BIT(PWR->VOSR, PWR_VOSR_USBPWREN); +} + +/** + * @brief Disable the USB OTG_HS power. + * @rmtoll VOSR USBPWREN LL_PWR_DisableUSBPWR + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableUSBPWR(void) +{ + CLEAR_BIT(PWR->VOSR, PWR_VOSR_USBPWREN); +} + +/** + * @brief Check if the USB OTG_HS power is enabled. + * @rmtoll VOSR USBPWREN LL_PWR_IsEnabledUSBPWR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBPWR(void) +{ + return ((READ_BIT(PWR->VOSR, PWR_VOSR_USBPWREN) == (PWR_VOSR_USBPWREN)) ? 1UL : 0UL); +} + +/** + * @brief Enable the VDDUSB supply. + * @rmtoll VOSR USV LL_PWR_EnableVddUSB + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableVddUSB(void) +{ + SET_BIT(PWR->SVMCR, PWR_SVMCR_USV); +} + +/** + * @brief Disable the VDDUSB supply. + * @rmtoll VOSR USV LL_PWR_DisableVddUSB + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableVddUSB(void) +{ + CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_USV); +} + +/** + * @brief Check if the VDDUSB supply is enabled. + * @rmtoll VOSR USV LL_PWR_IsEnabledVddUSB + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddUSB(void) +{ + return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_USV) == (PWR_SVMCR_USV)) ? 1UL : 0UL); +} +#elif defined(PWR_STOP3_SUPPORT) && defined(PWR_SVMCR_USV) +/** + * @brief Enable the VDDUSB supply. + * @rmtoll VOSR USV LL_PWR_EnableVddUSB + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableVddUSB(void) +{ + SET_BIT(PWR->SVMCR, PWR_SVMCR_USV); +} + +/** + * @brief Disable the VDDUSB supply. + * @rmtoll VOSR USV LL_PWR_DisableVddUSB + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableVddUSB(void) +{ + CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_USV); +} + +/** + * @brief Check if the VDDUSB supply is enabled. + * @rmtoll VOSR USV LL_PWR_IsEnabledVddUSB + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddUSB(void) +{ + return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_USV) == (PWR_SVMCR_USV)) ? 1UL : 0UL); +} +#endif /* defined(PWR_STOP3_SUPPORT) && defined(PWR_SVMCR_USV) */ + +#if defined(PWR_SVMCR_IO2SV) +/** + * @brief Enable the independent I/Os supply. + * @rmtoll SVMCR IO2SV LL_PWR_EnableVddIO2 + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableVddIO2(void) +{ + SET_BIT(PWR->SVMCR, PWR_SVMCR_IO2SV); +} + +/** + * @brief Disable the independent I/Os supply. + * @rmtoll SVMCR IO2SV LL_PWR_DisableVddIO2 + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableVddIO2(void) +{ + CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_IO2SV); +} + +/** + * @brief Check if the independent I/Os supply is enabled. + * @rmtoll SVMCR IO2SV LL_PWR_IsEnabledVddIO2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO2(void) +{ + return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_IO2SV) == (PWR_SVMCR_IO2SV)) ? 1UL : 0UL); +} +#endif /* defined(PWR_SVMCR_IO2SV) */ +#endif /* defined(PWR_STOP2_SUPPORT) */ /** * @brief Set the Power voltage detector level. @@ -739,7 +1315,9 @@ __STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void) * @arg @ref LL_PWR_PVDLEVEL_4 * @arg @ref LL_PWR_PVDLEVEL_5 * @arg @ref LL_PWR_PVDLEVEL_6 +#if !defined(PWR_STOP3_SUPPORT) * @arg @ref LL_PWR_PVDLEVEL_7 +#endif * @retval None */ __STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel) @@ -758,7 +1336,9 @@ __STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel) * @arg @ref LL_PWR_PVDLEVEL_4 * @arg @ref LL_PWR_PVDLEVEL_5 * @arg @ref LL_PWR_PVDLEVEL_6 +#if !defined(PWR_STOP3_SUPPORT) * @arg @ref LL_PWR_PVDLEVEL_7 +#endif */ __STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void) { @@ -803,7 +1383,9 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void) * @arg @ref LL_PWR_WAKEUP_PIN2 * @arg @ref LL_PWR_WAKEUP_PIN3 * @arg @ref LL_PWR_WAKEUP_PIN4 +#if !defined(PWR_STOP3_SUPPORT) * @arg @ref LL_PWR_WAKEUP_PIN5 +#endif * @arg @ref LL_PWR_WAKEUP_PIN6 * @arg @ref LL_PWR_WAKEUP_PIN7 * @arg @ref LL_PWR_WAKEUP_PIN8 @@ -822,7 +1404,9 @@ __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin) * @arg @ref LL_PWR_WAKEUP_PIN2 * @arg @ref LL_PWR_WAKEUP_PIN3 * @arg @ref LL_PWR_WAKEUP_PIN4 +#if !defined(PWR_STOP3_SUPPORT) * @arg @ref LL_PWR_WAKEUP_PIN5 +#endif * @arg @ref LL_PWR_WAKEUP_PIN6 * @arg @ref LL_PWR_WAKEUP_PIN7 * @arg @ref LL_PWR_WAKEUP_PIN8 @@ -841,7 +1425,9 @@ __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin) * @arg @ref LL_PWR_WAKEUP_PIN2 * @arg @ref LL_PWR_WAKEUP_PIN3 * @arg @ref LL_PWR_WAKEUP_PIN4 +#if !defined(PWR_STOP3_SUPPORT) * @arg @ref LL_PWR_WAKEUP_PIN5 +#endif * @arg @ref LL_PWR_WAKEUP_PIN6 * @arg @ref LL_PWR_WAKEUP_PIN7 * @arg @ref LL_PWR_WAKEUP_PIN8 @@ -860,7 +1446,9 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin) * @arg @ref LL_PWR_WAKEUP_PIN2 * @arg @ref LL_PWR_WAKEUP_PIN3 * @arg @ref LL_PWR_WAKEUP_PIN4 +#if !defined(PWR_STOP3_SUPPORT) * @arg @ref LL_PWR_WAKEUP_PIN5 +#endif * @arg @ref LL_PWR_WAKEUP_PIN6 * @arg @ref LL_PWR_WAKEUP_PIN7 * @arg @ref LL_PWR_WAKEUP_PIN8 @@ -879,7 +1467,9 @@ __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin) * @arg @ref LL_PWR_WAKEUP_PIN2 * @arg @ref LL_PWR_WAKEUP_PIN3 * @arg @ref LL_PWR_WAKEUP_PIN4 +#if !defined(PWR_STOP3_SUPPORT) * @arg @ref LL_PWR_WAKEUP_PIN5 +#endif * @arg @ref LL_PWR_WAKEUP_PIN6 * @arg @ref LL_PWR_WAKEUP_PIN7 * @arg @ref LL_PWR_WAKEUP_PIN8 @@ -898,7 +1488,9 @@ __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin) * @arg @ref LL_PWR_WAKEUP_PIN2 * @arg @ref LL_PWR_WAKEUP_PIN3 * @arg @ref LL_PWR_WAKEUP_PIN4 +#if !defined(PWR_STOP3_SUPPORT) * @arg @ref LL_PWR_WAKEUP_PIN5 +#endif * @arg @ref LL_PWR_WAKEUP_PIN6 * @arg @ref LL_PWR_WAKEUP_PIN7 * @arg @ref LL_PWR_WAKEUP_PIN8 @@ -917,7 +1509,9 @@ __STATIC_INLINE uint32_t LL_PWR_GetWakeUpPinPolarity(uint32_t WakeUpPin) * @arg @ref LL_PWR_WAKEUP_PIN2 * @arg @ref LL_PWR_WAKEUP_PIN3 * @arg @ref LL_PWR_WAKEUP_PIN4 +#if !defined(PWR_STOP3_SUPPORT) * @arg @ref LL_PWR_WAKEUP_PIN5 +#endif * @arg @ref LL_PWR_WAKEUP_PIN6 * @arg @ref LL_PWR_WAKEUP_PIN7 * @arg @ref LL_PWR_WAKEUP_PIN8 @@ -937,7 +1531,9 @@ __STATIC_INLINE void LL_PWR_SetWakeUpPinSignal0Selection(uint32_t WakeUpPin) * @arg @ref LL_PWR_WAKEUP_PIN2 * @arg @ref LL_PWR_WAKEUP_PIN3 * @arg @ref LL_PWR_WAKEUP_PIN4 +#if !defined(PWR_STOP3_SUPPORT) * @arg @ref LL_PWR_WAKEUP_PIN5 +#endif * @arg @ref LL_PWR_WAKEUP_PIN6 * @arg @ref LL_PWR_WAKEUP_PIN7 * @arg @ref LL_PWR_WAKEUP_PIN8 @@ -957,7 +1553,9 @@ __STATIC_INLINE void LL_PWR_SetWakeUpPinSignal1Selection(uint32_t WakeUpPin) * @arg @ref LL_PWR_WAKEUP_PIN2 * @arg @ref LL_PWR_WAKEUP_PIN3 * @arg @ref LL_PWR_WAKEUP_PIN4 +#if !defined(PWR_STOP3_SUPPORT) * @arg @ref LL_PWR_WAKEUP_PIN5 +#endif * @arg @ref LL_PWR_WAKEUP_PIN6 * @arg @ref LL_PWR_WAKEUP_PIN7 * @arg @ref LL_PWR_WAKEUP_PIN8 @@ -977,7 +1575,9 @@ __STATIC_INLINE void LL_PWR_SetWakeUpPinSignal2Selection(uint32_t WakeUpPin) * @arg @ref LL_PWR_WAKEUP_PIN2 * @arg @ref LL_PWR_WAKEUP_PIN3 * @arg @ref LL_PWR_WAKEUP_PIN4 +#if !defined(PWR_STOP3_SUPPORT) * @arg @ref LL_PWR_WAKEUP_PIN5 +#endif * @arg @ref LL_PWR_WAKEUP_PIN6 * @arg @ref LL_PWR_WAKEUP_PIN7 * @arg @ref LL_PWR_WAKEUP_PIN8 @@ -997,7 +1597,9 @@ __STATIC_INLINE void LL_PWR_SetWakeUpPinSignal3Selection(uint32_t WakeUpPin) * @arg @ref LL_PWR_WAKEUP_PIN2 * @arg @ref LL_PWR_WAKEUP_PIN3 * @arg @ref LL_PWR_WAKEUP_PIN4 +#if !defined(PWR_STOP3_SUPPORT) * @arg @ref LL_PWR_WAKEUP_PIN5 +#endif * @arg @ref LL_PWR_WAKEUP_PIN6 * @arg @ref LL_PWR_WAKEUP_PIN7 * @arg @ref LL_PWR_WAKEUP_PIN8 @@ -1044,6 +1646,11 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void) * @arg @ref LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTA * @arg @ref LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTB * @arg @ref LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTC +#if defined(PWR_STOP2_SUPPORT) + * @arg @ref LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTD + * @arg @ref LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTE + * @arg @ref LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTG +#endif * @arg @ref LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTH * @param GPIOPin This parameter can be a combination of the following values: * @arg @ref LL_PWR_GPIO_PIN_0 @@ -1076,6 +1683,11 @@ __STATIC_INLINE void LL_PWR_EnableGPIOStandbyRetention(uint32_t GPIOPort, uint32 * @arg @ref LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTA * @arg @ref LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTB * @arg @ref LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTC +#if defined(PWR_STOP2_SUPPORT) + * @arg @ref LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTD + * @arg @ref LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTE + * @arg @ref LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTG +#endif * @arg @ref LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTH * @param GPIOPin This parameter can be a combinat+ion of the following values: * @arg @ref LL_PWR_GPIO_PIN_0 @@ -1108,6 +1720,11 @@ __STATIC_INLINE void LL_PWR_DisableGPIOStandbyRetention(uint32_t GPIOPort, uint3 * @arg @ref LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTA * @arg @ref LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTB * @arg @ref LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTC +#if defined(PWR_STOP2_SUPPORT) + * @arg @ref LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTD + * @arg @ref LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTE + * @arg @ref LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTG +#endif * @arg @ref LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTH * @param GPIOPin This parameter can be one of the following values: * @arg @ref LL_PWR_GPIO_PIN_0 @@ -1140,6 +1757,11 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOStandbyRetention(uint32_t GPIOPort, * @arg @ref LL_PWR_GPIO_STATE_RETENTION_STATUS_PORTA * @arg @ref LL_PWR_GPIO_STATE_RETENTION_STATUS_PORTB * @arg @ref LL_PWR_GPIO_STATE_RETENTION_STATUS_PORTC +#if defined(PWR_STOP2_SUPPORT) + * @arg @ref LL_PWR_GPIO_STATE_RETENTION_STATUS_PORTD + * @arg @ref LL_PWR_GPIO_STATE_RETENTION_STATUS_PORTE + * @arg @ref LL_PWR_GPIO_STATE_RETENTION_STATUS_PORTG +#endif * @arg @ref LL_PWR_GPIO_STATE_RETENTION_STATUS_PORTH * @param GPIOPin This parameter can be one of the following values: * @arg @ref LL_PWR_GPIO_PIN_0 @@ -1172,6 +1794,11 @@ __STATIC_INLINE uint32_t LL_PWR_IsGPIOStandbyStateRetained(uint32_t GPIOPort, ui * @arg @ref LL_PWR_GPIO_STATE_RETENTION_STATUS_PORTA * @arg @ref LL_PWR_GPIO_STATE_RETENTION_STATUS_PORTB * @arg @ref LL_PWR_GPIO_STATE_RETENTION_STATUS_PORTC +#if defined(PWR_STOP2_SUPPORT) + * @arg @ref LL_PWR_GPIO_STATE_RETENTION_STATUS_PORTD + * @arg @ref LL_PWR_GPIO_STATE_RETENTION_STATUS_PORTE + * @arg @ref LL_PWR_GPIO_STATE_RETENTION_STATUS_PORTG +#endif * @arg @ref LL_PWR_GPIO_STATE_RETENTION_STATUS_PORTH * @param GPIOPin This parameter can be one of the following values: * @arg @ref LL_PWR_GPIO_PIN_0 @@ -1202,6 +1829,9 @@ __STATIC_INLINE void LL_PWR_ClearGPIOStandbyRetentionStatus(uint32_t GPIOPort, u * @rmtoll SVMSR ACTVOS LL_PWR_GetRegulCurrentVOS * @retval Returned value can be one of the following values: * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 +#if defined(PWR_STOP3_SUPPORT) + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1_5 +#endif * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 */ __STATIC_INLINE uint32_t LL_PWR_GetRegulCurrentVOS(void) @@ -1354,6 +1984,44 @@ __STATIC_INLINE uint32_t LL_PWR_GetRadioMode(void) * @} */ +#if defined(PWR_STOP2_SUPPORT) && defined(PWR_S2RETR_PTASREN) +/** @defgroup PWR_LL_EF_PTA_STOP2_RETENTION_MANAGEMENT PWR PTA Stop2 Retention Management + * @{ + */ + +/** + * @brief Enable the PTA output signals retention in Stop 2 mode. + * @rmtoll S2RETR PTASRE LL_PWR_EnablePTAOutputStop2Retention + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnablePTAOutputStop2Retention(void) +{ + SET_BIT(PWR->S2RETR, PWR_S2RETR_PTASREN); +} + +/** + * @brief Disable the PTA output signals retention in Stop 2 mode. + * @rmtoll S2RETR PTASRE LL_PWR_DisablePTAOutputStop2Retention + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisablePTAOutputStop2Retention(void) +{ + CLEAR_BIT(PWR->S2RETR, PWR_S2RETR_PTASREN); +} + +/** + * @brief Check if the PTA output signals retention in Stop 2 mode is enabled. + * @rmtoll S2RETR PTASRE LL_PWR_IsEnabledPTAOutputStop2Retention + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledPTAOutputStop2Retention(void) +{ + return ((READ_BIT(PWR->S2RETR, PWR_S2RETR_PTASREN) == (PWR_S2RETR_PTASREN)) ? 1UL : 0UL); +} +/** + * @} + */ +#endif /* PWR_STOP2_SUPPORT && PWR_S2RETR_PTASREN */ /** @defgroup PWR_LL_EF_FLAG_MANAGEMENT PWR FLAG Management * @{ @@ -1370,6 +2038,29 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void) return ((READ_BIT(PWR->VOSR, PWR_VOSR_VOSRDY) == (PWR_VOSR_VOSRDY)) ? 1UL : 0UL); } +#if defined(PWR_STOP2_SUPPORT) +#if defined(USB_OTG_HS) +/** + * @brief Indicate whether the VDD11 USB is ready or not. + * @rmtoll SVMSR VDD11USBRDY LL_PWR_IsActiveFlag_VDD11USBRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VDD11USBRDY(void) +{ + return ((READ_BIT(PWR->VOSR, PWR_VOSR_VDD11USBRDY) == (PWR_VOSR_VDD11USBRDY)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether the USB booster is ready or not. + * @rmtoll SVMSR USBBOOSTRDY LL_PWR_IsActiveFlag_USBBOOSTRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_USBBOOSTRDY(void) +{ + return ((READ_BIT(PWR->VOSR, PWR_VOSR_USBBOOSTRDY) == (PWR_VOSR_USBBOOSTRDY)) ? 1UL : 0UL); +} +#endif /* defined(USB_OTG_HS) */ +#endif /* defined(PWR_STOP2_SUPPORT) */ /** * @brief Indicate whether the system was in standby mode or not. @@ -1391,6 +2082,17 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_STOP(void) return ((READ_BIT(PWR->SR, PWR_SR_STOPF) == (PWR_SR_STOPF)) ? 1UL : 0UL); } +#if defined(PWR_STOP2_SUPPORT) +/** + * @brief Indicate whether the system was in stop2 mode or not. + * @rmtoll SR STOP2F LL_PWR_IsActiveFlag_STOP2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_STOP2(void) +{ + return ((READ_BIT(PWR->SR, PWR_SR_STOP2F) == (PWR_SR_STOP2F)) ? 1UL : 0UL); +} +#endif /* defined(PWR_STOP2_SUPPORT) */ #if defined(PWR_SVMSR_REGS) /** @@ -1509,6 +2211,17 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU8(void) return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF8) == (PWR_WUSR_WUF8)) ? 1UL : 0UL); } +#if defined(PWR_STOP2_SUPPORT) && defined(PWR_S2RETR_PTASR) +/** + * @brief Indicate whether the PTA output signals state retention in Stop 2 mode is active or not. + * @rmtoll SVMSR PTASR LL_PWR_IsActiveFlag_PTASR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PTASR(void) +{ + return ((READ_BIT(PWR->S2RETR, PWR_S2RETR_PTASR) == (PWR_S2RETR_PTASR)) ? 1UL : 0UL); +} +#endif /* defined(PWR_STOP2_SUPPORT) && defined(PWR_S2RETR_PTASR) */ /** * @brief Clear stop flag. @@ -1520,6 +2233,17 @@ __STATIC_INLINE void LL_PWR_ClearFlag_STOP(void) WRITE_REG(PWR->SR, PWR_SR_CSSF); } +#if defined(PWR_STOP2_SUPPORT) +/** + * @brief Clear stop2 flag. + * @rmtoll SR CSSF LL_PWR_ClearFlag_STOP2 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_STOP2(void) +{ + WRITE_REG(PWR->SR, PWR_SR_CSSF); +} +#endif /* defined(PWR_STOP2_SUPPORT) */ /** * @brief Clear standby flag. @@ -1625,6 +2349,17 @@ __STATIC_INLINE void LL_PWR_ClearFlag_WU(void) WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF); } +#if defined(PWR_STOP2_SUPPORT) && defined(PWR_S2RETR_PTASR) +/** + * @brief Clear the PTA output signals state retention in Stop 2 mode active. + * @rmtoll SVMSR PTASR LL_PWR_ClearFlag_PTASR + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_PTASR(void) +{ + CLEAR_BIT(PWR->S2RETR, PWR_S2RETR_PTASR); +} +#endif /* defined(PWR_STOP2_SUPPORT) && defined(PWR_S2RETR_PTASR) */ /** * @} */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_rcc.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_rcc.h index 10239a1cc2..880d5e277f 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_rcc.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_rcc.h @@ -45,9 +45,9 @@ extern "C" { */ /* Defines used to perform offsets*/ /* Offset used to access to RCC_CCIPR1, RCC_CCIPR2 and RCC_CCIPR3 registers */ -#define RCC_OFFSET_CCIPR1 0U -#define RCC_OFFSET_CCIPR2 0x04U -#define RCC_OFFSET_CCIPR3 0x08U +#define RCC_OFFSET_CCIPR1 0UL +#define RCC_OFFSET_CCIPR2 0x04UL +#define RCC_OFFSET_CCIPR3 0x08UL /* Defines used for security configuration extension */ #define RCC_SECURE_MASK 0x10FBU @@ -272,9 +272,12 @@ typedef struct /** @defgroup RCC_LL_EC_SYSTICK_CLKSOURCE SYSTICK clock source selection * @{ */ -#define LL_RCC_SYSTICK_CLKSOURCE_HCLKDIV8 0U /*!< HCLKDIV8 clock used as SYSTICK clock source */ -#define LL_RCC_SYSTICK_CLKSOURCE_LSI RCC_CCIPR1_SYSTICKSEL_0 /*!< LSI clock used as SYSTICK clock source */ -#define LL_RCC_SYSTICK_CLKSOURCE_LSE RCC_CCIPR1_SYSTICKSEL_1 /*!< LSE clock used as SYSTICK clock source */ +#define LL_RCC_SYSTICK_CLKSOURCE_HCLKDIV8 0U /*!< HCLKDIV8 clock used as SYSTICK clock source */ +#define LL_RCC_SYSTICK_CLKSOURCE_LSI RCC_CCIPR1_SYSTICKSEL_0 /*!< LSI clock used as SYSTICK clock source */ +#define LL_RCC_SYSTICK_CLKSOURCE_LSE RCC_CCIPR1_SYSTICKSEL_1 /*!< LSE clock used as SYSTICK clock source */ +#if !defined (STM32WBA50xx) && !defined (STM32WBA52xx) && !defined (STM32WBA54xx) && !defined (STM32WBA55xx) && !defined (STM32WBA5Mxx) +#define LL_RCC_SYSTICK_CLKSOURCE_HSIDIV4 (RCC_CCIPR1_SYSTICKSEL_1 | RCC_CCIPR1_SYSTICKSEL_0) /*!< HSIDIV4 clock used as SYSTICK clock source */ +#endif /** * @} */ @@ -412,6 +415,12 @@ typedef struct #define LL_RCC_USART2_CLKSOURCE_HSI ((RCC_CCIPR1_USART2SEL << 16U) | RCC_CCIPR1_USART2SEL_1) /*!< HSI clock used as USART2 clock source */ #define LL_RCC_USART2_CLKSOURCE_LSE ((RCC_CCIPR1_USART2SEL << 16U) | RCC_CCIPR1_USART2SEL) /*!< LSE clock used as USART2 clock source */ #endif /* USART2 */ +#if defined(USART3) +#define LL_RCC_USART3_CLKSOURCE_PCLK1 (RCC_CCIPR1_USART3SEL << 16U) /*!< PCLK1 clock used as USART3 clock source */ +#define LL_RCC_USART3_CLKSOURCE_SYSCLK ((RCC_CCIPR1_USART3SEL << 16U) | RCC_CCIPR1_USART3SEL_0) /*!< SYSCLK clock used as USART3 clock source */ +#define LL_RCC_USART3_CLKSOURCE_HSI ((RCC_CCIPR1_USART3SEL << 16U) | RCC_CCIPR1_USART3SEL_1) /*!< HSI clock used as USART3 clock source */ +#define LL_RCC_USART3_CLKSOURCE_LSE ((RCC_CCIPR1_USART3SEL << 16U) | RCC_CCIPR1_USART3SEL) /*!< LSE clock used as USART3 clock source */ +#endif /* USART3 */ /** * @} */ @@ -433,9 +442,19 @@ typedef struct #define LL_RCC_I2C1_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C1SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C1 clock source */ #define LL_RCC_I2C1_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C1SEL_Pos << 16U) | (RCC_CCIPR1_I2C1SEL_0 >> RCC_CCIPR1_I2C1SEL_Pos)) /*!< SYSCLK clock used as I2C1 clock source */ #define LL_RCC_I2C1_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C1SEL_Pos << 16U) | (RCC_CCIPR1_I2C1SEL_1 >> RCC_CCIPR1_I2C1SEL_Pos)) /*!< HSI clock used as I2C1 clock source */ +#if defined(I2C2) +#define LL_RCC_I2C2_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C2SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C2 clock source */ +#define LL_RCC_I2C2_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C2SEL_Pos << 16U) | (RCC_CCIPR1_I2C2SEL_0 >> RCC_CCIPR1_I2C2SEL_Pos)) /*!< SYSCLK clock used as I2C2 clock source */ +#define LL_RCC_I2C2_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C2SEL_Pos << 16U) | (RCC_CCIPR1_I2C2SEL_1 >> RCC_CCIPR1_I2C2SEL_Pos)) /*!< HSI clock used as I2C2 clock source */ +#endif /* I2C2 */ #define LL_RCC_I2C3_CLKSOURCE_PCLK7 ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_I2C3SEL_Pos << 16U)) /*!< PCLK7 clock used as I2C3 clock source */ #define LL_RCC_I2C3_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_I2C3SEL_Pos << 16U) | (RCC_CCIPR3_I2C3SEL_0 >> RCC_CCIPR3_I2C3SEL_Pos)) /*!< SYSCLK clock used as I2C3 clock source */ #define LL_RCC_I2C3_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_I2C3SEL_Pos << 16U) | (RCC_CCIPR3_I2C3SEL_1 >> RCC_CCIPR3_I2C3SEL_Pos)) /*!< HSI clock used as I2C3 clock source */ +#if defined(I2C4) +#define LL_RCC_I2C4_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C4SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C4 clock source */ +#define LL_RCC_I2C4_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C4SEL_Pos << 16U) | (RCC_CCIPR1_I2C4SEL_0 >> RCC_CCIPR1_I2C4SEL_Pos)) /*!< SYSCLK clock used as I2C4 clock source */ +#define LL_RCC_I2C4_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C4SEL_Pos << 16U) | (RCC_CCIPR1_I2C4SEL_1 >> RCC_CCIPR1_I2C4SEL_Pos)) /*!< HSI clock used as I2C4 clock source */ +#endif /* I2C4 */ /** * @} */ @@ -448,6 +467,11 @@ typedef struct #define LL_RCC_SPI1_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI1SEL_Pos << 16U) | (RCC_CCIPR1_SPI1SEL_0 >> RCC_CCIPR1_SPI1SEL_Pos)) /*!< SYSCLK clock used as SPI1 clock source */ #define LL_RCC_SPI1_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI1SEL_Pos << 16U) | (RCC_CCIPR1_SPI1SEL_1 >> RCC_CCIPR1_SPI1SEL_Pos)) /*!< HSI clock used as SPI1 clock source */ #endif /* SPI1 */ +#if defined(SPI2) +#define LL_RCC_SPI2_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI2SEL_Pos << 16U)) /*!< PCLK1 clock used as SPI2 clock source */ +#define LL_RCC_SPI2_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI2SEL_Pos << 16U) | (RCC_CCIPR1_SPI2SEL_0 >> RCC_CCIPR1_SPI2SEL_Pos)) /*!< SYSCLK clock used as SPI2 clock source */ +#define LL_RCC_SPI2_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI2SEL_Pos << 16U) | (RCC_CCIPR1_SPI2SEL_1 >> RCC_CCIPR1_SPI2SEL_Pos)) /*!< HSI clock used as SPI2 clock source */ +#endif /* SPI2 */ #define LL_RCC_SPI3_CLKSOURCE_PCLK7 ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_SPI3SEL_Pos << 16U)) /*!< PCLK7 clock used as SPI3 clock source */ #define LL_RCC_SPI3_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_SPI3SEL_Pos << 16U) | (RCC_CCIPR3_SPI3SEL_0 >> RCC_CCIPR3_SPI3SEL_Pos)) /*!< SYSCLK clock used as SPI3 clock source */ #define LL_RCC_SPI3_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_SPI3SEL_Pos << 16U) | (RCC_CCIPR3_SPI3SEL_1 >> RCC_CCIPR3_SPI3SEL_Pos)) /*!< HSI clock used as SPI3 clock source */ @@ -517,6 +541,18 @@ typedef struct * @} */ +#if defined(USB_OTG_HS) +/** @defgroup RCC_LL_EC_SAI_CLKSOURCE Peripheral OTG_HS PHY clock source selection + * @{ + */ +#define LL_RCC_OTG_HS_CLKSOURCE_HSE 0U /*!< HSE clock used as OTGHS clock source */ +#define LL_RCC_OTG_HS_CLKSOURCE_PLL1P RCC_CCIPR2_OTGHSSEL_0 /*!< PLL1P clock used as OTGHS clock source */ +#define LL_RCC_OTG_HS_CLKSOURCE_HSE_DIV2 RCC_CCIPR2_OTGHSSEL_1 /*!< HSE/2 clock used as OTGHS clock source */ +#define LL_RCC_OTG_HS_CLKSOURCE_PLL1P_DIV2 (RCC_CCIPR2_OTGHSSEL_1 | RCC_CCIPR2_OTGHSSEL_0) /*!< PLL1P/2 clock used as OTGHS clock source */ +/** + * @} + */ +#endif /* USB_OTG_HS */ /** @defgroup RCC_LL_EC_TIM_INPUT_CAPTURE_CLOCKSource TIM Input capture clock source selection @@ -535,6 +571,9 @@ typedef struct #if defined(USART2) #define LL_RCC_USART2_CLKSOURCE RCC_CCIPR1_USART2SEL /*!< USART2 Clock source selection */ #endif /* USART2 */ +#if defined(USART3) +#define LL_RCC_USART3_CLKSOURCE RCC_CCIPR1_USART3SEL /*!< USART3 Clock source selection */ +#endif /* USART3 */ /** * @} */ @@ -545,6 +584,9 @@ typedef struct #if defined(SPI1) #define LL_RCC_SPI1_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI1SEL_Pos << 16U) | (RCC_CCIPR1_SPI1SEL >> RCC_CCIPR1_SPI1SEL_Pos)) /*!< SPI1 Clock source selection */ #endif /* SPI1 */ +#if defined(SPI2) +#define LL_RCC_SPI2_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI2SEL_Pos << 16U) | (RCC_CCIPR1_SPI2SEL >> RCC_CCIPR1_SPI2SEL_Pos)) /*!< SPI2 Clock source selection */ +#endif /* SPI2 */ #define LL_RCC_SPI3_CLKSOURCE ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_SPI3SEL_Pos << 16U) | (RCC_CCIPR3_SPI3SEL >> RCC_CCIPR3_SPI3SEL_Pos)) /*!< SPI3 Clock source selection */ /** * @} @@ -564,7 +606,13 @@ typedef struct #if defined(I2C1) #define LL_RCC_I2C1_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C1SEL_Pos << 16U) | (RCC_CCIPR1_I2C1SEL >> RCC_CCIPR1_I2C1SEL_Pos)) /*!< I2C1 Clock source selection */ #endif /* I2C1 */ +#if defined(I2C2) +#define LL_RCC_I2C2_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C2SEL_Pos << 16U) | (RCC_CCIPR1_I2C2SEL >> RCC_CCIPR1_I2C2SEL_Pos)) /*!< I2C2 Clock source selection */ +#endif /* I2C2 */ #define LL_RCC_I2C3_CLKSOURCE ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_I2C3SEL_Pos << 16U) | (RCC_CCIPR3_I2C3SEL >> RCC_CCIPR3_I2C3SEL_Pos)) /*!< I2C3 Clock source selection */ +#if defined(I2C4) +#define LL_RCC_I2C4_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C4SEL_Pos << 16U) | (RCC_CCIPR1_I2C4SEL >> RCC_CCIPR1_I2C4SEL_Pos)) /*!< I2C4 Clock source selection */ +#endif /* I2C4 */ /** * @} @@ -607,6 +655,15 @@ typedef struct * @} */ +#if defined(USB_OTG_HS) +/** @defgroup RCC_LL_EC_OTG_HS Peripheral OTG_HS PHY get clock source + * @{ + */ +#define LL_RCC_OTG_HS_CLKSOURCE RCC_CCIPR2_OTGHSSEL /*!< OTG_HS Clock source selection */ +/** + * @} + */ +#endif /* USB_OTG_HS */ /** @defgroup RCC_LL_EC_PLL1SOURCE PLL1 entry clock source * @{ @@ -1481,6 +1538,9 @@ __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler) * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_LSI * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_LSE * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_HCLKDIV8 + * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_HSIDIV4 (*) + * + * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_RCC_SetSystickClockSource(uint32_t SystickSource) @@ -1587,6 +1647,9 @@ __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void) * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_LSI * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_LSE * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_HCLKDIV8 + * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_HSIDIV4 (*) + * + * (*) value not defined in all devices. */ __STATIC_INLINE uint32_t LL_RCC_GetSystickClockSource(void) { @@ -1813,6 +1876,9 @@ __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescale * @brief Configure USARTx clock source * @rmtoll CCIPR1 USART1SEL LL_RCC_SetUSARTClockSource\n * CCIPR1 USART2SEL LL_RCC_SetUSARTClockSource\n +#if defined(USART3) + * CCIPR1 USART3SEL LL_RCC_SetUSARTClockSource +#endif * @param USARTxSource This parameter can be one of the following values: * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK @@ -1822,6 +1888,14 @@ __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescale * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE +#if defined(USART3) + * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*) + * + * (*) value not defined in all devices. +#endif * @retval None */ __STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource) @@ -1847,39 +1921,69 @@ __STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource) /** * @brief Configure I2Cx clock source * @rmtoll CCIPR1 I2C1SEL LL_RCC_SetI2CClockSource\n +#if defined(I2C2) + * CCIPR1 I2C2SEL LL_RCC_SetI2CClockSource\n +#endif * CCIPR3 I2C3SEL LL_RCC_SetI2CClockSource\n +#if defined(I2C4) + * CCIPR1 I2C4SEL LL_RCC_SetI2CClockSource +#endif * @param I2CxSource This parameter can be one of the following values: * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1 * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI +#if defined(I2C2) + * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK (*) + * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI (*) +#endif * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK7 * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI +#if defined(I2C4) + * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK (*) + * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*) + * + * (*) value not defined in all devices. +#endif * @retval None */ __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource) { __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (I2CxSource >> 24U)); - MODIFY_REG(*reg, 3U << (((I2CxSource & 0x00FF0000U) >> 16U) & 0x1FU), ((I2CxSource & 0x000000FFU) << (((I2CxSource & 0x00FF0000U) >> 16U) & 0x1FU))); + MODIFY_REG(*reg, 3UL << (((I2CxSource & 0x00FF0000U) >> 16U) & 0x1FU), ((I2CxSource & 0x000000FFU) << (((I2CxSource & 0x00FF0000U) >> 16U) & 0x1FU))); } /** * @brief Configure SPIx clock source * @rmtoll CCIPR1 SPI1SEL LL_RCC_SetSPIClockSource\n +#if defined(SPI2) + * CCIPR1 SPI2SEL LL_RCC_SetSPIClockSource +#endif * CCIPR3 SPI3SEL LL_RCC_SetSPIClockSource\n * @param SPIxSource This parameter can be one of the following values: * @arg @ref LL_RCC_SPI1_CLKSOURCE_PCLK2 * @arg @ref LL_RCC_SPI1_CLKSOURCE_SYSCLK * @arg @ref LL_RCC_SPI1_CLKSOURCE_HSI +#if defined(SPI2) + * @arg @ref LL_RCC_SPI2_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_SPI2_CLKSOURCE_SYSCLK (*) + * @arg @ref LL_RCC_SPI2_CLKSOURCE_HSI (*) +#endif * @arg @ref LL_RCC_SPI3_CLKSOURCE_PCLK7 * @arg @ref LL_RCC_SPI3_CLKSOURCE_SYSCLK * @arg @ref LL_RCC_SPI3_CLKSOURCE_HSI +#if defined(SPI2) + * + * (*) value not defined in all devices. +#endif * @retval None */ __STATIC_INLINE void LL_RCC_SetSPIClockSource(uint32_t SPIxSource) { __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (SPIxSource >> 24U)); - MODIFY_REG(*reg, 3U << (((SPIxSource & 0x00FF0000U) >> 16U) & 0x1FU), ((SPIxSource & 0x000000FFU) << (((SPIxSource & 0x00FF0000U) >> 16U) & 0x1FU))); + MODIFY_REG(*reg, 3UL << (((SPIxSource & 0x00FF0000U) >> 16U) & 0x1FU), ((SPIxSource & 0x000000FFU) << (((SPIxSource & 0x00FF0000U) >> 16U) & 0x1FU))); } /** @@ -1900,7 +2004,7 @@ __STATIC_INLINE void LL_RCC_SetSPIClockSource(uint32_t SPIxSource) __STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource) { __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (LPTIMxSource >> 24U)); - MODIFY_REG(*reg, 3U << (((LPTIMxSource & 0x00FF0000U) >> 16U) & 0x1FU), ((LPTIMxSource & 0x000000FFU) << (((LPTIMxSource & 0x00FF0000U) >> 16U) & 0x1FU))); + MODIFY_REG(*reg, 3UL << (((LPTIMxSource & 0x00FF0000U) >> 16U) & 0x1FU), ((LPTIMxSource & 0x000000FFU) << (((LPTIMxSource & 0x00FF0000U) >> 16U) & 0x1FU))); } @@ -1952,14 +2056,36 @@ __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADC4Source) MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_ADCSEL, ADC4Source); } +#if defined(USB_OTG_HS) +/** + * @brief Configure OTG_HS PHYx clock source + * @rmtoll CCIPR2 OTGHSSEL LL_RCC_SetOTGHSClockSource + * @param OTGHSxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_OTG_HS_CLKSOURCE_HSE + * @arg @ref LL_RCC_OTG_HS_CLKSOURCE_PLL1P + * @arg @ref LL_RCC_OTG_HS_CLKSOURCE_HSE_DIV2 + * @arg @ref LL_RCC_OTG_HS_CLKSOURCE_PLL1P_DIV2 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetOTGHSClockSource(uint32_t OTGHSxSource) +{ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_OTGHSSEL, OTGHSxSource); +} +#endif /* USB_OTG_HS */ /** * @brief Get USARTx clock source * @rmtoll CCIPR1 USART1SEL LL_RCC_GetUSARTClockSource\n * CCIPR1 USART2SEL LL_RCC_GetUSARTClockSource\n +#if defined(USART3) + * CCIPR1 USART3SEL LL_RCC_GetUSARTClockSource\n +#endif * @param USARTx This parameter can be one of the following values: * @arg @ref LL_RCC_USART1_CLKSOURCE * @arg @ref LL_RCC_USART2_CLKSOURCE +#if defined(USART3) + * @arg @ref LL_RCC_USART3_CLKSOURCE +#endif * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK @@ -1969,6 +2095,14 @@ __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADC4Source) * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE +#if defined(USART3) + * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*) + * + * (*) value not defined in all devices. +#endif */ __STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx) { @@ -1994,17 +2128,41 @@ __STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx) /** * @brief Get I2Cx clock source * @rmtoll CCIPR1 I2C1SEL LL_RCC_GetI2CClockSource\n +#if defined(I2C2) + * CCIPR1 I2C2SEL LL_RCC_GetI2CClockSource\n +#endif * CCIPR3 I2C3SEL LL_RCC_GetI2CClockSource\n +#if defined(I2C4) + * CCIPR1 I2C4SEL LL_RCC_GetI2CClockSource\n +#endif * @param I2Cx This parameter can be one of the following values: * @arg @ref LL_RCC_I2C1_CLKSOURCE +#if defined(I2C2) + * @arg @ref LL_RCC_I2C2_CLKSOURCE +#endif * @arg @ref LL_RCC_I2C3_CLKSOURCE +#if defined(I2C4) + * @arg @ref LL_RCC_I2C4_CLKSOURCE +#endif * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1 * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI +#if defined(I2C2) + * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK (*) + * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI (*) +#endif * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK7 * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI +#if defined(I2C4) + * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK (*) + * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*) + * + * (*) value not defined in all devices. +#endif */ __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx) { @@ -2015,17 +2173,32 @@ __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx) /** * @brief Get SPIx clock source * @rmtoll CCIPR1 SPI1SEL LL_RCC_GetSPIClockSource\n +#if defined(SPI2) + * CCIPR1 SPI2SEL LL_RCC_GetSPIClockSource +#endif * CCIPR3 SPI3SEL LL_RCC_GetSPIClockSource * @param SPIx This parameter can be one of the following values: * @arg @ref LL_RCC_SPI1_CLKSOURCE +#if defined(SPI2) + * @arg @ref LL_RCC_SPI2_CLKSOURCE +#endif * @arg @ref LL_RCC_SPI3_CLKSOURCE * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_SPI1_CLKSOURCE_PCLK2 * @arg @ref LL_RCC_SPI1_CLKSOURCE_SYSCLK * @arg @ref LL_RCC_SPI1_CLKSOURCE_HSI +#if defined(SPI2) + * @arg @ref LL_RCC_SPI2_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_SPI2_CLKSOURCE_SYSCLK (*) + * @arg @ref LL_RCC_SPI2_CLKSOURCE_HSI (*) +#endif * @arg @ref LL_RCC_SPI3_CLKSOURCE_PCLK7 * @arg @ref LL_RCC_SPI3_CLKSOURCE_SYSCLK * @arg @ref LL_RCC_SPI3_CLKSOURCE_HSI +#if defined(SPI2) + * + * (*) value not defined in all devices. +#endif */ __STATIC_INLINE uint32_t LL_RCC_GetSPIClockSource(uint32_t SPIx) { @@ -2133,6 +2306,23 @@ __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx) return (uint32_t)(READ_BIT(RCC->CCIPR3, ADCx)); } +#if defined(USB_OTG_HS) +/** + * @brief Get OTG_HS PHYx clock source + * @rmtoll CCIPR2 OTGHSSEL LL_RCC_GetOTGHSClockSource + * @param OTGHSx This parameter can be one of the following values: + * @arg @ref LL_RCC_OTG_HS_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_OTG_HS_CLKSOURCE_HSE + * @arg @ref LL_RCC_OTG_HS_CLKSOURCE_PLL1P + * @arg @ref LL_RCC_OTG_HS_CLKSOURCE_HSE_DIV2 + * @arg @ref LL_RCC_OTG_HS_CLKSOURCE_PLL1P_DIV2 + */ +__STATIC_INLINE uint32_t LL_RCC_GetOTGHSClockSource(uint32_t OTGHSx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR2, OTGHSx)); +} +#endif /* USB_OTG_HS */ /** * @} @@ -3250,6 +3440,9 @@ uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource); uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource); uint32_t LL_RCC_GetSPIClockFreq(uint32_t SPIxSource); uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource); +#if defined(USB_OTG_HS) +uint32_t LL_RCC_GetOTGHSClockFreq(uint32_t OTGHSxSource); +#endif /* USB_OTG_HS */ /** * @} */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_rng.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_rng.h index 7d47a67f1c..3bdb880a35 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_rng.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_rng.h @@ -677,7 +677,11 @@ __STATIC_INLINE void LL_RNG_SetHealthConfig(RNG_TypeDef *RNGx, uint32_t HTCFG) #if defined(RNG_HTCR_NIST_VALUE) /* For NIST compliance we can fin the recommended value in the application note AN4230 */ #endif /* defined(RNG_HTCR_NIST_VALUE) */ +#if defined(RNG_HTCR0_HTCFG) + WRITE_REG(RNGx->HTCR[0], HTCFG); +#else WRITE_REG(RNGx->HTCR, HTCFG); +#endif /* defined(RNG_HTCR0_HTCFG) */ } /** @@ -688,7 +692,11 @@ __STATIC_INLINE void LL_RNG_SetHealthConfig(RNG_TypeDef *RNGx, uint32_t HTCFG) */ __STATIC_INLINE uint32_t LL_RNG_GetHealthConfig(const RNG_TypeDef *RNGx) { +#if defined(RNG_HTCR0_HTCFG) + return (uint32_t)READ_REG(RNGx->HTCR[0]); +#else return (uint32_t)READ_REG(RNGx->HTCR); +#endif /* defined(RNG_HTCR0_HTCFG) */ } /** diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_rtc.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_rtc.h index 876a3faa3b..84fb18d556 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_rtc.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_rtc.h @@ -4282,7 +4282,9 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP4(const RTC_TypeDef *RTCx) UNUSED(RTCx); return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP4F) == (TAMP_SR_TAMP4F)) ? 1U : 0U); } +#endif /* TAMP_SR_TAMP4F */ +#ifdef TAMP_SR_TAMP5F /** * @brief Get tamper 5 detection flag. * @rmtoll TAMP_SR TAMP5F LL_RTC_IsActiveFlag_TAMP5 @@ -4294,7 +4296,9 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP5(const RTC_TypeDef *RTCx) UNUSED(RTCx); return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP5F) == (TAMP_SR_TAMP5F)) ? 1U : 0U); } +#endif /* TAMP_SR_TAMP5F */ +#ifdef TAMP_SR_TAMP6F /** * @brief Get tamper 6 detection flag. * @rmtoll TAMP_SR TAMP6F LL_RTC_IsActiveFlag_TAMP6 @@ -4306,7 +4310,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP6(const RTC_TypeDef *RTCx) UNUSED(RTCx); return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP6F) == (TAMP_SR_TAMP6F)) ? 1U : 0U); } -#endif /* TAMP_SR_TAMP4F */ +#endif /* TAMP_SR_TAMP6F */ /** * @brief Get internal tamper 3 detection flag. @@ -4464,7 +4468,9 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP4M(const RTC_TypeDef *RTCx) UNUSED(RTCx); return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP4MF) == (TAMP_MISR_TAMP4MF)) ? 1U : 0U); } +#endif /* TAMP_MISR_TAMP4MF */ +#ifdef TAMP_MISR_TAMP5MF /** * @brief Get tamper 5 interrupt masked flag. * @rmtoll TAMP_MISR TAMP5MF LL_RTC_IsActiveFlag_TAMP5M @@ -4476,7 +4482,9 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP5M(const RTC_TypeDef *RTCx) UNUSED(RTCx); return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP5MF) == (TAMP_MISR_TAMP5MF)) ? 1U : 0U); } +#endif /* TAMP_MISR_TAMP5MF */ +#ifdef TAMP_MISR_TAMP6MF /** * @brief Get tamper 6 interrupt masked flag. * @rmtoll TAMP_MISR TAMP6MF LL_RTC_IsActiveFlag_TAMP6M @@ -4488,7 +4496,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP6M(const RTC_TypeDef *RTCx) UNUSED(RTCx); return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP6MF) == (TAMP_MISR_TAMP6MF)) ? 1U : 0U); } -#endif /* TAMP_MISR_TAMP4MF */ +#endif /* TAMP_MISR_TAMP6MF */ /** * @brief Get internal tamper 3 interrupt masked flag. @@ -4646,7 +4654,9 @@ __STATIC_INLINE void LL_RTC_ClearFlag_TAMP4(const RTC_TypeDef *RTCx) UNUSED(RTCx); WRITE_REG(TAMP->SCR, TAMP_SCR_CTAMP4F); } +#endif /* TAMP_SCR_CTAMP4F */ +#ifdef TAMP_SCR_CTAMP5F /** * @brief Clear tamper 5 detection flag. * @rmtoll TAMP_SCR CTAMP5F LL_RTC_ClearFlag_TAMP5 @@ -4658,7 +4668,9 @@ __STATIC_INLINE void LL_RTC_ClearFlag_TAMP5(const RTC_TypeDef *RTCx) UNUSED(RTCx); WRITE_REG(TAMP->SCR, TAMP_SCR_CTAMP5F); } +#endif /* TAMP_SCR_CTAMP5F */ +#ifdef TAMP_SCR_CTAMP6F /** * @brief Clear tamper 6 detection flag. * @rmtoll TAMP_SCR CTAMP6F LL_RTC_ClearFlag_TAMP6 @@ -4670,7 +4682,7 @@ __STATIC_INLINE void LL_RTC_ClearFlag_TAMP6(const RTC_TypeDef *RTCx) UNUSED(RTCx); WRITE_REG(TAMP->SCR, TAMP_SCR_CTAMP6F); } -#endif /* TAMP_SCR_CTAMP4F */ +#endif /* TAMP_SCR_CTAMP6F */ /** * @brief Clear internal tamper 3 detection flag. @@ -5363,7 +5375,9 @@ __STATIC_INLINE void LL_RTC_DisableIT_TAMP4(const RTC_TypeDef *RTCx) UNUSED(RTCx); CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP4IE); } +#endif /* TAMP_IER_TAMP4IE */ +#ifdef TAMP_IER_TAMP5IE /** * @brief Enable tamper 5 interrupt. * @rmtoll TAMP_IER TAMP5IE LL_RTC_EnableIT_TAMP5 @@ -5387,7 +5401,9 @@ __STATIC_INLINE void LL_RTC_DisableIT_TAMP5(const RTC_TypeDef *RTCx) UNUSED(RTCx); CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP5IE); } +#endif /* TAMP_IER_TAMP5IE */ +#ifdef TAMP_IER_TAMP6IE /** * @brief Enable tamper 6 interrupt. * @rmtoll TAMP_IER TAMP6IE LL_RTC_EnableIT_TAMP6 @@ -5411,7 +5427,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_TAMP6(const RTC_TypeDef *RTCx) UNUSED(RTCx); CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP6IE); } -#endif /* TAMP_IER_TAMP4IE */ +#endif /* TAMP_IER_TAMP6IE */ /** * @brief Enable internal tamper 3 interrupt. @@ -5677,7 +5693,9 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP4(const RTC_TypeDef *RTCx) UNUSED(RTCx); return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP4IE) == (TAMP_IER_TAMP4IE)) ? 1U : 0U); } +#endif /* TAMP_IER_TAMP4IE */ +#ifdef TAMP_IER_TAMP5IE /** * @brief Check if tamper 5 interrupt is enabled or not. * @rmtoll TAMP_IER TAMP5IE LL_RTC_IsEnabledIT_TAMP5 @@ -5689,7 +5707,9 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP5(const RTC_TypeDef *RTCx) UNUSED(RTCx); return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP5IE) == (TAMP_IER_TAMP5IE)) ? 1U : 0U); } +#endif /* TAMP_IER_TAMP5IE */ +#ifdef TAMP_IER_TAMP6IE /** * @brief Check if tamper 6 interrupt is enabled or not. * @rmtoll TAMP_IER TAMP6IE LL_RTC_IsEnabledIT_TAMP6 @@ -5701,7 +5721,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP6(const RTC_TypeDef *RTCx) UNUSED(RTCx); return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP6IE) == (TAMP_IER_TAMP6IE)) ? 1U : 0U); } -#endif /* TAMP_IER_TAMP4IE */ +#endif /* TAMP_IER_TAMP6IE */ /** * @brief Check if internal tamper 3 interrupt is enabled or not. diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_spi.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_spi.h index 37db1561f3..722716adef 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_spi.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_spi.h @@ -31,7 +31,7 @@ extern "C" { * @{ */ -#if defined(SPI1) || defined(SPI3) +#if defined(SPI1) || defined(SPI2) || defined(SPI3) /** @defgroup SPI_LL SPI * @{ @@ -2722,7 +2722,7 @@ void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct); */ -#endif /* defined(SPI1) || defined(SPI3) */ +#endif /* defined(SPI1) || defined(SPI2) || defined(SPI3) */ /** * @} diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_system.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_system.h index 8f9ce8b0d9..08dfbac32e 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_system.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_system.h @@ -43,7 +43,7 @@ extern "C" { * @{ */ -#if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) +#if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined (VREFBUF) /** @defgroup SYSTEM_LL SYSTEM * @{ @@ -60,9 +60,18 @@ extern "C" { /** * @brief Power-down in Run mode Flash key */ +#if defined(FLASH_DBANK_SUPPORT) +#define FLASH_PDKEY1_1 0x04152637U /*!< Flash bank 1 power down key1 */ +#define FLASH_PDKEY1_2 0xFAFBFCFDU /*!< Flash bank 1 power down key2: used with FLASH_PDKEY1R + to unlock the PDREQ1 bit in FLASH_ACR */ +#define FLASH_PDKEY2_1 0x40516273U /*!< Flash bank 2 power down key1 */ +#define FLASH_PDKEY2_2 0xAFBFCFDFU /*!< Flash bank 2 power down key2: used with FLASH_PDKEY2R + to unlock the PDREQ2 bit in FLASH_ACR */ +#else #define FLASH_PDKEY1_1 0x04152637U /*!< Flash power down key1 */ #define FLASH_PDKEY1_2 0xFAFBFCFDU /*!< Flash power down key2: used with FLASH_PDKEYR to unlock the PDREQ bit in FLASH_ACR */ +#endif /* FLASH_DBANK_SUPPORT */ /** * @} */ @@ -150,11 +159,17 @@ extern "C" { */ #define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1LFZR_DBG_TIM2_STOP /*!< The counter clock of TIM2 is stopped when the core is halted*/ #define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1LFZR_DBG_TIM3_STOP /*!< The counter clock of TIM3 is stopped when the core is halted*/ +#if defined(TIM4) +#define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1LFZR_DBG_TIM4_STOP /*!< The counter clock of TIM4 is stopped when the core is halted*/ +#endif /* TIM4 */ #define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1LFZR_DBG_WWDG_STOP /*!< The window watchdog counter clock is stopped when the core is halted*/ #define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1LFZR_DBG_IWDG_STOP /*!< The independent watchdog counter clock is stopped when the core is halted*/ #if defined(I2C1) #define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1LFZR_DBG_I2C1_STOP /*!< The I2C1 SMBus timeout is frozen*/ #endif /* I2C1 */ +#if defined(I2C2) +#define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1LFZR_DBG_I2C2_STOP /*!< The I2C2 SMBus timeout is frozen*/ +#endif /* I2C2 */ /** * @} */ @@ -162,6 +177,9 @@ extern "C" { /** @defgroup SYSTEM_LL_EC_APB1_GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP * @{ */ +#if defined(I2C4) +#define LL_DBGMCU_APB1_GRP2_I2C4_STOP DBGMCU_APB1HFZR_DBG_I2C4_STOP /*!< The I2C4 SMBus timeout is frozen*/ +#endif /* I2C4 */ #if defined(LPTIM2) #define LL_DBGMCU_APB1_GRP2_LPTIM2_STOP DBGMCU_APB1HFZR_DBG_LPTIM2_STOP /*!< The counter clock of LPTIM2 is stopped when the core is halted*/ #endif /* LPTIM2 */ @@ -212,6 +230,18 @@ extern "C" { * @} */ +#if defined(VREFBUF) +/** @defgroup SYSTEM_LL_EC_VOLTAGE VREFBUF VOLTAGE + * @{ + */ +#define LL_VREFBUF_VOLTAGE_SCALE0 VREFBUF_CSR_VRS_OUT1 /*!< Voltage reference scale 0 (VREF_OUT1) */ +#define LL_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_OUT2 /*!< Voltage reference scale 1 (VREF_OUT2) */ +#define LL_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_OUT3 /*!< Voltage reference scale 2 (VREF_OUT3) */ +#define LL_VREFBUF_VOLTAGE_SCALE3 VREFBUF_CSR_VRS_OUT4 /*!< Voltage reference scale 3 (VREF_OUT4) */ +/** + * @} + */ +#endif /* VREFBUF */ /** * @} @@ -1170,6 +1200,20 @@ __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void) */ __STATIC_INLINE void LL_FLASH_EnableRunPowerDown(void) { +#if defined(FLASH_DBANK_SUPPORT) + /* Following values must be written consecutively to unlock the PDREQ1 bit in + FLASH_ACR for Bank 1 */ + WRITE_REG(FLASH->PDKEY1R, FLASH_PDKEY1_1); + WRITE_REG(FLASH->PDKEY1R, FLASH_PDKEY1_2); + + /* Following values must be written consecutively to unlock the PDREQ2 bit in + FLASH_ACR for Bank 2 */ + WRITE_REG(FLASH->PDKEY2R, FLASH_PDKEY2_1); + WRITE_REG(FLASH->PDKEY2R, FLASH_PDKEY2_2); + + /*Request to enter flash in power mode */ + SET_BIT(FLASH->ACR, (FLASH_ACR_PDREQ1 | FLASH_ACR_PDREQ2)); +#else /* Following values must be written consecutively to unlock the PDREQ bit in FLASH_ACR */ WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1_1); @@ -1177,6 +1221,7 @@ __STATIC_INLINE void LL_FLASH_EnableRunPowerDown(void) /*Request to enter flash in power mode */ SET_BIT(FLASH->ACR, FLASH_ACR_PDREQ); +#endif /* FLASH_DBANK_SUPPORT */ } /** @@ -1234,6 +1279,115 @@ __STATIC_INLINE uint32_t LL_FLASH_GetSTCompanyID(void) */ +#if defined(VREFBUF) +/** @defgroup SYSTEM_LL_EF_VREFBUF VREFBUF + * @{ + */ + +/** + * @brief Enable Internal voltage reference + * @rmtoll VREFBUF_CSR ENVR LL_VREFBUF_Enable + * @retval None + */ +__STATIC_INLINE void LL_VREFBUF_Enable(void) +{ + SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR); +} + +/** + * @brief Disable Internal voltage reference + * @rmtoll VREFBUF_CSR ENVR LL_VREFBUF_Disable + * @retval None + */ +__STATIC_INLINE void LL_VREFBUF_Disable(void) +{ + CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR); +} + +/** + * @brief Enable high impedance (VREF+pin is high impedance) + * @rmtoll VREFBUF_CSR HIZ LL_VREFBUF_EnableHIZ + * @retval None + */ +__STATIC_INLINE void LL_VREFBUF_EnableHIZ(void) +{ + SET_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ); +} + +/** + * @brief Disable high impedance (VREF+pin is internally connected to the voltage reference buffer output) + * @rmtoll VREFBUF_CSR HIZ LL_VREFBUF_DisableHIZ + * @retval None + */ +__STATIC_INLINE void LL_VREFBUF_DisableHIZ(void) +{ + CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ); +} + +/** + * @brief Set the Voltage reference scale + * @rmtoll VREFBUF_CSR VRS LL_VREFBUF_SetVoltageScaling + * @param Scale This parameter can be one of the following values: + * @arg @ref LL_VREFBUF_VOLTAGE_SCALE0 + * @arg @ref LL_VREFBUF_VOLTAGE_SCALE1 + * @arg @ref LL_VREFBUF_VOLTAGE_SCALE2 + * @arg @ref LL_VREFBUF_VOLTAGE_SCALE3 + * @retval None + */ +__STATIC_INLINE void LL_VREFBUF_SetVoltageScaling(uint32_t Scale) +{ + MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, Scale); +} + +/** + * @brief Get the Voltage reference scale + * @rmtoll VREFBUF_CSR VRS LL_VREFBUF_GetVoltageScaling + * @retval Returned value can be one of the following values: + * @arg @ref LL_VREFBUF_VOLTAGE_SCALE0 + * @arg @ref LL_VREFBUF_VOLTAGE_SCALE1 + * @arg @ref LL_VREFBUF_VOLTAGE_SCALE2 + * @arg @ref LL_VREFBUF_VOLTAGE_SCALE3 + */ +__STATIC_INLINE uint32_t LL_VREFBUF_GetVoltageScaling(void) +{ + return (uint32_t)(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRS)); +} + +/** + * @brief Check if Voltage reference buffer is ready + * @rmtoll VREFBUF_CSR VRR LL_VREFBUF_IsVREFReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_VREFBUF_IsVREFReady(void) +{ + return ((READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == VREFBUF_CSR_VRR) ? 1UL : 0UL); +} + +/** + * @brief Get the trimming code for VREFBUF calibration + * @rmtoll VREFBUF_CCR TRIM LL_VREFBUF_GetTrimming + * @retval Between 0 and 0x3F + */ +__STATIC_INLINE uint32_t LL_VREFBUF_GetTrimming(void) +{ + return (uint32_t)(READ_BIT(VREFBUF->CCR, VREFBUF_CCR_TRIM)); +} + +/** + * @brief Set the trimming code for VREFBUF calibration (Tune the internal reference buffer voltage) + * @rmtoll VREFBUF_CCR TRIM LL_VREFBUF_SetTrimming + * @param Value Between 0 and 0x3F + * @retval None + */ +__STATIC_INLINE void LL_VREFBUF_SetTrimming(uint32_t Value) +{ + WRITE_REG(VREFBUF->CCR, Value); +} + +/** + * @} + */ +#endif /* VREFBUF */ /** * @} diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_tim.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_tim.h index 6f7c5aff8f..a844b4fa62 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_tim.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_tim.h @@ -31,7 +31,7 @@ extern "C" { * @{ */ -#if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM16) || defined (TIM17) +#if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM16) || defined (TIM17) /** @defgroup TIM_LL TIM * @{ @@ -149,7 +149,7 @@ static const uint8_t SHIFT_TAB_OISx[] = */ #define OCREF_CLEAR_SELECT_POS (28U) -#define OCREF_CLEAR_SELECT_MSK (0x1U << OCREF_CLEAR_SELECT_POS) /*!< 0x10000000 */ +#define OCREF_CLEAR_SELECT_MSK (0x1UL << OCREF_CLEAR_SELECT_POS) /*!< 0x10000000 */ /** * @} */ @@ -172,6 +172,7 @@ static const uint8_t SHIFT_TAB_OISx[] = * @arg @ref LL_TIM_CHANNEL_CH6 * @retval none */ +#if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E) #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \ (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\ ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\ @@ -182,6 +183,13 @@ static const uint8_t SHIFT_TAB_OISx[] = ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\ ((__CHANNEL__) == LL_TIM_CHANNEL_CH4N) ? 7U :\ ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 8U : 9U) +#else +#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \ + (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U : 6U) +#endif /* TIM_CCER_CC5E && TIM_CCER_CC6E*/ /** @brief Calculate the deadtime sampling period(in ps). * @param __TIMCLK__ timer input clock frequency (in Hz). @@ -515,6 +523,7 @@ typedef struct @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ +#if defined(TIM_BDTR_BK2E) uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not. This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE @@ -552,6 +561,7 @@ typedef struct @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ +#endif /* TIM_BDTR_BK2E */ uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE @@ -582,12 +592,18 @@ typedef struct #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */ #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */ #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */ +#if defined(TIM_CCER_CC5E) #define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrupt flag */ +#endif /* TIM_CCER_CC5E */ +#if defined(TIM_CCER_CC6E) #define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrupt flag */ +#endif /* TIM_CCER_CC6E */ #define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */ #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */ #define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */ +#if defined(TIM_SR_B2IF) #define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt flag */ +#endif /* TIM_SR_B2IF */ #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */ #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */ #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */ @@ -610,6 +626,7 @@ typedef struct /** * @} */ +#if defined(TIM_BDTR_BK2E) /** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable * @{ @@ -619,6 +636,7 @@ typedef struct /** * @} */ +#endif /* TIM_BDTR_BK2E */ /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable * @{ @@ -734,13 +752,23 @@ typedef struct #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */ #define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */ #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */ +#if defined(TIM_CCER_CC2NE) #define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */ +#endif /* TIM_CCER_CC2NE */ #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */ +#if defined(TIM_CCER_CC3NE) #define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */ +#endif /* TIM_CCER_CC3NE */ #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */ -#define LL_TIM_CHANNEL_CH4N TIM_CCER_CC4NE /*!< Timer complementary output channel 4 */ +#if defined(TIM_CCER_CC4NE) +#define LL_TIM_CHANNEL_CH4N TIM_CCER_CC4NE /*!< Timer complementary output channel 4 */ +#endif /* TIM_CCER_CC4NE */ +#if defined(TIM_CCER_CC5E) #define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /*!< Timer output channel 5 */ +#endif /* TIM_CCER_CC5E */ +#if defined(TIM_CCER_CC6E) #define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /*!< Timer output channel 6 */ +#endif /* TIM_CCER_CC6E */ /** * @} */ @@ -806,6 +834,7 @@ typedef struct * @} */ +#if defined(TIM_CCR5_CCR5) /** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5 * @{ */ @@ -816,6 +845,7 @@ typedef struct /** * @} */ +#endif /* TIM_CCR5_CCR5 */ /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection * @{ @@ -913,6 +943,7 @@ typedef struct * @} */ +#if defined(TIM_CR2_MMS2) /** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2 * @{ */ @@ -935,6 +966,7 @@ typedef struct /** * @} */ +#endif /* TIM_CR2_MMS2 */ /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode * @{ @@ -962,11 +994,21 @@ typedef struct /** @defgroup TIM_LL_EC_TS Trigger Selection * @{ */ +#if defined(TIM1) #define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */ #define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */ +#endif /* TIM1 */ +#if defined(TIM3) #define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */ +#endif /* TIM3 */ +#if defined(TIM4) +#define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */ +#endif /* TIM4 */ #define LL_TIM_TS_ITR7 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 7 (ITR7) is used as trigger input */ #define LL_TIM_TS_ITR8 (TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 8 (ITR8) is used as trigger input */ +#if defined(USB_OTG_HS) || defined(USB_DRD_FS) +#define LL_TIM_TS_ITR11 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 11 (ITR11) is used as trigger input */ +#endif /* USB_OTG_HS || USB_DRD_FS */ #define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */ #define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */ #define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */ @@ -1018,6 +1060,7 @@ typedef struct * @} */ +#if defined(TIM1) /** @defgroup TIM_LL_EC_TIM1_ETRSOURCE External Trigger Source TIM1 * @{ */ @@ -1033,6 +1076,7 @@ typedef struct /** * @} */ +#endif /* TIM1 */ /** @defgroup TIM_LL_EC_TIM2_ETRSOURCE External Trigger Source TIM2 * @{ @@ -1043,12 +1087,23 @@ typedef struct #define LL_TIM_TIM2_ETRSOURCE_COMP2 TIM_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */ #endif /* COMP1 && COMP2 */ #define LL_TIM_TIM2_ETRSOURCE_HSI TIM_AF1_ETRSEL_2 /*!< ETR input is connected to HSI */ +#if defined(TIM3) #define LL_TIM_TIM2_ETRSOURCE_TIM3_ETR TIM_AF1_ETRSEL_3 /*!< ETR input is connected to TIM3 ETR */ +#endif /* TIM3 */ +#if defined(TIM4) +#define LL_TIM_TIM2_ETRSOURCE_TIM4_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_0) /*!< ETR input is connected to TIM4 ETR */ +#endif /* TIM4 */ #define LL_TIM_TIM2_ETRSOURCE_LSE (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /*!< ETR input is connected to LSE */ +#if defined(TIM2_ETR_ADC4_SUPPORT) +#define LL_TIM_TIM2_ETRSOURCE_ADC4_AWD1 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2) /*!< ADC4 analog watchdog 1 */ +#define LL_TIM_TIM2_ETRSOURCE_ADC4_AWD2 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) /*!< ADC4 analog watchdog 2 */ +#define LL_TIM_TIM2_ETRSOURCE_ADC4_AWD3 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1) /*!< ADC4 analog watchdog 3 */ +#endif /* TIM2_ETR_ADC4_SUPPORT */ /** * @} */ +#if defined(TIM3) /** @defgroup TIM_LL_EC_TIM3_ETRSOURCE External Trigger Source TIM3 * @{ */ @@ -1059,12 +1114,32 @@ typedef struct #endif /* COMP1 && COMP2 */ #define LL_TIM_TIM3_ETRSOURCE_HSI TIM_AF1_ETRSEL_2 /*!< ETR input is connected to HSI */ #define LL_TIM_TIM3_ETRSOURCE_TIM2_ETR TIM_AF1_ETRSEL_3 /*!< ETR input is connected to TIM2 ETR */ +#if defined(TIM4) +#define LL_TIM_TIM3_ETRSOURCE_TIM4_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_0) /*!< ETR input is connected to TIM4 ETR */ +#endif /* TIM4 */ #define LL_TIM_TIM3_ETRSOURCE_ADC4_AWD1 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /*!< ADC1 analog watchdog 1 */ #define LL_TIM_TIM3_ETRSOURCE_ADC4_AWD2 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2) /*!< ADC1 analog watchdog 2 */ #define LL_TIM_TIM3_ETRSOURCE_ADC4_AWD3 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) /*!< ADC1 analog watchdog 3 */ /** * @} */ +#endif /* TIM3 */ + +#if defined(TIM4) +/** @defgroup TIM_LL_EC_TIM4_ETRSOURCE External Trigger Source TIM4 + * @{ + */ +#define LL_TIM_TIM4_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */ +#if defined(COMP1) && defined(COMP2) +#define LL_TIM_TIM4_ETRSOURCE_COMP1 TIM_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */ +#define LL_TIM_TIM4_ETRSOURCE_COMP2 TIM_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */ +#endif /* COMP1 && COMP2 */ +#define LL_TIM_TIM4_ETRSOURCE_HSI TIM_AF1_ETRSEL_2 /*!< ETR input is connected to HSI */ +#define LL_TIM_TIM4_ETRSOURCE_TIM3_ETR TIM_AF1_ETRSEL_3 /*!< ETR input is connected to TIM3 ETR */ +/** + * @} + */ +#endif /* TIM4 */ /** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity * @{ @@ -1098,6 +1173,7 @@ typedef struct * @} */ +#if defined(TIM_BDTR_BK2P) /** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY * @{ */ @@ -1106,7 +1182,9 @@ typedef struct /** * @} */ +#endif /* TIM_BDTR_BK2P */ +#if defined(TIM_BDTR_BK2F) /** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER * @{ */ @@ -1129,6 +1207,7 @@ typedef struct /** * @} */ +#endif /* TIM_BDTR_BK2F */ /** @defgroup TIM_LL_EC_OSSI OSSI * @{ @@ -1152,7 +1231,9 @@ typedef struct * @{ */ #define LL_TIM_BREAK_INPUT_BKIN 0x00000000U /*!< TIMx_BKIN input */ +#if defined(TIM_BDTR_BK2E) #define LL_TIM_BREAK_INPUT_BKIN2 0x00000004U /*!< TIMx_BKIN2 input */ +#endif /* TIM_BDTR_BK2E */ /** * @} */ @@ -1187,6 +1268,7 @@ typedef struct * @} */ +#if defined(TIM_BDTR_BK2BID) /** @defgroup TIM_LL_EC_BREAK2_AFMODE BREAK2 AF MODE * @{ */ @@ -1195,12 +1277,15 @@ typedef struct /** * @} */ +#endif /* TIM_BDTR_BK2BID */ /** Legacy definitions for compatibility purpose @cond 0 */ #define LL_TIM_ReArmBRK(_PARAM_) +#if defined(TIM_BDTR_BK2E) #define LL_TIM_ReArmBRK2(_PARAM_) +#endif /* TIM_BDTR_BK2E */ /** @endcond */ @@ -1285,6 +1370,7 @@ typedef struct /** * @} */ +#if defined(TIM1) /** @defgroup TIM_LL_EC_TIM1_TI1_RMP TIM1 External Input Ch1 Remap * @{ */ @@ -1296,6 +1382,7 @@ typedef struct /** * @} */ +#endif /* TIM1 */ /** @defgroup TIM_LL_EC_TIM2_TI1_RMP TIM2 External Input Ch1 Remap * @{ @@ -1333,6 +1420,7 @@ typedef struct * @} */ +#if defined(TIM3) /** @defgroup TIM_LL_EC_TIM3_TI1_RMP TIM3 External Input Ch1 Remap * @{ */ @@ -1356,6 +1444,33 @@ typedef struct /** * @} */ +#endif /* TIM3 */ + +#if defined(TIM4) +/** @defgroup TIM_LL_EC_TIM4_TI1_RMP TIM4 External Input Ch1 Remap + * @{ + */ +#define LL_TIM_TIM4_TI1_RMP_GPIO 0x00000000UL /*!< TIM4 TI1 is connected to GPIO */ +#if defined(COMP1) && defined(COMP2) +#define LL_TIM_TIM4_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM4 TI1 is connected to COMP1 output */ +#define LL_TIM_TIM4_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM4 TI1 is connected to COMP2 output */ +#endif /* COMP1 && COMP2 */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_TIM4_TI2_RMP TIM4 External Input Ch2 Remap + * @{ + */ +#define LL_TIM_TIM4_TI2_RMP_GPIO 0x00000000UL /*!< TIM4 TI2 is connected to GPIO */ +#if defined(COMP1) && defined(COMP2) +#define LL_TIM_TIM4_TI2_RMP_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM4 TI2 is connected to COMP1 output */ +#define LL_TIM_TIM4_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM4 TI2 is connected to COMP2 output */ +#endif /* COMP1 && COMP2 */ +/** + * @} + */ +#endif /* TIM4 */ /** @defgroup TIM_LL_EC_TIM16_TI1_RMP TIM16 External Input Ch1 Remap * @{ @@ -1389,8 +1504,10 @@ typedef struct * @{ */ #define LL_TIM_OCREF_CLR_INT_ETR OCREF_CLEAR_SELECT_MSK /*!< OCREF_CLR_INT is connected to ETRF */ +#if defined(COMP1) && defined(COMP2) #define LL_TIM_OCREF_CLR_INT_COMP1 0x00000000U /*!< OCREF clear input is connected to COMP1_OUT */ #define LL_TIM_OCREF_CLR_INT_COMP2 TIM_AF2_OCRSEL_0 /*!< OCREF clear input is connected to COMP2_OUT */ +#endif /* COMP1 && COMP2 */ /** * @} */ @@ -2900,6 +3017,7 @@ __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t Compare WRITE_REG(TIMx->CCR4, CompareValue); } +#if defined(TIM_CCR5_CCR5) /** * @brief Set compare value for output channel 5 (TIMx_CCR5). * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not @@ -2915,6 +3033,8 @@ __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t Compare MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue); } +#endif /* TIM_CCR5_CCR5 */ +#if defined(TIM_CCR6_CCR6) /** * @brief Set compare value for output channel 6 (TIMx_CCR6). * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not @@ -2930,6 +3050,7 @@ __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t Compare WRITE_REG(TIMx->CCR6, CompareValue); } +#endif /* TIM_CCR6_CCR6 */ /** * @brief Get compare value (TIMx_CCR1) set for output channel 1. * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. @@ -2998,6 +3119,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx) return (uint32_t)(READ_REG(TIMx->CCR4)); } +#if defined(TIM_CCR5_CCR5) /** * @brief Get compare value (TIMx_CCR5) set for output channel 5. * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not @@ -3012,6 +3134,8 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(const TIM_TypeDef *TIMx) return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5)); } +#endif /* TIM_CCR5_CCR5 */ +#if defined(TIM_CCR6_CCR6) /** * @brief Get compare value (TIMx_CCR6) set for output channel 6. * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not @@ -3026,6 +3150,8 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(const TIM_TypeDef *TIMx) return (uint32_t)(READ_REG(TIMx->CCR6)); } +#endif /* TIM_CCR6_CCR6 */ +#if defined(TIM_CCR5_CCR5) /** * @brief Select on which reference signal the OC5REF is combined to. * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check @@ -3046,6 +3172,7 @@ __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t G MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5); } +#endif /* TIM_CCR5_CCR5 */ /** * @brief Set the pulse on compare pulse width prescaler. * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check @@ -3636,6 +3763,7 @@ __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSy MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization); } +#if defined(TIM_CR2_MMS2) /** * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization . * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check @@ -3666,6 +3794,7 @@ __STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSyn MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization); } +#endif /* TIM_CR2_MMS2 */ /** * @brief Set the synchronization mode of a slave timer. * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not @@ -3693,15 +3822,19 @@ __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode) * @rmtoll SMCR TS LL_TIM_SetTriggerInput * @param TIMx Timer instance * @param TriggerInput This parameter can be one of the following values: - * @arg @ref LL_TIM_TS_ITR0 - * @arg @ref LL_TIM_TS_ITR1 - * @arg @ref LL_TIM_TS_ITR2 + * @arg @ref LL_TIM_TS_ITR0 (*) + * @arg @ref LL_TIM_TS_ITR1 (*) + * @arg @ref LL_TIM_TS_ITR2 (*) + * @arg @ref LL_TIM_TS_ITR3 (*) * @arg @ref LL_TIM_TS_ITR7 * @arg @ref LL_TIM_TS_ITR8 + * @arg @ref LL_TIM_TS_ITR11 (*) * @arg @ref LL_TIM_TS_TI1F_ED * @arg @ref LL_TIM_TS_TI1FP1 * @arg @ref LL_TIM_TS_TI2FP2 * @arg @ref LL_TIM_TS_ETRF + * + * (*) Value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput) @@ -3797,11 +3930,11 @@ __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, u * @param TIMx Timer instance * @param ETRSource This parameter can be one of the following values: * - * For TIM1, the parameter is one of the following values: + * For TIM1, the parameter is one of the following values: (**) * * @arg @ref LL_TIM_TIM1_ETRSOURCE_GPIO - * @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP1 (*) - * @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP2 (*) + * @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP1 (*) + * @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP2 (*) * @arg @ref LL_TIM_TIM1_ETRSOURCE_HSI * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC4_AWD1 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC4_AWD2 @@ -3810,24 +3943,38 @@ __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, u * For TIM2, the parameter is one of the following values: * * @arg @ref LL_TIM_TIM2_ETRSOURCE_GPIO - * @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP1 (*) - * @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP2 (*) + * @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP1 (*) + * @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP2 (*) * @arg @ref LL_TIM_TIM2_ETRSOURCE_HSI - * @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM3_ETR + * @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM3_ETR (*) + * @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM4_ETR (*) * @arg @ref LL_TIM_TIM2_ETRSOURCE_LSE + * @arg @ref LL_TIM_TIM2_ETRSOURCE_ADC4_AWD1 (*) + * @arg @ref LL_TIM_TIM2_ETRSOURCE_ADC4_AWD2 (*) + * @arg @ref LL_TIM_TIM2_ETRSOURCE_ADC4_AWD3 (*) * - * For TIM3, the parameter is one of the following values: + * For TIM3, the parameter is one of the following values: (**) * * @arg @ref LL_TIM_TIM3_ETRSOURCE_GPIO - * @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP1 (*) - * @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP2 (*) + * @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP1 (*) + * @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP2 (*) * @arg @ref LL_TIM_TIM3_ETRSOURCE_HSI * @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM2_ETR + * @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM4_ETR (*) * @arg @ref LL_TIM_TIM3_ETRSOURCE_ADC4_AWD1 * @arg @ref LL_TIM_TIM3_ETRSOURCE_ADC4_AWD2 * @arg @ref LL_TIM_TIM3_ETRSOURCE_ADC4_AWD3 * + * For TIM4, the parameter is one of the following values: (**) + * + * @arg @ref LL_TIM_TIM4_ETRSOURCE_GPIO + * @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP1 + * @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP2 + * @arg @ref LL_TIM_TIM4_ETRSOURCE_HSI + * @arg @ref LL_TIM_TIM4_ETRSOURCE_TIM3_ETR + * * (*) Value not defined in all devices. \n + * (**) Timer instance not available on all devices \n * @retval None */ __STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource) @@ -4001,6 +4148,7 @@ __STATIC_INLINE void LL_TIM_DisarmBRK(TIM_TypeDef *TIMx) SET_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM); } +#if defined(TIM_BDTR_BK2E) /** * @brief Enable the break 2 function. * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not @@ -4090,6 +4238,7 @@ __STATIC_INLINE void LL_TIM_DisarmBRK2(TIM_TypeDef *TIMx) SET_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM); } +#endif /* TIM_BDTR_BK2E */ /** * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes. * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not @@ -4205,11 +4354,13 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx) * @param TIMx Timer instance * @param BreakInput This parameter can be one of the following values: * @arg @ref LL_TIM_BREAK_INPUT_BKIN - * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 + * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 (*) * @param Source This parameter can be one of the following values: * @arg @ref LL_TIM_BKIN_SOURCE_BKIN - * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 - * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 + * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 (*) + * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 (*) + * + * (*) Value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source) @@ -4231,11 +4382,13 @@ __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t B * @param TIMx Timer instance * @param BreakInput This parameter can be one of the following values: * @arg @ref LL_TIM_BREAK_INPUT_BKIN - * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 + * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 (*) * @param Source This parameter can be one of the following values: * @arg @ref LL_TIM_BKIN_SOURCE_BKIN - * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 - * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 + * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 (*) + * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 (*) + * + * (*) Value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source) @@ -4257,14 +4410,16 @@ __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t * @param TIMx Timer instance * @param BreakInput This parameter can be one of the following values: * @arg @ref LL_TIM_BREAK_INPUT_BKIN - * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 + * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 (*) * @param Source This parameter can be one of the following values: * @arg @ref LL_TIM_BKIN_SOURCE_BKIN - * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 - * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 + * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 (*) + * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 (*) * @param Polarity This parameter can be one of the following values: * @arg @ref LL_TIM_BKIN_POLARITY_LOW * @arg @ref LL_TIM_BKIN_POLARITY_HIGH + * + * (*) Value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source, @@ -4710,7 +4865,7 @@ __STATIC_INLINE void LL_TIM_ConfigIDX(TIM_TypeDef *TIMx, uint32_t Configuration) * * Below description summarizes "Timer Instance" and "Remap" param combinations: * - * TIM1: one of the following values: + * TIM1: one of the following values: (**) * @arg LL_TIM_TIM1_TI1_RMP_GPIO: TIM1 TI1 is connected to GPIO * @arg LL_TIM_TIM1_TI1_RMP_COMP1: TIM1 TI1 is connected to COMP1 output (*) * @arg LL_TIM_TIM1_TI1_RMP_COMP2: TIM1 TI1 is connected to COMP2 output (*) @@ -4726,7 +4881,7 @@ __STATIC_INLINE void LL_TIM_ConfigIDX(TIM_TypeDef *TIMx, uint32_t Configuration) * @arg LL_TIM_TIM2_TI4_RMP_COMP1: TIM2 TI4 is connected to COMP1 output (*) * @arg LL_TIM_TIM2_TI4_RMP_COMP2: TIM2 TI4 is connected to COMP2 output (*) * - * TIM3: one of the following values: + * TIM3: one of the following values: (**) * @arg LL_TIM_TIM3_TI1_RMP_GPIO: TIM3 TI1 is connected to GPIO * @arg LL_TIM_TIM3_TI1_RMP_COMP1: TIM3 TI1 is connected to COMP1 output (*) * @arg LL_TIM_TIM3_TI1_RMP_COMP2: TIM3 TI1 is connected to COMP2 output (*) @@ -4734,6 +4889,14 @@ __STATIC_INLINE void LL_TIM_ConfigIDX(TIM_TypeDef *TIMx, uint32_t Configuration) * @arg LL_TIM_TIM3_TI2_RMP_COMP1: TIM3 TI2 is connected to COMP1 output (*) * @arg LL_TIM_TIM3_TI2_RMP_COMP2: TIM3 TI2 is connected to COMP2 output (*) * + * TIM4: one of the following values: (**) + * @arg LL_TIM_TIM4_TI1_RMP_GPIO: TIM4 TI1 is connected to GPIO + * @arg LL_TIM_TIM4_TI1_RMP_COMP1: TIM4 TI1 is connected to COMP1 output + * @arg LL_TIM_TIM4_TI1_RMP_COMP2: TIM4 TI1 is connected to COMP2 output + * @arg LL_TIM_TIM4_TI2_RMP_GPIO: TIM4 TI2 is connected to GPIO + * @arg LL_TIM_TIM4_TI2_RMP_COMP1: TIM4 TI2 is connected to COMP1 output + * @arg LL_TIM_TIM4_TI2_RMP_COMP2: TIM4 TI2 is connected to COMP2 output + * * TIM16: one of the following values: * @arg LL_TIM_TIM16_TI1_RMP_GPIO: TIM16 TI1 is connected to GPIO * @arg LL_TIM_TIM16_TI1_RMP_MCO: TIM16 TI1 is connected to MCO @@ -4753,7 +4916,7 @@ __STATIC_INLINE void LL_TIM_ConfigIDX(TIM_TypeDef *TIMx, uint32_t Configuration) * @arg LL_TIM_TIM17_TI1_RMP_HSI_256: TIM17 TI1 is connected to HSI/256 * * (*) Value not defined in all devices. \n - + * (**) Timer instance not available on all devices. \n * * @retval None */ @@ -4943,6 +5106,7 @@ __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx) return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL); } +#if defined (TIM_SR_CC5IF) /** * @brief Clear the Capture/Compare 5 interrupt flag (CC5F). * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5 @@ -4965,6 +5129,8 @@ __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef *TIMx) return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL); } +#endif /* TIM_SR_CC5IF */ +#if defined (TIM_SR_CC6IF) /** * @brief Clear the Capture/Compare 6 interrupt flag (CC6F). * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6 @@ -4987,6 +5153,7 @@ __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef *TIMx) return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL); } +#endif /* TIM_SR_CC6IF */ /** * @brief Clear the commutation interrupt flag (COMIF). * @rmtoll SR COMIF LL_TIM_ClearFlag_COM @@ -5053,6 +5220,7 @@ __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx) return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL); } +#if defined(TIM_SR_B2IF) /** * @brief Clear the break 2 interrupt flag (B2IF). * @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2 @@ -5075,6 +5243,7 @@ __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef *TIMx) return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL); } +#endif /* TIM_SR_B2IF */ /** * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF). * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR @@ -6052,6 +6221,7 @@ __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx) SET_BIT(TIMx->EGR, TIM_EGR_BG); } +#if defined(TIM_EGR_B2G) /** * @brief Generate break 2 event. * @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2 @@ -6063,6 +6233,7 @@ __STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx) SET_BIT(TIMx->EGR, TIM_EGR_B2G); } +#endif /* TIM_EGR_B2G */ /** * @} */ @@ -6098,7 +6269,7 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *T * @} */ -#endif /* TIM1 || TIM2 || TIM3 || TIM16 || TIM17 */ +#endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM16 || TIM17 */ /** * @} diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_usart.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_usart.h index 7ce0589479..496473ee86 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_usart.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_usart.h @@ -31,7 +31,7 @@ extern "C" { * @{ */ -#if defined(USART1) || defined(USART2) +#if defined(USART1) || defined(USART2) || defined(USART3) /** @defgroup USART_LL USART * @{ @@ -56,6 +56,10 @@ static const uint32_t USART_PRESCALER_TAB[] = 32UL, 64UL, 128UL, + 256UL, + 256UL, + 256UL, + 256UL, 256UL }; /** @@ -4478,7 +4482,7 @@ void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitS * @} */ -#endif /* USART1 || USART2 */ +#endif /* USART1 || USART2 || USART3 */ /** * @} diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_usb.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_usb.h new file mode 100644 index 0000000000..34385bb1ea --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_usb.h @@ -0,0 +1,1296 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_ll_usb.h + * @author MCD Application Team + * @brief Header file of USB Low Layer HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_LL_USB_H +#define STM32WBAxx_LL_USB_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal_def.h" + +#if defined (USB_OTG_HS) || defined (USB_DRD_FS) +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @addtogroup USB_LL + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +#ifndef HAL_USB_TIMEOUT +#define HAL_USB_TIMEOUT 0xF000000U +#endif /* define HAL_USB_TIMEOUT */ + +#ifndef HAL_USB_CURRENT_MODE_MAX_DELAY_MS +#define HAL_USB_CURRENT_MODE_MAX_DELAY_MS 200U +#endif /* define HAL_USB_CURRENT_MODE_MAX_DELAY_MS */ + +/** + * @brief USB Mode definition + */ + +typedef enum +{ + USB_DEVICE_MODE = 0, + USB_HOST_MODE = 1, + USB_DRD_MODE = 2 +} USB_ModeTypeDef; + +#if defined (HAL_HCD_MODULE_ENABLED) +/** + * @brief URB States definition + */ +typedef enum +{ + URB_IDLE = 0, + URB_DONE, + URB_NOTREADY, + URB_NYET, + URB_ERROR, + URB_STALL, + URB_NAK_WAIT +} USB_URBStateTypeDef; + +/** + * @brief Host channel States definition + */ +typedef enum +{ + HC_IDLE = 0, + HC_XFRC, + HC_HALTED, + HC_ACK, + HC_NAK, + HC_NYET, + HC_STALL, + HC_XACTERR, + HC_BBLERR, + HC_DATATGLERR +} USB_HCStateTypeDef; +#endif /* defined (HAL_HCD_MODULE_ENABLED) */ + + +/** + * @brief USB Instance Initialization Structure definition + */ +typedef struct +{ + uint8_t dev_endpoints; /*!< Device Endpoints number. + This parameter depends on the used USB core. + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint8_t Host_channels; /*!< Host Channels number. + This parameter Depends on the used USB core. + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint8_t dma_enable; /*!< USB DMA state. + If DMA is not supported this parameter shall be set by default to zero */ + + uint8_t speed; /*!< USB Core speed. + This parameter can be any value of @ref PCD_Speed/HCD_Speed + (HCD_SPEED_xxx, HCD_SPEED_xxx) */ + + uint8_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */ + + uint8_t phy_itface; /*!< Select the used PHY interface. + This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */ + + uint8_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ + + uint8_t low_power_enable; /*!< Enable or disable the low Power Mode. */ + + uint8_t lpm_enable; /*!< Enable or disable Link Power Management. */ + + uint8_t battery_charging_enable; /*!< Enable or disable Battery charging. */ + + uint8_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */ + +#if defined (USB_OTG_HS) + uint8_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */ + + uint8_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */ +#endif /* defined (USB_OTG_HS) */ +#if defined (USB_DRD_FS) + uint8_t bulk_doublebuffer_enable; /*!< Enable or disable the double buffer mode on bulk EP */ + + uint8_t iso_singlebuffer_enable; /*!< Enable or disable the Single buffer mode on Isochronous EP */ +#endif /* defined (USB_DRD_FS) */ +} USB_CfgTypeDef; + +#if defined (HAL_PCD_MODULE_ENABLED) +typedef struct +{ + uint8_t num; /*!< Endpoint number + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint8_t is_in; /*!< Endpoint direction + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t is_stall; /*!< Endpoint stall condition + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + +#if defined (USB_OTG_HS) + uint8_t is_iso_incomplete; /*!< Endpoint isoc condition + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ +#endif /* defined (USB_OTG_HS) */ + + uint8_t type; /*!< Endpoint type + This parameter can be any value of @ref USB_LL_EP_Type */ + + uint8_t data_pid_start; /*!< Initial data PID + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + +#if defined (USB_DRD_FS) + uint16_t pmaadress; /*!< PMA Address + This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ + + uint16_t pmaaddr0; /*!< PMA Address0 + This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ + + uint16_t pmaaddr1; /*!< PMA Address1 + This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ + + uint8_t doublebuffer; /*!< Double buffer enable + This parameter can be 0 or 1 */ +#endif /* defined (USB_DRD_FS) */ + + uint32_t maxpacket; /*!< Endpoint Max packet size + This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ + + uint8_t *xfer_buff; /*!< Pointer to transfer buffer */ + + uint32_t xfer_len; /*!< Current transfer length */ + + uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */ + +#if defined (USB_OTG_HS) + uint8_t even_odd_frame; /*!< IFrame parity + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint16_t tx_fifo_num; /*!< Transmission FIFO number + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address */ + + uint32_t xfer_size; /*!< requested transfer size */ +#endif /* defined (USB_OTG_HS) */ + +#if defined (USB_DRD_FS) + uint32_t xfer_len_db; /*!< double buffer transfer length used with bulk double buffer in */ + + uint8_t xfer_fill_db; /*!< double buffer Need to Fill new buffer used with bulk_in */ +#endif /* defined (USB_DRD_FS) */ +} USB_EPTypeDef; +#endif /* defined (HAL_PCD_MODULE_ENABLED) */ + +#if defined (HAL_HCD_MODULE_ENABLED) +typedef struct +{ + uint8_t dev_addr; /*!< USB device address. + This parameter must be a number between Min_Data = 1 and Max_Data = 255 */ +#if defined (USB_DRD_FS) + uint8_t phy_ch_num; /*!< Host channel number. + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + +#else + uint8_t ch_num; /*!< Host channel number. + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint8_t ep_is_in; /*!< Endpoint direction + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ +#endif /* defined (USB_DRD_FS) */ + + uint8_t ep_num; /*!< Endpoint number. + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + uint8_t ch_dir; /*!< channel direction + This parameter store the physical channel direction IN/OUT/BIDIR */ + + uint8_t speed; /*!< USB Host Channel speed. + This parameter can be any value of @ref HCD_Device_Speed: + (HCD_DEVICE_SPEED_xxx) */ + +#if defined (USB_OTG_HS) + uint8_t do_ping; /*!< Enable or disable the use of the PING protocol for HS mode. */ + uint8_t do_ssplit; /*!< Enable start split transaction in HS mode. */ + uint8_t do_csplit; /*!< Enable complete split transaction in HS mode. */ + uint8_t ep_ss_schedule; /*!< Enable periodic endpoint start split schedule . */ + uint32_t iso_splt_xactPos; /*!< iso split transfer transaction position. */ +#endif /* defined (USB_OTG_HS) */ + + uint8_t hub_port_nbr; /*!< USB HUB port number */ + uint8_t hub_addr; /*!< USB HUB address */ + + uint8_t ep_type; /*!< Endpoint Type. + This parameter can be any value of @ref USB_LL_EP_Type */ + + uint16_t max_packet; /*!< Endpoint Max packet size. + This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ + + uint8_t data_pid; /*!< Initial data PID. + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */ + +#if defined (USB_OTG_HS) + uint32_t XferSize; /*!< OTG Channel transfer size. */ +#endif /* defined (USB_OTG_HS) */ + + uint32_t xfer_len; /*!< Current transfer length. */ +#if defined (USB_DRD_FS) + uint32_t xfer_len_db; /*!< Current transfer length used in double buffer mode. */ +#endif /* defined (USB_DRD_FS) */ + + uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer. */ + + uint8_t toggle_in; /*!< IN transfer current toggle flag. + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t toggle_out; /*!< OUT transfer current toggle flag + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ +#if defined (USB_OTG_HS) + uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address. */ + uint32_t NyetErrCnt; /*!< Complete Split NYET Host channel error count. */ + + uint32_t NakCnt; /*!< Host channel NAK count. */ +#endif /* defined (USB_OTG_HS) */ + + uint32_t ErrCnt; /*!< Host channel error count. */ + +#if defined (USB_DRD_FS) + uint16_t pmaadress; /*!< PMA Address + This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ + + uint16_t pmaaddr0; /*!< PMA Address0 + This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ + + uint16_t pmaaddr1; /*!< PMA Address1 + This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ + + uint8_t doublebuffer; /*!< Double buffer enable + This parameter can be 0 or 1 */ +#endif /* defined (USB_DRD_FS) */ + + USB_URBStateTypeDef urb_state; /*!< URB state. + This parameter can be any value of @ref USB_URBStateTypeDef */ + + USB_HCStateTypeDef state; /*!< Host Channel state. + This parameter can be any value of @ref USB_HCStateTypeDef */ +} USB_HCTypeDef; +#endif /* defined (HAL_HCD_MODULE_ENABLED) */ + +#if defined (USB_OTG_HS) +typedef USB_ModeTypeDef USB_OTG_ModeTypeDef; +typedef USB_CfgTypeDef USB_OTG_CfgTypeDef; + +#if defined (HAL_PCD_MODULE_ENABLED) +typedef USB_EPTypeDef USB_OTG_EPTypeDef; +#endif /* defined (HAL_PCD_MODULE_ENABLED) */ + +#if defined (HAL_HCD_MODULE_ENABLED) +typedef USB_URBStateTypeDef USB_OTG_URBStateTypeDef; +typedef USB_HCStateTypeDef USB_OTG_HCStateTypeDef; +typedef USB_HCTypeDef USB_OTG_HCTypeDef; +#endif /* defined (HAL_HCD_MODULE_ENABLED) */ +#endif /* defined (USB_OTG_HS) */ + +#if defined (USB_DRD_FS) +typedef USB_ModeTypeDef USB_DRD_ModeTypeDef; +typedef USB_CfgTypeDef USB_DRD_CfgTypeDef; + +#if defined (HAL_PCD_MODULE_ENABLED) +typedef USB_EPTypeDef USB_DRD_EPTypeDef; +#endif /* defined (HAL_PCD_MODULE_ENABLED) */ + +#if defined (HAL_HCD_MODULE_ENABLED) +typedef USB_URBStateTypeDef USB_DRD_URBStateTypeDef; +typedef USB_HCStateTypeDef USB_DRD_HCStateTypeDef; +typedef USB_HCTypeDef USB_DRD_HCTypeDef; +#endif /* defined (HAL_HCD_MODULE_ENABLED) */ +#endif /* defined (USB_DRD_FS) */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup PCD_Exported_Constants PCD Exported Constants + * @{ + */ + +#if defined (USB_OTG_HS) +/** @defgroup USB_OTG_CORE VERSION ID + * @{ + */ +#define USB_OTG_CORE_ID_300A 0x4F54300AU +#define USB_OTG_CORE_ID_310A 0x4F54310AU +/** + * @} + */ + +/** @defgroup USB_Core_Mode_ USB Core Mode + * @{ + */ +#define USB_OTG_MODE_DEVICE 0U +#define USB_OTG_MODE_HOST 1U +#define USB_OTG_MODE_DRD 2U +/** + * @} + */ + +/** @defgroup USB_LL_Core_Speed USB Low Layer Core Speed + * @{ + */ +#define USB_OTG_SPEED_HIGH 0U +#define USB_OTG_SPEED_HIGH_IN_FULL 1U +#define USB_OTG_SPEED_FULL 3U +/** + * @} + */ + +/** @defgroup USB_LL_Core_PHY USB Low Layer Core PHY + * @{ + */ +#define USB_OTG_HS_EMBEDDED_PHY 3U +/** + * @} + */ + +/** @defgroup USB_LL_Turnaround_Timeout Turnaround Timeout Value + * @{ + */ +#ifndef USBD_HS_TRDT_VALUE +#define USBD_HS_TRDT_VALUE 9U +#endif /* USBD_HS_TRDT_VALUE */ +#ifndef USBD_FS_TRDT_VALUE +#define USBD_FS_TRDT_VALUE 5U +#define USBD_DEFAULT_TRDT_VALUE 9U +#endif /* USBD_HS_TRDT_VALUE */ +/** + * @} + */ + +/** @defgroup USB_LL_Core_MPS USB Low Layer Core MPS + * @{ + */ +#define USB_OTG_HS_MAX_PACKET_SIZE 512U +#define USB_OTG_FS_MAX_PACKET_SIZE 64U +#define USB_OTG_MAX_EP0_SIZE 64U +/** + * @} + */ + +/** @defgroup USB_LL_Core_PHY_Frequency USB Low Layer Core PHY Frequency + * @{ + */ +#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0U << 1) +#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1U << 1) +#define DSTS_ENUMSPD_FS_PHY_48MHZ (3U << 1) +/** + * @} + */ + +/** @defgroup USB_LL_CORE_Frame_Interval USB Low Layer Core Frame Interval + * @{ + */ +#define DCFG_FRAME_INTERVAL_80 0U +#define DCFG_FRAME_INTERVAL_85 1U +#define DCFG_FRAME_INTERVAL_90 2U +#define DCFG_FRAME_INTERVAL_95 3U +/** + * @} + */ +#endif /* defined (USB_OTG_HS) */ +/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS + * @{ + */ +#define EP_MPS_64 0U +#define EP_MPS_32 1U +#define EP_MPS_16 2U +#define EP_MPS_8 3U +/** + * @} + */ + +/** @defgroup USB_LL_EP_Type USB Low Layer EP Type + * @{ + */ +#define EP_TYPE_CTRL 0U +#define EP_TYPE_ISOC 1U +#define EP_TYPE_BULK 2U +#define EP_TYPE_INTR 3U +#define EP_TYPE_MSK 3U +/** + * @} + */ + +/** @defgroup USB_LL_EP_Speed USB Low Layer EP Speed + * @{ + */ +#define EP_SPEED_LOW 0U +#define EP_SPEED_FULL 1U +#define EP_SPEED_HIGH 2U +/** + * @} + */ + +/** @defgroup USB_LL_CH_PID_Type USB Low Layer Channel PID Type + * @{ + */ +#define HC_PID_DATA0 0U +#define HC_PID_DATA2 1U +#define HC_PID_DATA1 2U +#define HC_PID_SETUP 3U +/** + * @} + */ + +/** @defgroup USB_LL Device Speed + * @{ + */ +#define USBD_HS_SPEED 0U +#define USBD_HSINFS_SPEED 1U +#define USBH_HS_SPEED 0U +#define USBD_FS_SPEED 2U +#define USBH_FSLS_SPEED 1U +/** + * @} + */ + +#if defined (USB_OTG_HS) +/** @defgroup USB_LL_STS_Defines USB Low Layer STS Defines + * @{ + */ +#define STS_GOUT_NAK 1U +#define STS_DATA_UPDT 2U +#define STS_XFER_COMP 3U +#define STS_SETUP_COMP 4U +#define STS_SETUP_UPDT 6U +/** + * @} + */ + +/** @defgroup USB_LL_HCFG_SPEED_Defines USB Low Layer HCFG Speed Defines + * @{ + */ +#define HCFG_30_60_MHZ 0U +#define HCFG_48_MHZ 1U +#define HCFG_6_MHZ 2U +/** + * @} + */ + +/** @defgroup USB_LL_HFIR_Defines USB Low Layer frame interval Defines + * @{ + */ +#define HFIR_6_MHZ 6000U +#define HFIR_60_MHZ 60000U +#define HFIR_48_MHZ 48000U +/** + * @} + */ + +/** @defgroup USB_LL_HPRT0_PRTSPD_SPEED_Defines USB Low Layer HPRT0 PRTSPD Speed Defines + * @{ + */ +#define HPRT0_PRTSPD_HIGH_SPEED 0U +#define HPRT0_PRTSPD_FULL_SPEED 1U +#define HPRT0_PRTSPD_LOW_SPEED 2U +/** + * @} + */ + +#define HCCHAR_CTRL 0U +#define HCCHAR_ISOC 1U +#define HCCHAR_BULK 2U +#define HCCHAR_INTR 3U + +#define GRXSTS_PKTSTS_IN 2U +#define GRXSTS_PKTSTS_IN_XFER_COMP 3U +#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5U +#define GRXSTS_PKTSTS_CH_HALTED 7U + +#define CLEAR_INTERRUPT_MASK 0xFFFFFFFFU + +#define HC_MAX_PKT_CNT 256U +#define ISO_SPLT_MPS 188U + +#define HCSPLT_BEGIN 1U +#define HCSPLT_MIDDLE 2U +#define HCSPLT_END 3U +#define HCSPLT_FULL 4U + +#define TEST_J 1U +#define TEST_K 2U +#define TEST_SE0_NAK 3U +#define TEST_PACKET 4U +#define TEST_FORCE_EN 5U + +#define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_PCGCCTL_BASE) +#define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_HOST_PORT_BASE) + +#define USBx_DEVICE ((USB_OTG_DeviceTypeDef *)(USBx_BASE + USB_OTG_DEVICE_BASE)) +#define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)(USBx_BASE\ + + USB_OTG_IN_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE))) + +#define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)(USBx_BASE\ + + USB_OTG_OUT_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE))) + +#define USBx_DFIFO(i) *(__IO uint32_t *)(USBx_BASE + USB_OTG_FIFO_BASE + ((i) * USB_OTG_FIFO_SIZE)) + +#define USBx_HOST ((USB_OTG_HostTypeDef *)(USBx_BASE + USB_OTG_HOST_BASE)) +#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)(USBx_BASE\ + + USB_OTG_HOST_CHANNEL_BASE\ + + ((i) * USB_OTG_HOST_CHANNEL_SIZE))) + + +#define EP_ADDR_MSK 0xFU +#endif /* defined (USB_OTG_HS) */ +#if defined (USB_DRD_FS) +#define USB_CHEP_ERRRX USB_CHEP_ERR_RX +#define USB_EP_ERRRX USB_CHEP_ERR_RX +#define USB_CH_ERRRX USB_CHEP_ERR_RX + +#define USB_CHEP_ERRTX USB_CHEP_ERR_TX +#define USB_EP_ERRTX USB_CHEP_ERR_TX +#define USB_CH_ERRTX USB_CHEP_ERR_TX + +#define USB_CHEP_DTOG_RX USB_CHEP_DTOGRX +#define USB_EP_DTOG_RX USB_CHEP_DTOGRX +#define USB_CH_DTOG_RX USB_CHEP_DTOGRX + +#define USB_CHEP_DTOG_TX USB_CHEP_DTOGTX +#define USB_EP_DTOG_TX USB_CHEP_DTOGTX +#define USB_CH_DTOG_TX USB_CHEP_DTOGTX + +#define USB_CHEP_TX_STTX USB_CHEP_STATTX +#define USB_EP_TX_STTX USB_CHEP_STATTX +#define USB_CH_TX_STTX USB_CHEP_STATTX + +#define USB_CHEP_RX_STRX USB_CHEP_STATRX +#define USB_EP_RX_STRX USB_CHEP_STATRX +#define USB_CH_RX_STRX USB_CHEP_STATRX + +#define USB_CHEP_KIND USB_CHEP_EPKIND +#define USB_CHEP_LSEP USB_CHEP_LS_EP +#define USB_CHEP_ADDR USB_CHEP_EA + +#define USB_ISTR_RESET USB_ISTR_RST_DCON +#define USB_ISTR_DCON USB_ISTR_RST_DCON +#define USB_ISTR_LS_DCONN USB_ISTR_LS_DCON + +#define USB_CNTR_RESETM USB_CNTR_RST_DCONM +#define USB_CNTR_DCON USB_CNTR_RST_DCONM + +#define USB_BCDR_DPPD USB_BCDR_DPPU_DPD +#define USB_BCDR_DPPU USB_BCDR_DPPU_DPD +#define USB_LPMCSR_LMPEN USB_LPMCSR_LPMEN + +#define EP_ADDR_MSK 0x7U + +#ifndef USE_USB_DOUBLE_BUFFER +#define USE_USB_DOUBLE_BUFFER 1U +#endif /* USE_USB_DOUBLE_BUFFER */ + +#define USB_EMBEDDED_PHY 2U + +/*!< USB Speed */ +#define USB_DRD_SPEED_FS 1U +#define USB_DRD_SPEED_LS 2U +#define USB_DRD_SPEED_LSFS 3U + +/*!< Channel Direction */ +#define CH_IN_DIR 1U +#define CH_OUT_DIR 0U + +/*!< Number of used channels in the Application */ +#ifndef USB_DRD_USED_CHANNELS +#define USB_DRD_USED_CHANNELS 8U +#endif /* USB_DRD_USED_CHANNELS */ + +/** + * used for USB_HC_DoubleBuffer API + */ +#define USB_DRD_BULK_DBUFF_ENBALE 1U +#define USB_DRD_BULK_DBUFF_DISABLE 2U +#define USB_DRD_ISOC_DBUFF_ENBALE 3U +#define USB_DRD_ISOC_DBUFF_DISABLE 4U + +/* First available address in PMA */ +#define PMA_START_ADDR (0x10U + (8U *(USB_DRD_USED_CHANNELS - 2U))) +#define PMA_END_ADDR USB_DRD_PMA_SIZE + +/* Exported macro ------------------------------------------------------------*/ +/** + * @} + */ +/******************** Bit definition for USB_COUNTn_RX register *************/ +#define USB_CNTRX_NBLK_MSK (0x1FU << 26) +#define USB_CNTRX_BLSIZE (0x1U << 31) + + +/*Set Channel/Endpoint to the USB Register */ +#define USB_DRD_SET_CHEP(USBx, bEpChNum, wRegValue) (*(__IO uint32_t *)\ + (&(USBx)->CHEP0R + (bEpChNum)) = (uint32_t)(wRegValue)) + +/*Get Channel/Endpoint from the USB Register */ +#define USB_DRD_GET_CHEP(USBx, bEpChNum) (*(__IO uint32_t *)(&(USBx)->CHEP0R + (bEpChNum))) + + +/** + * @brief free buffer used from the application realizing it to the line + * toggles bit SW_BUF in the double buffered endpoint register + * @param USBx USB device. + * @param bEpChNum, bDir + * @retval None + */ +#define USB_DRD_FREE_USER_BUFFER(USBx, bEpChNum, bDir) \ + do { \ + if ((bDir) == 0U) \ + { \ + /* OUT double buffered endpoint */ \ + USB_DRD_TX_DTOG((USBx), (bEpChNum)); \ + } \ + else if ((bDir) == 1U) \ + { \ + /* IN double buffered endpoint */ \ + USB_DRD_RX_DTOG((USBx), (bEpChNum)); \ + } \ + } while(0) + + +/** + * @brief Set the Setup bit in the corresponding channel, when a Setup + transaction is needed. + * @param USBx USB device. + * @param bEpChNum + * @retval None + */ +#define USB_DRD_CHEP_TX_SETUP(USBx, bEpChNum) \ + do { \ + uint32_t _wRegVal; \ + \ + _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) ; \ + \ + /* Set Setup bit */ \ + USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wRegVal | USB_CHEP_SETUP)); \ + } while(0) + + +/** + * @brief Clears bit ERR_RX in the Channel register + * @param USBx USB peripheral instance register address. + * @param bChNum Endpoint Number. + * @retval None + */ +#define USB_DRD_CLEAR_CHEP_RX_ERR(USBx, bChNum) \ + do { \ + uint32_t _wRegVal; \ + \ + _wRegVal = USB_DRD_GET_CHEP((USBx), (bChNum)); \ + _wRegVal = (_wRegVal & USB_CHEP_REG_MASK & (~USB_CHEP_ERRRX) & (~USB_CHEP_VTRX)) | \ + (USB_CHEP_VTTX | USB_CHEP_ERRTX); \ + \ + USB_DRD_SET_CHEP((USBx), (bChNum), _wRegVal); \ + } while(0) /* USB_DRD_CLEAR_CHEP_RX_ERR */ + + +/** + * @brief Clears bit ERR_TX in the Channel register + * @param USBx USB peripheral instance register address. + * @param bChNum Endpoint Number. + * @retval None + */ +#define USB_DRD_CLEAR_CHEP_TX_ERR(USBx, bChNum) \ + do { \ + uint32_t _wRegVal; \ + \ + _wRegVal = USB_DRD_GET_CHEP((USBx), (bChNum)); \ + _wRegVal = (_wRegVal & USB_CHEP_REG_MASK & (~USB_CHEP_ERRTX) & (~USB_CHEP_VTTX)) | \ + (USB_CHEP_VTRX|USB_CHEP_ERRRX); \ + \ + USB_DRD_SET_CHEP((USBx), (bChNum), _wRegVal); \ + } while(0) /* USB_DRD_CLEAR_CHEP_TX_ERR */ + + +/** + * @brief sets the status for tx transfer (bits STAT_TX[1:0]). + * @param USBx USB peripheral instance register address. + * @param bEpChNum Endpoint Number. + * @param wState new state + * @retval None + */ +#define USB_DRD_SET_CHEP_TX_STATUS(USBx, bEpChNum, wState) \ + do { \ + uint32_t _wRegVal; \ + \ + _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_CHEP_TX_DTOGMASK; \ + /* toggle first bit ? */ \ + if ((USB_CHEP_TX_DTOG1 & (wState)) != 0U) \ + { \ + _wRegVal ^= USB_CHEP_TX_DTOG1; \ + } \ + /* toggle second bit ? */ \ + if ((USB_CHEP_TX_DTOG2 & (wState)) != 0U) \ + { \ + _wRegVal ^= USB_CHEP_TX_DTOG2; \ + } \ + USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wRegVal | USB_CHEP_VTRX| USB_CHEP_VTTX)); \ + } while(0) /* USB_DRD_SET_CHEP_TX_STATUS */ + + +/** + * @brief sets the status for rx transfer (bits STAT_TX[1:0]) + * @param USBx USB peripheral instance register address. + * @param bEpChNum Endpoint Number. + * @param wState new state + * @retval None + */ +#define USB_DRD_SET_CHEP_RX_STATUS(USBx, bEpChNum, wState) \ + do { \ + uint32_t _wRegVal; \ + \ + _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_CHEP_RX_DTOGMASK; \ + /* toggle first bit ? */ \ + if ((USB_CHEP_RX_DTOG1 & (wState)) != 0U) \ + { \ + _wRegVal ^= USB_CHEP_RX_DTOG1; \ + } \ + /* toggle second bit ? */ \ + if ((USB_CHEP_RX_DTOG2 & (wState)) != 0U) \ + { \ + _wRegVal ^= USB_CHEP_RX_DTOG2; \ + } \ + USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wRegVal | USB_CHEP_VTRX | USB_CHEP_VTTX)); \ + } while(0) /* USB_DRD_SET_CHEP_RX_STATUS */ + + +/** + * @brief gets the status for tx/rx transfer (bits STAT_TX[1:0] + * /STAT_RX[1:0]) + * @param USBx USB peripheral instance register address. + * @param bEpChNum Endpoint Number. + * @retval status + */ +#define USB_DRD_GET_CHEP_TX_STATUS(USBx, bEpChNum) \ + ((uint16_t)USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_DRD_CHEP_TX_STTX) + +#define USB_DRD_GET_CHEP_RX_STATUS(USBx, bEpChNum) \ + ((uint16_t)USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_DRD_CHEP_RX_STRX) + + +/** + * @brief set EP_KIND bit. + * @param USBx USB peripheral instance register address. + * @param bEpChNum Endpoint Number. + * @retval None + */ +#define USB_DRD_SET_CHEP_KIND(USBx, bEpChNum) \ + do { \ + uint32_t _wRegVal; \ + \ + _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_CHEP_REG_MASK; \ + \ + USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wRegVal | USB_CHEP_VTRX | USB_CHEP_VTTX | USB_CHEP_KIND)); \ + } while(0) /* USB_DRD_SET_CHEP_KIND */ + + +/** + * @brief clear EP_KIND bit. + * @param USBx USB peripheral instance register address. + * @param bEpChNum Endpoint Number. + * @retval None + */ +#define USB_DRD_CLEAR_CHEP_KIND(USBx, bEpChNum) \ + do { \ + uint32_t _wRegVal; \ + \ + _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_EP_KIND_MASK; \ + \ + USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wRegVal | USB_CHEP_VTRX | USB_CHEP_VTTX)); \ + } while(0) /* USB_DRD_CLEAR_CHEP_KIND */ + + +/** + * @brief Clears bit CTR_RX / CTR_TX in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpChNum Endpoint Number. + * @retval None + */ +#define USB_DRD_CLEAR_RX_CHEP_CTR(USBx, bEpChNum) \ + do { \ + uint32_t _wRegVal; \ + \ + _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) & (0xFFFF7FFFU & USB_CHEP_REG_MASK); \ + \ + USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wRegVal | USB_CHEP_VTTX)); \ + } while(0) /* USB_CLEAR_RX_CHEP_CTR */ + +#define USB_DRD_CLEAR_TX_CHEP_CTR(USBx, bEpChNum) \ + do { \ + uint32_t _wRegVal; \ + \ + _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) & (0xFFFFFF7FU & USB_CHEP_REG_MASK); \ + \ + USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wRegVal | USB_CHEP_VTRX)); \ + } while(0) /* USB_CLEAR_TX_CHEP_CTR */ + + +/** + * @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpChNum Endpoint Number. + * @retval None + */ +#define USB_DRD_RX_DTOG(USBx, bEpChNum) \ + do { \ + uint32_t _wEPVal; \ + \ + _wEPVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_CHEP_REG_MASK; \ + \ + USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wEPVal | USB_CHEP_VTRX | USB_CHEP_VTTX | USB_CHEP_DTOG_RX)); \ + } while(0) /* USB_DRD_RX_DTOG */ + +#define USB_DRD_TX_DTOG(USBx, bEpChNum) \ + do { \ + uint32_t _wEPVal; \ + \ + _wEPVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_CHEP_REG_MASK; \ + \ + USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wEPVal | USB_CHEP_VTRX | USB_CHEP_VTTX | USB_CHEP_DTOG_TX)); \ + } while(0) /* USB_TX_DTOG */ + + +/** + * @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpChNum Endpoint Number. + * @retval None + */ +#define USB_DRD_CLEAR_RX_DTOG(USBx, bEpChNum) \ + do { \ + uint32_t _wRegVal; \ + \ + _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)); \ + \ + if ((_wRegVal & USB_CHEP_DTOG_RX) != 0U) \ + { \ + USB_DRD_RX_DTOG((USBx), (bEpChNum)); \ + } \ + } while(0) /* USB_DRD_CLEAR_RX_DTOG */ + +#define USB_DRD_CLEAR_TX_DTOG(USBx, bEpChNum) \ + do { \ + uint32_t _wRegVal; \ + \ + _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)); \ + \ + if ((_wRegVal & USB_CHEP_DTOG_TX) != 0U) \ + { \ + USB_DRD_TX_DTOG((USBx), (bEpChNum)); \ + } \ + } while(0) /* USB_DRD_CLEAR_TX_DTOG */ + + +/** + * @brief Sets address in an endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpChNum Endpoint Number. + * @param bAddr Address. + * @retval None + */ +#define USB_DRD_SET_CHEP_ADDRESS(USBx, bEpChNum, bAddr) \ + do { \ + uint32_t _wRegVal; \ + \ + /*Read the USB->CHEPx into _wRegVal, Reset(DTOGRX/STRX/DTOGTX/STTX) and set the EpAddress*/ \ + _wRegVal = (USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_CHEP_REG_MASK) | (bAddr); \ + \ + /*Set _wRegVal in USB->CHEPx and set Transmit/Receive Valid Transfer (x=bEpChNum)*/ \ + USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wRegVal | USB_CHEP_VTRX | USB_CHEP_VTTX)); \ + } while(0) /* USB_DRD_SET_CHEP_ADDRESS */ + + +/* PMA API Buffer Descriptor Management ------------------------------------------------------------*/ +/* Buffer Descriptor Table TXBD0/RXBD0 --- > TXBD7/RXBD7 8 possible descriptor +* The buffer descriptor is located inside the packet buffer memory (USB_PMA_BUFF) +* TXBD [Reserve |Countx| Address_Tx] +* RXBD [BLSIEZ|NUM_Block |CounRx| Address_Rx] */ + +/* Set TX Buffer Descriptor Address Field */ +#define USB_DRD_SET_CHEP_TX_ADDRESS(USBx, bEpChNum, wAddr) \ + do { \ + /* Reset old Address */ \ + (USB_DRD_PMA_BUFF + (bEpChNum))->TXBD &= USB_PMA_TXBD_ADDMSK; \ + \ + /* Bit0 & Bit1 should be =0 PMA must be Word aligned */ \ + (USB_DRD_PMA_BUFF + (bEpChNum))->TXBD |= (uint32_t)(((uint32_t)(wAddr) >> 2U) << 2U); \ + } while(0) /* USB_DRD_SET_CHEP_TX_ADDRESS */ + +/* Set RX Buffer Descriptor Address Field */ +#define USB_DRD_SET_CHEP_RX_ADDRESS(USBx, bEpChNum, wAddr) \ + do { \ + /* Reset old Address */ \ + (USB_DRD_PMA_BUFF + (bEpChNum))->RXBD &= USB_PMA_RXBD_ADDMSK; \ + \ + /* Bit0 & Bit1 should be =0 PMA must be Word aligned */ \ + (USB_DRD_PMA_BUFF + (bEpChNum))->RXBD |= (uint32_t)(((uint32_t)(wAddr) >> 2U) << 2U); \ + } while(0) /* USB_SET_CHEP_RX_ADDRESS */ + + +/** + * @brief Sets counter of rx buffer with no. of blocks. + * @param pdwReg Register pointer + * @param wCount Counter. + * @param wNBlocks no. of Blocks. + * @retval None + */ +#define USB_DRD_CALC_BLK32(pdwReg, wCount, wNBlocks) \ + do { \ + /* Divide PacketSize by 32 to calculate the Nb of Block32 */ \ + (wNBlocks) =((uint32_t)(wCount) >> 5U); \ + if (((uint32_t)(wCount) % 32U) == 0U) \ + { \ + (wNBlocks)--; \ + } \ + \ + (pdwReg)|= (uint32_t)((((wNBlocks) << 26U)) | USB_CNTRX_BLSIZE); \ + } while(0) /* USB_DRD_CALC_BLK32 */ + +#define USB_DRD_CALC_BLK2(pdwReg, wCount, wNBlocks) \ + do { \ + /* Divide PacketSize by 32 to calculate the Nb of Block32 */ \ + (wNBlocks) = (uint32_t)((uint32_t)(wCount) >> 1U); \ + if (((wCount) & 0x1U) != 0U) \ + { \ + (wNBlocks)++; \ + } \ + (pdwReg) |= (uint32_t)((wNBlocks) << 26U); \ + } while(0) /* USB_DRD_CALC_BLK2 */ + +#define USB_DRD_SET_CHEP_CNT_RX_REG(pdwReg, wCount) \ + do { \ + uint32_t wNBlocks; \ + \ + (pdwReg) &= ~(USB_CNTRX_BLSIZE | USB_CNTRX_NBLK_MSK); \ + \ + if ((wCount) == 0U) \ + { \ + (pdwReg) |= USB_CNTRX_BLSIZE; \ + } \ + else if ((wCount) <= 62U) \ + { \ + USB_DRD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \ + } \ + else \ + { \ + USB_DRD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \ + } \ + } while(0) /* USB_DRD_SET_CHEP_CNT_RX_REG */ + + +/** + * @brief sets counter for the tx/rx buffer. + * @param USBx USB peripheral instance register address. + * @param bEpChNum Endpoint Number. + * @param wCount Counter value. + * @retval None + */ +#define USB_DRD_SET_CHEP_TX_CNT(USBx,bEpChNum, wCount) \ + do { \ + /* Reset old TX_Count value */ \ + (USB_DRD_PMA_BUFF + (bEpChNum))->TXBD &= USB_PMA_TXBD_COUNTMSK; \ + \ + /* Set the wCount in the dedicated EP_TXBuffer */ \ + (USB_DRD_PMA_BUFF + (bEpChNum))->TXBD |= (uint32_t)((uint32_t)(wCount) << 16U); \ + } while(0) + +#define USB_DRD_SET_CHEP_RX_DBUF0_CNT(USBx, bEpChNum, wCount) \ + USB_DRD_SET_CHEP_CNT_RX_REG(((USB_DRD_PMA_BUFF + (bEpChNum))->TXBD), (wCount)) + +#define USB_DRD_SET_CHEP_RX_CNT(USBx, bEpChNum, wCount) \ + USB_DRD_SET_CHEP_CNT_RX_REG(((USB_DRD_PMA_BUFF + (bEpChNum))->RXBD), (wCount)) + +/** + * @brief gets counter of the tx buffer. + * @param USBx USB peripheral instance register address. + * @param bEpChNum Endpoint Number. + * @retval Counter value + */ +#define USB_DRD_GET_CHEP_TX_CNT(USBx, bEpChNum) (((USB_DRD_PMA_BUFF + (bEpChNum))->TXBD & 0x03FF0000U) >> 16U) +#define USB_DRD_GET_CHEP_RX_CNT(USBx, bEpChNum) (((USB_DRD_PMA_BUFF + (bEpChNum))->RXBD & 0x03FF0000U) >> 16U) + +#define USB_DRD_GET_EP_TX_CNT USB_GET_CHEP_TX_CNT +#define USB_DRD_GET_CH_TX_CNT USB_GET_CHEP_TX_CNT + +#define USB_DRD_GET_EP_RX_CNT USB_DRD_GET_CHEP_RX_CNT +#define USB_DRD_GET_CH_RX_CNT USB_DRD_GET_CHEP_RX_CNT +/** + * @brief Sets buffer 0/1 address in a double buffer endpoint. + * @param USBx USB peripheral instance register address. + * @param bEpChNum Endpoint Number. + * @param wBuf0Addr buffer 0 address. + * @retval Counter value + */ +#define USB_DRD_SET_CHEP_DBUF0_ADDR(USBx, bEpChNum, wBuf0Addr) \ + USB_DRD_SET_CHEP_TX_ADDRESS((USBx), (bEpChNum), (wBuf0Addr)) + +#define USB_DRD_SET_CHEP_DBUF1_ADDR(USBx, bEpChNum, wBuf1Addr) \ + USB_DRD_SET_CHEP_RX_ADDRESS((USBx), (bEpChNum), (wBuf1Addr)) + + +/** + * @brief Sets addresses in a double buffer endpoint. + * @param USBx USB peripheral instance register address. + * @param bEpChNum Endpoint Number. + * @param wBuf0Addr: buffer 0 address. + * @param wBuf1Addr = buffer 1 address. + * @retval None + */ +#define USB_DRD_SET_CHEP_DBUF_ADDR(USBx, bEpChNum, wBuf0Addr, wBuf1Addr) \ + do { \ + USB_DRD_SET_CHEP_DBUF0_ADDR((USBx), (bEpChNum), (wBuf0Addr)); \ + USB_DRD_SET_CHEP_DBUF1_ADDR((USBx), (bEpChNum), (wBuf1Addr)); \ + } while(0) /* USB_DRD_SET_CHEP_DBUF_ADDR */ + + +/** + * @brief Gets buffer 0/1 address of a double buffer endpoint. + * @param USBx USB peripheral instance register address. + * @param bEpChNum Endpoint Number. + * @param bDir endpoint dir EP_DBUF_OUT = OUT + * EP_DBUF_IN = IN + * @param wCount: Counter value + * @retval None + */ +#define USB_DRD_SET_CHEP_DBUF0_CNT(USBx, bEpChNum, bDir, wCount) \ + do { \ + if ((bDir) == 0U) \ + { \ + /* OUT endpoint */ \ + USB_DRD_SET_CHEP_RX_DBUF0_CNT((USBx), (bEpChNum), (wCount)); \ + } \ + else \ + { \ + if ((bDir) == 1U) \ + { \ + /* IN endpoint */ \ + USB_DRD_SET_CHEP_TX_CNT((USBx), (bEpChNum), (wCount)); \ + } \ + } \ + } while(0) /* USB_DRD_SET_CHEP_DBUF0_CNT */ + +#define USB_DRD_SET_CHEP_DBUF1_CNT(USBx, bEpChNum, bDir, wCount) \ + do { \ + if ((bDir) == 0U) \ + { \ + /* OUT endpoint */ \ + USB_DRD_SET_CHEP_RX_CNT((USBx), (bEpChNum), (wCount)); \ + } \ + else \ + { \ + if ((bDir) == 1U) \ + { \ + /* IN endpoint */ \ + (USB_DRD_PMA_BUFF + (bEpChNum))->RXBD &= USB_PMA_TXBD_COUNTMSK; \ + (USB_DRD_PMA_BUFF + (bEpChNum))->RXBD |= (uint32_t)((uint32_t)(wCount) << 16U); \ + } \ + } \ + } while(0) /* USB_DRD_SET_CHEP_DBUF1_CNT */ + +#define USB_DRD_SET_CHEP_DBUF_CNT(USBx, bEpChNum, bDir, wCount) \ + do { \ + USB_DRD_SET_CHEP_DBUF0_CNT((USBx), (bEpChNum), (bDir), (wCount)); \ + USB_DRD_SET_CHEP_DBUF1_CNT((USBx), (bEpChNum), (bDir), (wCount)); \ + } while(0) /* USB_DRD_SET_EPCH_DBUF_CNT */ + +/** + * @brief Gets buffer 0/1 rx/tx counter for double buffering. + * @param USBx USB peripheral instance register address. + * @param bEpChNum Endpoint Number. + * @retval None + */ +#define USB_DRD_GET_CHEP_DBUF0_CNT(USBx, bEpChNum) (USB_DRD_GET_CHEP_TX_CNT((USBx), (bEpChNum))) +#define USB_DRD_GET_CHEP_DBUF1_CNT(USBx, bEpChNum) (USB_DRD_GET_CHEP_RX_CNT((USBx), (bEpChNum))) +#endif /* defined (USB_DRD_FS) */ +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup USB_LL_Exported_Macros USB Low Layer Exported Macros + * @{ + */ +#if defined (USB_OTG_HS) +#define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__)) +#define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__)) + +#define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__)) +#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__)) +#endif /* defined (USB_OTG_HS) */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup USB_LL_Exported_Functions USB Low Layer Exported Functions + * @{ + */ +#if defined (USB_OTG_HS) +HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg); +HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg); +HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, uint32_t hclk, uint8_t speed); +HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode); +HAL_StatusTypeDef USB_SetDevSpeed(const USB_OTG_GlobalTypeDef *USBx, uint8_t speed); +HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num); + +#if defined (HAL_PCD_MODULE_ENABLED) +HAL_StatusTypeDef USB_ActivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_DeactivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_EPSetStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_EPClearStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma); +HAL_StatusTypeDef USB_EPStopXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); +#endif /* defined (HAL_PCD_MODULE_ENABLED) */ + +HAL_StatusTypeDef USB_WritePacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *src, + uint8_t ch_ep_num, uint16_t len, uint8_t dma); + +void *USB_ReadPacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len); + +HAL_StatusTypeDef USB_SetDevAddress(const USB_OTG_GlobalTypeDef *USBx, uint8_t address); +HAL_StatusTypeDef USB_DevConnect(const USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_DevDisconnect(const USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_ActivateSetup(const USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_EP0_OutStart(const USB_OTG_GlobalTypeDef *USBx, uint8_t dma, const uint8_t *psetup); +uint8_t USB_GetDevSpeed(const USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef const *USBx); +uint32_t USB_ReadChInterrupts(const USB_OTG_GlobalTypeDef *USBx, uint8_t chnum); +uint32_t USB_ReadDevAllOutEpInterrupt(const USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_ReadDevOutEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum); +uint32_t USB_ReadDevAllInEpInterrupt(const USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_ReadDevInEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum); +void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt); +HAL_StatusTypeDef USB_InitFSLSPClkSel(const USB_OTG_GlobalTypeDef *USBx, uint8_t freq); + +HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg); +HAL_StatusTypeDef USB_ResetPort(const USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_DriveVbus(const USB_OTG_GlobalTypeDef *USBx, uint8_t state); +uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef const *USBx); +uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef const *USBx); +HAL_StatusTypeDef USB_DoPing(const USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num); +HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx); + +#if defined (HAL_HCD_MODULE_ENABLED) +HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, + uint8_t epnum, uint8_t dev_address, uint8_t speed, + uint8_t ep_type, uint16_t mps); +HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, + USB_OTG_HCTypeDef *hc, uint8_t dma); + +uint32_t USB_HC_ReadInterrupt(const USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_HC_Halt(const USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num); +HAL_StatusTypeDef USB_HC_Activate(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, uint8_t ch_dir); +#endif /* defined (HAL_HCD_MODULE_ENABLED) */ + +HAL_StatusTypeDef USB_ActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_DeActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx); +#endif /* defined (USB_OTG_HS) */ + +#if defined (USB_DRD_FS) +HAL_StatusTypeDef USB_CoreInit(USB_DRD_TypeDef *USBx, USB_DRD_CfgTypeDef cfg); +HAL_StatusTypeDef USB_DevInit(USB_DRD_TypeDef *USBx, USB_DRD_CfgTypeDef cfg); +HAL_StatusTypeDef USB_EnableGlobalInt(USB_DRD_TypeDef *USBx); +HAL_StatusTypeDef USB_DisableGlobalInt(USB_DRD_TypeDef *USBx); +HAL_StatusTypeDef USB_SetCurrentMode(USB_DRD_TypeDef *USBx, USB_DRD_ModeTypeDef mode); + +HAL_StatusTypeDef USB_FlushRxFifo(USB_DRD_TypeDef const *USBx); +HAL_StatusTypeDef USB_FlushTxFifo(USB_DRD_TypeDef const *USBx, uint32_t num); + +#if defined (HAL_PCD_MODULE_ENABLED) +HAL_StatusTypeDef USB_ActivateEndpoint(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep); +HAL_StatusTypeDef USB_DeactivateEndpoint(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep); +HAL_StatusTypeDef USB_EPStartXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep); +HAL_StatusTypeDef USB_EPSetStall(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep); +HAL_StatusTypeDef USB_EPClearStall(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep); +HAL_StatusTypeDef USB_EPStopXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep); +#endif /* defined (HAL_PCD_MODULE_ENABLED) */ + +HAL_StatusTypeDef USB_SetDevAddress(USB_DRD_TypeDef *USBx, uint8_t address); +HAL_StatusTypeDef USB_DevConnect(USB_DRD_TypeDef *USBx); +HAL_StatusTypeDef USB_DevDisconnect(USB_DRD_TypeDef *USBx); +HAL_StatusTypeDef USB_StopDevice(USB_DRD_TypeDef *USBx); +uint32_t USB_ReadInterrupts(USB_DRD_TypeDef const *USBx); + +HAL_StatusTypeDef USB_ResetPort(USB_DRD_TypeDef *USBx); +HAL_StatusTypeDef USB_HostInit(USB_DRD_TypeDef *USBx, USB_DRD_CfgTypeDef cfg); + +#if defined (HAL_HCD_MODULE_ENABLED) +HAL_StatusTypeDef USB_HC_IN_Halt(USB_DRD_TypeDef *USBx, uint8_t phy_ch); +HAL_StatusTypeDef USB_HC_OUT_Halt(USB_DRD_TypeDef *USBx, uint8_t phy_ch); +HAL_StatusTypeDef USB_HC_StartXfer(USB_DRD_TypeDef *USBx, USB_DRD_HCTypeDef *hc); +HAL_StatusTypeDef USB_HC_DoubleBuffer(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num, uint8_t db_state); +HAL_StatusTypeDef USB_HC_Init(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num, uint8_t epnum, + uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps); + +HAL_StatusTypeDef USB_HC_Activate(USB_DRD_TypeDef *USBx, uint8_t ch_num, uint8_t ch_dir); +#endif /* defined (HAL_HCD_MODULE_ENABLED) */ + +uint32_t USB_GetHostSpeed(USB_DRD_TypeDef const *USBx); +uint32_t USB_GetCurrentFrame(USB_DRD_TypeDef const *USBx); +HAL_StatusTypeDef USB_StopHost(USB_DRD_TypeDef *USBx); + +HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_DRD_TypeDef *USBx); +HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_DRD_TypeDef *USBx); + +void USB_WritePMA(USB_DRD_TypeDef const *USBx, uint8_t *pbUsrBuf, + uint16_t wPMABufAddr, uint16_t wNBytes); + +void USB_ReadPMA(USB_DRD_TypeDef const *USBx, uint8_t *pbUsrBuf, + uint16_t wPMABufAddr, uint16_t wNBytes); +#endif /* defined (USB_DRD_FS) */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* defined (USB_OTG_HS) || defined (USB_DRD_FS) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32WBAxx_LL_USB_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_utils.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_utils.h index e03d562351..57c89d3183 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_utils.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_utils.h @@ -163,6 +163,15 @@ typedef struct #define LL_UTILS_PACKAGETYPE_WLCSP41_SMPS 0x00000009U /*!< WLCSP41 with internal SMPS package type */ #define LL_UTILS_PACKAGETYPE_UFQFPN48_SMPS 0x0000000AU /*!< UFQFPN48 with internal SMPS package type */ #define LL_UTILS_PACKAGETYPE_UFBGA59 0x0000000BU /*!< UFBGA59 package type */ +#elif defined(STM32WBA62xx) || defined(STM32WBA63xx) || defined(STM32WBA64xx) || defined(STM32WBA65xx) || defined (STM32WBA6Mxx) +#define LL_UTILS_PACKAGETYPE_UFQFPN48_USB 0x00000003U /*!< UFQFPN48 with USB package type */ +#define LL_UTILS_PACKAGETYPE_WLCSP88_USB 0x00000005U /*!< WLSCP88 with USB package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA121_USB 0x00000007U /*!< UFBGA121 with USB package type */ +#define LL_UTILS_PACKAGETYPE_UFQFPN48_SMPS 0x0000000AU /*!< UFQFPN48 with internal SMPS package type */ +#define LL_UTILS_PACKAGETYPE_UFQFPN48_SMPS_USB 0x0000000BU /*!< UFQFPN48 with internal SMPS and USB package type */ +#define LL_UTILS_PACKAGETYPE_VFQFPN68_SMPS_USB 0x0000000CU /*!< VFQFPN68 with internal SMPS and USB package type */ +#define LL_UTILS_PACKAGETYPE_WLCSP88_SMPS_USB 0x0000000DU /*!< WLCSP88 with internal SMPS and USB package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA121_SMPS_USB 0x0000000FU /*!< UFBGA121 with internal SMPS and USB package type */ #endif /* defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) || defined(STM32WBA5Mxx) */ /** * @} @@ -230,6 +239,15 @@ __STATIC_INLINE uint32_t LL_GetFlashSize(void) * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP41_SMPS * @arg @ref LL_UTILS_PACKAGETYPE_UFQFPN48_SMPS * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA59 +#elif defined(STM32WBA62xx) || defined(STM32WBA63xx) || defined(STM32WBA64xx) || defined(STM32WBA65xx) || defined (STM32WBA6Mxx) + * @arg @ref LL_UTILS_PACKAGETYPE_UFQFPN48_USB + * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP88_USB + * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA121_USB + * @arg @ref LL_UTILS_PACKAGETYPE_UFQFPN48_SMPS + * @arg @ref LL_UTILS_PACKAGETYPE_UFQFPN48_SMPS_USB + * @arg @ref LL_UTILS_PACKAGETYPE_VFQFPN68_SMPS_USB + * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP88_SMPS_USB + * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA121_SMPS_USB #endif */ __STATIC_INLINE uint32_t LL_GetPackageType(void) diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/README.md b/system/Drivers/STM32WBAxx_HAL_Driver/README.md index b52ced71dd..7b4f5f9dc6 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/README.md +++ b/system/Drivers/STM32WBAxx_HAL_Driver/README.md @@ -9,7 +9,7 @@ **STM32Cube** covers the overall STM32 products portfolio. It includes a comprehensive embedded software platform delivered for each STM32 series. * The CMSIS modules (core and device) corresponding to the ARM(tm) core implemented in this STM32 product. * The STM32 HAL-LL drivers, an abstraction layer offering a set of APIs ensuring maximized portability across the STM32 portfolio. - * The BSP drivers of each evaluation, demonstration, or nucleo board provided for this STM32 series. + * The BSP drivers of each evaluation, discovery, or nucleo board provided for this STM32 series. * A consistent set of middleware libraries such as WPAN, ThreadX, FileX, USBX, NetDuoX, OpenBootloader, trustedfirmware, mbed-crypto... * A full set of software projects (basic examples, applications, and demonstrations) for each board, each project developed in three flavors using three toolchains (EWARM, MDK-ARM, and STM32CubeIDE). diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Release_Notes.html b/system/Drivers/STM32WBAxx_HAL_Driver/Release_Notes.html index e3943b7be0..fcb8816140 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Release_Notes.html +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Release_Notes.html @@ -5,16 +5,24 @@ Release Notes for STM32WBAxx HAL Drivers - - @@ -23,41 +31,445 @@

Release Notes for

STM32WBAxx HAL Drivers

-

Copyright © 2022 STMicroelectronics

- +

Copyright © 2022-2025 STMicroelectronics

+

Purpose

-

The STM32Cube HAL and LL, an STM32 abstraction layer embedded software, ensure maximized portability across STM32 portfolio.

-

The portable APIs layer provides a generic, multi instanced and simple set of APIs to interact with the upper layer (application, libraries and stacks). It is composed of native and extended APIs set. It is directly built around a generic architecture and allows the build-upon layers, like the middleware layer, to implement its functions without knowing in-depth the used STM32 device. This improves the library code reusability and guarantees an easy portability on other devices and STM32 families.

-

The Low Layer (LL) drivers are part of the STM32Cube firmware HAL that provides a basic set of optimized and one shot services. The Low layer drivers, contrary to the HAL ones are not fully portable across the STM32 families; the availability of some functions depends on the physical availability of the relative features on the product. The Low Layer (LL) drivers are designed to offer the following features:

-
    -
  • New set of inline functions for direct and atomic register access
    • -
  • One-shot operations that can be used by the HAL drivers or from application level
    • -
  • Full independence from HAL and standalone usage (without HAL drivers)
    • +

    The STM32Cube HAL and LL, an STM32 abstraction layer embedded +software, ensure maximized portability across STM32 portfolio.

    +

    The portable APIs layer provides a generic, multi instanced and +simple set of APIs to interact with the upper layer (application, +libraries and stacks). It is composed of native and extended APIs set. +It is directly built around a generic architecture and allows the +build-upon layers, like the middleware layer, to implement its functions +without knowing in-depth the used STM32 device. This improves the +library code reusability and guarantees an easy portability on other +devices and STM32 families.

    +

    The Low Layer (LL) drivers are part of the STM32Cube firmware HAL +that provides a basic set of optimized and one shot services. The Low +layer drivers, contrary to the HAL ones are not fully portable across +the STM32 families; the availability of some functions depends on the +physical availability of the relative features on the product. The Low +Layer (LL) drivers are designed to offer the following features:

    +
      +
    • New set of inline functions for direct and atomic register +access
      • +
    • One-shot operations that can be used by the HAL drivers or from +application level
      • +
    • Full independence from HAL and standalone usage (without HAL +drivers)
    • Full features coverage of all the supported peripherals
    -
    -

    Update History

    +
    +

    Update History

    - + +

    Main Changes

    -

    Official Release of STM32CubeWBA Firmware package supporting STM32WBA50xx, STM32WBA52xx, STM32WBA54xx, STM32WBA55xx and STM32WBA5Mxx devices

    +

    Official +Release of STM32CubeWBA Firmware package supporting +STM32WBA5x and STM32WBA6x devices

    Contents

    -

    Official Release of HAL/LL Drivers for STM32WBAxx serie

    +

    Official +Release of HAL/LL Drivers for +STM32WBAxx serie

    • HAL/LL Drivers are available for all peripherals:
        -
      • HAL: ADC, COMP, CORTEX, CRC, CRYP, DMA, EXTI, FLASH, GPIO, GTZC, HASH, HSEM, I2C, ICACHE, IRDA, IWDG, LPTIM, PKA, PWR, RAMCFG, RCC, RNG, RTC, SAI, SMARTCARD, SMBUS, SPI, TIM, TSC, UART, USART, WWDG
        • -
      • LL: ADC, BUS, COMP, CORTEX, CRC, DMA, EXTI, GPIO, HSEM, I2C, ICACHE, IWDG, LPTIM, LPUART, PKA, PWR, RCC, RNG, RTC, SPI, SYSTEM, TIM, USART, UTILS, WWDG
        • +
      • HAL: ADC, COMP, CORTEX, CRC, CRYP, DMA, EXTI, +FLASH, GPIO, GTZC, HASH, HCD, HSEM, I2C, ICACHE, IRDA, IWDG, LPTIM, PCD, +PKA, PWR, RAMCFG, RCC, RNG, RTC, SAI, SMARTCARD, SMBUS, SPI, TIM, TSC, +UART, USART, WWDG
        • +
      • LL: ADC, BUS, COMP, CORTEX, CRC, DMA, EXTI, GPIO, +HSEM, I2C, ICACHE, IWDG, LPTIM, LPUART, PKA, PWR, RCC, RNG, RTC, SPI, +SYSTEM, TIM, USART, USB, UTILS, WWDG
      • -
    • Update HAL/LL drivers to include latest corrections
      • +
    • Update HAL/LL drivers to support of STM32WBA6Mxx +devices


    HAL Drivers updates

      +
    • HAL CORTEX driver +
        +
      • Correct management of HSI/4 as source clock for Systick when +available on devices
        • +
      • +
    • HAL CRYP driver +
        +
      • MISRA-C 2012 warnings correction due to IAR version change
        • +
      • +
    • HAL DMA driver +
        +
      • MISRA-C 2012 warnings correction due to IAR version change
        • +
      • +
    • HAL EXTI driver +
        +
      • MISRA-C 2012 warnings correction due to IAR version change
        • +
      • +
    • HAL FLASH driver +
        +
      • MISRA-C 2012 warnings correction due to IAR version change
        • +
      • Correct timeout management during flag waiting period
        • +
      • +
    • HAL GENERIC driver +
        +
      • MISRA-C 2012 warnings correction due to IAR version change
        • +
      • Correct management of HSI/4 as source clock for Systick when +available on devices
        • +
      • Timebase timer template : update to register the callback function +before to start a timer activity
        • +
      • +
    • HAL GPIO driver +
        +
      • Add STM32WBA6M device
        • +
      • Add missing alternate function defines
        • +
      • +
    • HAL GTZC driver +
        +
      • Add STM32WBA6M device
        • +
      • MISRA-C 2012 warnings correction due to IAR version change
        • +
      • +
    • HAL I2C driver +
        +
      • MISRA-C 2012 warnings correction due to IAR version change
        • +
      • +
    • HAL ICACHE driver +
        +
      • MISRA-C 2012 warnings correction due to IAR version change
        • +
      • +
    • HAL PWR driver +
        +
      • Add STM32WBA6M device
        • +
      • +
    • HAL RCC driver +
        +
      • Add STM32WBA6M device
        • +
      • MISRA-C 2012 warnings correction due to IAR version change
        • +
      • Correct management of HSI/4 as source clock for Systick when +available on devices
        • +
      • +
    • HAL SAI driver +
        +
      • Add STM32WBA6M device
        • +
      • MISRA-C 2012 warnings correction due to IAR version change
        • +
      • +
    • HAL SMARTCARD driver +
        +
      • MISRA-C 2012 warnings correction due to IAR version change
        • +
      • +
    • HAL SMBUS driver +
        +
      • MISRA-C 2012 warnings correction due to IAR version change
        • +
      • +
    • HAL SPI driver +
        +
      • MISRA-C 2012 warnings correction due to IAR version change
        • +
      • +
    • HAL TIM driver +
        +
      • Update TIM_CCER_CCxE_MASK to support internal TIM Channel5 and TIM +Channel6.
        • +
      • Fix update flag (UIF) clearing in TIM_Base_SetConfig.
        • +
      • Include Dithering mode in IS_TIM_PERIOD macro.
        • +
      • +
    • HAL USART driver +
        +
      • MISRA-C 2012 warnings correction due to IAR version change
        • +
      • +
    +


    +

    +

    LL Drivers updates

    +
      +
    • LL ADC driver +
        +
      • Add STM32WBA6M device
        • +
      • Add constant qualifier to ADC calibration addresses
        • +
      • +
    • LL COMP driver +
        +
      • MISRA-C 2012 warnings correction due to IAR version change
        • +
      • +
    • LL CORTEX driver +
        +
      • MISRA-C 2012 warnings correction due to IAR version change
        • +
      • +
    • LL DMA driver +
        +
      • Fix re-definition of port for porting purpose
        • +
      • +
    • LL GPIO driver +
        +
      • Add STM32WBA6M device
        • +
      • +
    • LL LPTIM driver +
        +
      • MISRA-C 2012 warnings correction due to IAR version change
        • +
      • +
    • LL TIM driver +
        +
      • MISRA-C 2012 warnings correction due to IAR version change
        • +
      • +
    • LL UTILS driver +
        +
      • Add STM32WBA6M device
        • +
      • +
    +


    +

    +

    Supported Devices and boards

    +
      +
    • STM32WBA50xx, STM32WBA52xx, STM32WBA54xx, STM32WBA55xx and +STM32WBA5Mxx devices
      • +
    • STM32WBA62xx, STM32WBA63xx, STM32WBA64xx, STM32WBA65xx and +STM32WBA6Mxx devices
      • +
    • NUCLEO-WBA55CG, STM32WBA55G-DK1 and B-WBA5M-WPAN boards
      • +
    • NUCLEO-WBA65RI and STM32WBA65I-DK1 board
      • +
    +

    Backward compatibility

    +
      +
    • Not applicable
      • +
    +

    Known Limitations

    +
      +
    • None
      • +
    +

    Dependencies

    +
      +
    • None
      • +
    +

    Notes

    +
      +
    • None
      • +
    +
    +
    +
    + + +
    +

    Main Changes

    +

    Official +Release of STM32CubeWBA Firmware package supporting +STM32WBA5x and STM32WBA6x devices

    +

    Contents

    +

    Official +Release of HAL/LL Drivers for +STM32WBAxx serie

    +
      +
    • HAL/LL Drivers are available for all peripherals: +
        +
      • HAL: ADC, COMP, CORTEX, CRC, CRYP, DMA, EXTI, +FLASH, GPIO, GTZC, HASH, HCD, HSEM, I2C, ICACHE, IRDA, +IWDG, LPTIM, PCD, PKA, PWR, RAMCFG, RCC, RNG, RTC, SAI, +SMARTCARD, SMBUS, SPI, TIM, TSC, UART, USART, WWDG
        • +
      • LL: ADC, BUS, COMP, CORTEX, CRC, DMA, EXTI, GPIO, +HSEM, I2C, ICACHE, IWDG, LPTIM, LPUART, PKA, PWR, RCC, RNG, RTC, SPI, +SYSTEM, TIM, USART, USB, UTILS, WWDG
        • +
      • +
    • Update HAL/LL drivers to include latest corrections
      • +
    +


    +

    +

    HAL Drivers updates

    +
      +
    • HAL CRYP driver +
        +
      • Better performance by removing multiple volatile reads or writes in +interrupt handler
        • +
      • Correction of MISRA warnings
        • +
      • Check the busy flag before writing CR register
        • +
      • Update to use correctly the wrapped key in decryption mode
        • +
      • Correction of Coverity warnings
        • +
      • +
    • HAL RNG driver +
        +
      • Distinguish error coming from RecoverSeedError or from +SeedError
        • +
      • +
    • HAL UART driver +
        +
      • Fix Doxygen issues for User Manual generation
        • +
      • +
    +


    +

    +

    LL Drivers updates

    +
      +
    • None
      • +
    +


    +

    +

    Supported Devices and +boards

    +
      +
    • STM32WBA50xx, STM32WBA52xx, STM32WBA54xx, STM32WBA55xx and +STM32WBA5Mxx devices
      • +
    • STM32WBA62xx, STM32WBA63xx, STM32WBA64xx and STM32WBA65xx +devices
      • +
    • NUCLEO-WBA55CG, STM32WBA55G-DK1 and B-WBA5M-WPAN boards
      • +
    • NUCLEO-WBA65RI and STM32WBA65I-DK1 board
      • +
    +

    Backward compatibility

    +
      +
    • Not applicable
      • +
    +

    Known Limitations

    +
      +
    • None
      • +
    +

    Dependencies

    +
      +
    • None
      • +
    +

    Notes

    +
      +
    • None
      • +
    +
    +
    +
    + + +
    +

    Main Changes

    +

    Official +Release of STM32CubeWBA Firmware package supporting +STM32WBA5x and STM32WBA6x devices

    +

    Contents

    +

    Official +Release of HAL/LL Drivers for +STM32WBAxx serie

    +
      +
    • HAL/LL Drivers are available for all peripherals: +
        +
      • HAL: ADC, COMP, CORTEX, CRC, CRYP, DMA, EXTI, +FLASH, GPIO, GTZC, HASH, HCD, HSEM, I2C, ICACHE, IRDA, +IWDG, LPTIM, PCD, PKA, PWR, RAMCFG, RCC, RNG, RTC, SAI, +SMARTCARD, SMBUS, SPI, TIM, TSC, UART, USART, WWDG
        • +
      • LL: ADC, BUS, COMP, CORTEX, CRC, DMA, EXTI, GPIO, +HSEM, I2C, ICACHE, IWDG, LPTIM, LPUART, PKA, PWR, RCC, RNG, RTC, SPI, +SYSTEM, TIM, USART, USB, UTILS, WWDG
        • +
      • +
    • Update HAL/LL drivers to support of STM32WBA6xxx +devices
      • +
    +


    +

    +

    HAL Drivers updates

    +
      +
    • HAL ADC driver +
        +
      • Update the DMA data length management implementation according to +source/destination width
        • +
      • +
    • HAL DMA driver +
        +
      • DMA Callbacks to be initialized to NULL in RESET state
        • +
      • Remove extra unused parentheses in HAL_DMA_IRQHandler
        • +
      • Fix Doxygen issues for User Manual generation
        • +
      • Fix GCC13 warning
        • +
      • +
    • HAL GPIO driver +
        +
      • Add pull-down capability in analog mode
        • +
      • +
    • HAL HSEM driver +
        +
      • Fix Doxygen issues for User Manual generation
        • +
      • +
    • HAL RCC driver +
        +
      • Fix Doxygen issues for User Manual generation
        • +
      • +
    +


    +

    +

    LL Drivers updates

    +
      +
    • LL LPTIM driver +
        +
      • Fixed LL_LPTIM_CC_SetChannelMode to manage properly on the fly +channel mode changes.
        • +
      • +
    +


    +

    +

    Supported Devices and +boards

    +
      +
    • STM32WBA50xx, STM32WBA52xx, STM32WBA54xx, STM32WBA55xx and +STM32WBA5Mxx devices
      • +
    • STM32WBA62xx, STM32WBA63xx, STM32WBA64xx and STM32WBA65xx +devices
      • +
    • NUCLEO-WBA55CG, STM32WBA55G-DK1 and B-WBA5M-WPAN boards
      • +
    • NUCLEO-WBA65RI and STM32WBA65I-DK1 board
      • +
    +

    Backward compatibility

    +
      +
    • Not applicable
      • +
    +

    Known Limitations

    +
      +
    • None
      • +
    +

    Dependencies

    +
      +
    • None
      • +
    +

    Notes

    +
      +
    • None
      • +
    +
    +
    +
    + + +
    +

    Main Changes

    +

    Official +Release of STM32CubeWBA Firmware package supporting +STM32WBA50xx, STM32WBA52xx, +STM32WBA54xx, STM32WBA55xx and +STM32WBA5Mxx devices

    +

    Contents

    +

    Official +Release of HAL/LL Drivers for +STM32WBAxx serie

    +
      +
    • HAL/LL Drivers are available for all peripherals: +
        +
      • HAL: ADC, COMP, CORTEX, CRC, CRYP, DMA, EXTI, +FLASH, GPIO, GTZC, HASH, HSEM, I2C, ICACHE, IRDA, IWDG, LPTIM, PKA, PWR, +RAMCFG, RCC, RNG, RTC, SAI, SMARTCARD, SMBUS, SPI, TIM, TSC, UART, +USART, WWDG
        • +
      • LL: ADC, BUS, COMP, CORTEX, CRC, DMA, EXTI, GPIO, +HSEM, I2C, ICACHE, IWDG, LPTIM, LPUART, PKA, PWR, RCC, RNG, RTC, SPI, +SYSTEM, TIM, USART, UTILS, WWDG
        • +
      • +
    • Update HAL/LL drivers to include latest corrections
      • +
    +


    +

    +

    HAL Drivers updates

    +
    • HAL COMP driver
      • Add power modes intermediate and ultra low power
        • @@ -65,7 +477,8 @@

        HAL Drivers updates

      • HAL DMA driver
        • Add a reset of a node of a linked list
          • -
        • Remove unused code related to 2D addressing as no 2D addressing in this family
          • +
        • Remove unused code related to 2D addressing as no 2D addressing in +this family
      • HAL GPIO driver
          @@ -77,8 +490,10 @@

          HAL Drivers updates

      • HAL I2C driver
          -
        • Move variable tmp declaration at the beginning in I2C_TransferCofig function
          • -
        • Update function HAL_I2C_IsDeviceReady() to take into account the number of trials
          • +
        • Move variable tmp declaration at the beginning in I2C_TransferCofig +function
          • +
        • Update function HAL_I2C_IsDeviceReady() to take into account the +number of trials
      • HAL LPTIM driver
          @@ -88,12 +503,14 @@

          HAL Drivers updates

        • HAL PKA driver
          • SAES decryption fails after PKA deinitialization
            • -
          • Remove static global variables and add them to PKA handle to be compliant with HAL coding rules
            • +
          • Remove static global variables and add them to PKA handle to be +compliant with HAL coding rules
          • Add check for MontgomeryParam not equal to null
        • HAL PWR driver
            -
          • Reorganization of IS_PWR_WAKEUP_PIN macro in order to ease maintenance and declaration conditionned on CMSIS
            • +
          • Reorganization of IS_PWR_WAKEUP_PIN macro in order to ease +maintenance and declaration conditionned on CMSIS
          • Add WBA5M device
          • Guidance added for HAL_PWR_ConfigAttributes() API calls
          • @@ -105,7 +522,8 @@

          HAL Drivers updates

          • Add WBA5M device
          • Guidance added for HAL_RCC_ConfigAttributes() API calls
            • -
          • Add missing @arg for RCC_IT_CSS function headers
            • +
          • Add missing @arg for +RCC_IT_CSS function headers
        • HAL RNG driver
            @@ -117,12 +535,13 @@

            HAL Drivers updates

        • HAL UART driver
            -
          • Correct DMA Rx abort procedure impact on ongoing Tx transfer in polling mode
            • +
          • Correct DMA Rx abort procedure impact on ongoing Tx transfer in +polling mode


        -

        LL Drivers updates

        +

        LL Drivers updates

        • LL ADC driver
            @@ -155,47 +574,63 @@

            LL Drivers updates


          -

          Supported Devices and boards

          +

          Supported Devices and +boards

            -
          • STM32WBA50xx, STM32WBA52xx, STM32WBA54xx, STM32WBA55xx and STM32WBA5Mxx devices
            • +
          • STM32WBA50xx, STM32WBA52xx, STM32WBA54xx, STM32WBA55xx and +STM32WBA5Mxx devices
          • NUCLEO-WBA55CG, STM32WBA55G-DK1 and b-WBA5M-WPAN boards
          -

          Backward compatibility

          +

          Backward compatibility

          • Not applicable
          -

          Known Limitations

          +

          Known Limitations

          • None
          -

          Dependencies

          +

          Dependencies

          • None
          -

          Notes

          +

          Notes

          • None
    - + +
    -

    Main Changes

    -

    Official Release of STM32CubeWBA Firmware package supporting STM32WBA50xx, STM32WBA52xx, STM32WBA54xx and STM32WBA55xx devices

    -

    Contents

    -

    Official Release of HAL/LL Drivers for STM32WBAxx serie

    +

    Main Changes

    +

    Official +Release of STM32CubeWBA Firmware package supporting +STM32WBA50xx, STM32WBA52xx, +STM32WBA54xx and STM32WBA55xx +devices

    +

    Contents

    +

    Official +Release of HAL/LL Drivers for +STM32WBAxx serie

    • HAL/LL Drivers are available for all peripherals:
        -
      • HAL: ADC, COMP, CORTEX, CRC, CRYP, DMA, EXTI, FLASH, GPIO, GTZC, HASH, HSEM, I2C, ICACHE, IRDA, IWDG, LPTIM, PKA, PWR, RAMCFG, RCC, RNG, RTC, SAI, SMARTCARD, SMBUS, SPI, TIM, TSC, UART, USART, WWDG
        • -
      • LL: ADC, COMP, CRC, DMA, EXTI, GPIO, I2C, ICACHE, LPTIM, LPUART, PKA, PWR, RCC, RNG, RTC, SPI, TIM, USART, UTILS
        • +
      • HAL: ADC, COMP, CORTEX, CRC, CRYP, DMA, EXTI, +FLASH, GPIO, GTZC, HASH, HSEM, I2C, ICACHE, IRDA, IWDG, LPTIM, PKA, PWR, +RAMCFG, RCC, RNG, RTC, SAI, SMARTCARD, SMBUS, SPI, TIM, TSC, UART, +USART, WWDG
        • +
      • LL: ADC, COMP, CRC, DMA, EXTI, GPIO, I2C, ICACHE, +LPTIM, LPUART, PKA, PWR, RCC, RNG, RTC, SPI, TIM, USART, UTILS
    • Update HAL/LL drivers to include latest corrections


    -

    HAL Drivers updates

    +

    HAL Drivers updates

    • HAL CORTEX driver
        @@ -222,24 +657,30 @@

        HAL Drivers updates

    • HAL UART driver
        -
      • Add HAL_UART_RXEVENT_IDLE event notification to user in case of HAL_UARTEx_ReceiveToIdle_DMA() use with Circular DMA, even if occurring just after TC event.
        • +
      • Add HAL_UART_RXEVENT_IDLE event notification to user in case of +HAL_UARTEx_ReceiveToIdle_DMA() use with Circular DMA, even if occurring +just after TC event.
      • Correct wrong comment in HAL_UARTEx_DisableFifoMode() function
        • -
      • Align prescaler value used by default in UART_GET_DIV_FACTOR macro with RM.
        • +
      • Align prescaler value used by default in UART_GET_DIV_FACTOR macro +with RM.
    • HAL USART driver
        -
      • Improve the visibility of the SPI function support in HAL USART description and comments.
        • +
      • Improve the visibility of the SPI function support in HAL USART +description and comments.
      • Correct wrong comment in HAL_USARTEx_DisableFifoMode() function
        • -
      • Align prescaler value used by default in USART_GET_DIV_FACTOR macro with RM.
        • +
      • Align prescaler value used by default in USART_GET_DIV_FACTOR macro +with RM.


    -

    LL Drivers updates

    +

    LL Drivers updates

    • LL CORTEX driver
        -
      • Remove duplicate write of attributes in LL_MPU_ConfigRegion() function
        • +
      • Remove duplicate write of attributes in LL_MPU_ConfigRegion() +function
      • Add how to use MPU attributes
    • LL EXTI driver @@ -248,7 +689,8 @@

      LL Drivers updates

  • LL HSEM driver
      -
    • Update LL HSEM description and define to be aligned with the correct number of semaphores
      • +
    • Update LL HSEM description and define to be aligned with the correct +number of semaphores
  • LL RNG driver
      @@ -263,47 +705,62 @@

      LL Drivers updates


    -

    Supported Devices and boards

    +

    Supported Devices and +boards

      -
    • STM32WBA50xx, STM32WBA52xx, STM32WBA54xx and STM32WBA55xx devices
      • +
    • STM32WBA50xx, STM32WBA52xx, STM32WBA54xx and STM32WBA55xx +devices
    • NUCLEO-WBA52CG, NUCLEO-WBA55CG and STM32WBA55G-DK1 boards
    -

    Backward compatibility

    +

    Backward compatibility

    • Not applicable
    -

    Known Limitations

    +

    Known Limitations

    • None
    -

    Dependencies

    +

    Dependencies

    • None
    -

    Notes

    +

    Notes

    • None
    • - + +
    -

    Main Changes

    -

    Official Release of STM32CubeWBA Firmware package supporting STM32WBA52xx and STM32WBA55xx devices

    -

    Contents

    -

    Official Release of HAL/LL Drivers for STM32WBAxx serie

    +

    Main Changes

    +

    Official +Release of STM32CubeWBA Firmware package supporting +STM32WBA52xx and STM32WBA55xx +devices

    +

    Contents

    +

    Official +Release of HAL/LL Drivers for +STM32WBAxx serie

    • HAL/LL Drivers are available for all peripherals:
        -
      • HAL: ADC, COMP, CORTEX, CRC, CRYP, DMA, EXTI, FLASH, GPIO, GTZC, HASH, HSEM, I2C, ICACHE, IRDA, IWDG, LPTIM, PKA, PWR, RAMCFG, RCC, RNG, RTC, SAI, SMARTCARD, SMBUS, SPI, TIM, TSC, UART, USART, WWDG
        • -
      • LL: ADC, COMP, CRC, DMA, EXTI, GPIO, I2C, ICACHE, LPTIM, LPUART, PKA, PWR, RCC, RNG, RTC, SPI, TIM, USART, UTILS
        • +
      • HAL: ADC, COMP, CORTEX, CRC, CRYP, DMA, EXTI, +FLASH, GPIO, GTZC, HASH, HSEM, I2C, ICACHE, IRDA, IWDG, LPTIM, PKA, PWR, +RAMCFG, RCC, RNG, RTC, SAI, SMARTCARD, SMBUS, SPI, TIM, TSC, UART, +USART, WWDG
        • +
      • LL: ADC, COMP, CRC, DMA, EXTI, GPIO, I2C, ICACHE, +LPTIM, LPUART, PKA, PWR, RCC, RNG, RTC, SPI, TIM, USART, UTILS
    • Update HAL/LL drivers to include latest corrections


    -

    HAL Drivers updates

    +

    HAL Drivers updates

    • HAL CORTEX driver
        @@ -311,30 +768,37 @@

        HAL Drivers updates

    • HAL I2C driver
        -
      • Update HAL_I2C_Slave_Transmit to check if the received NACK is the correct one
        • +
      • Update HAL_I2C_Slave_Transmit to check if the received NACK is the +correct one
      • Update SMBUS_ITErrorHandler to flash TXDR just in case of error
    • HAL RCC driver
        -
      • Add note for Backup domain access to be enabled for RCC_PERIPHCLK_RADIOST use in HAL_RCCEx_PeriphCLKConfig()
        • +
      • Add note for Backup domain access to be enabled for +RCC_PERIPHCLK_RADIOST use in HAL_RCCEx_PeriphCLKConfig()
    • HAL RTC driver
        -
      • Update access to the SCR register now done via a one-shot write access
        • +
      • Update access to the SCR register now done via a one-shot write +access
    • HAL TIM driver
        -
      • Remove not supported TIM_CLOCKSOURCE_ITR3, TIM_CLOCKSOURCE_ITR9 and TIM_CLOCKSOURCE_ITR10 constants
        • -
      • Update HAL_TIM_ConfigOCrefClear() function to check if SMCR.OCCS bit-field is supported by the current instance before updating registers
        • +
      • Remove not supported TIM_CLOCKSOURCE_ITR3, TIM_CLOCKSOURCE_ITR9 and +TIM_CLOCKSOURCE_ITR10 constants
        • +
      • Update HAL_TIM_ConfigOCrefClear() function to check if SMCR.OCCS +bit-field is supported by the current instance before updating +registers
    • HAL TSC driver
        -
      • Modify assert to track the fordidden prescaler related to DT duration
        • +
      • Modify assert to track the fordidden prescaler related to DT +duration


    -

    LL Drivers updates

    +

    LL Drivers updates

    • LL LPUART driver
        @@ -343,63 +807,87 @@

        LL Drivers updates


      -

      Supported Devices and boards

      +

      Supported Devices and +boards

      • STM32WBA52xx and STM32WBA55xx devices
      • NUCLEO-WBA52CG, NUCLEO-WBA55CG and STM32WBA55G-DK1 boards
      -

      Backward compatibility

      +

      Backward compatibility

      • Not applicable
      -

      Known Limitations

      +

      Known Limitations

      • None
      -

      Dependencies

      +

      Dependencies

      • None
      -

      Notes

      +

      Notes

      • None
    - + +
    -

    Main Changes

    -

    Official Release of STM32CubeWBA Firmware package supporting STM32WBA52xx and STM32WBA55xx devices

    -

    Contents

    -

    Official Release of HAL/LL Drivers for STM32WBAxx serie

    +

    Main Changes

    +

    Official +Release of STM32CubeWBA Firmware package supporting +STM32WBA52xx and STM32WBA55xx +devices

    +

    Contents

    +

    Official +Release of HAL/LL Drivers for +STM32WBAxx serie

    • HAL/LL Drivers are available for all peripherals:
        -
      • HAL: ADC, COMP, CORTEX, CRC, CRYP, DMA, EXTI, FLASH, GPIO, GTZC, HASH, HSEM, I2C, ICACHE, IRDA, IWDG, LPTIM, PKA, PWR, RAMCFG, RCC, RNG, RTC, SAI, SMARTCARD, SMBUS, SPI, TIM, TSC, UART, USART, WWDG
        • -
      • LL: ADC, COMP, CRC, DMA, EXTI, GPIO, I2C, ICACHE, LPTIM, LPUART, PKA, PWR, RCC, RNG, RTC, SPI, TIM, USART, UTILS
        • +
      • HAL: ADC, COMP, CORTEX, CRC, CRYP, DMA, EXTI, +FLASH, GPIO, GTZC, HASH, HSEM, I2C, ICACHE, IRDA, IWDG, LPTIM, PKA, PWR, +RAMCFG, RCC, RNG, RTC, SAI, SMARTCARD, SMBUS, SPI, TIM, TSC, UART, +USART, WWDG
        • +
      • LL: ADC, COMP, CRC, DMA, EXTI, GPIO, I2C, ICACHE, +LPTIM, LPUART, PKA, PWR, RCC, RNG, RTC, SPI, TIM, USART, UTILS
      • -
    • Update SysTick clock source management to handle HCLK, HCLK/8, LSI and LSE sources +
    • Update SysTick clock source management to handle +HCLK, HCLK/8, LSI and LSE sources
        -
      • The SysTick clock source shall be configured with HAL_SYSTICK_CLKSourceConfig()
        • -
      • New implementation allowing to not re-initialize the SysTick in RCC after HCLK change if the SysTick source is LSI or LSE
        • -
      • Add support of HAL_SYSTICK_GetCLKSourceConfig() API to return the selected SYSTICK clock source set with HAL_SYSTICK_CLKSourceConfig()
        • +
      • The SysTick clock source shall be configured with +HAL_SYSTICK_CLKSourceConfig()
        • +
      • New implementation allowing to not re-initialize the SysTick in RCC +after HCLK change if the SysTick source is LSI or LSE
        • +
      • Add support of HAL_SYSTICK_GetCLKSourceConfig() API to return the +selected SYSTICK clock source set with +HAL_SYSTICK_CLKSourceConfig()


    -

    HAL Drivers updates

    +

    HAL Drivers updates

    • HAL CORTEX driver
        -
      • Check preemption priority and subpriority versus current priority grouping
        • +
      • Check preemption priority and subpriority versus current priority +grouping
      • Remove check of __MPU_PRESENT flag in HAL CORTEX
        • -
      • Add support of HAL_SYSTICK_GetCLKSourceConfig() API to return the selected SYSTICK clock source set with HAL_SYSTICK_CLKSourceConfig()
        • +
      • Add support of HAL_SYSTICK_GetCLKSourceConfig() API to return the +selected SYSTICK clock source set with +HAL_SYSTICK_CLKSourceConfig()
    • HAL DMA driver
        -
      • Update HAL_DMA_GetConfigChannelAttributes() to return DMA attributes even when TZEN=0
        • -
      • Update HAL_DMA_IRQHandler() to remove unnecessary hardware flag check upon suspend interrupt management
        • +
      • Update HAL_DMA_GetConfigChannelAttributes() to return DMA attributes +even when TZEN=0
        • +
      • Update HAL_DMA_IRQHandler() to remove unnecessary hardware flag +check upon suspend interrupt management
    • HAL FLASH driver
        @@ -408,29 +896,37 @@

        HAL Drivers updates

      • HAL GPIO driver
        • Update HAL_GPIO_Init() using CMSIS definitions
          • -
        • Update GetConfigPinAttributes() to ensure it is used on a single pin
          • +
        • Update GetConfigPinAttributes() to ensure it is used on a single +pin
      • HAL I2C driver
        • Update HAL_I2C_Mem_Write_IT() to initialize XferSize at 0
          • -
        • Update HAL I2C driver to disable all interrupts after end of transaction
          • -
        • Update I2C_Slave_ISR_IT(), I2C_Slave_ISR_DMA() and I2C_ITSlaveCplt() to prevent the call of HAL_I2C_ListenCpltCallback() twice
          • -
        • Update I2C_WaitOnRXNEFlagUntilTimeout() to check I2C_FLAG_AF independently from I2C_FLAG_RXNE
          • +
        • Update HAL I2C driver to disable all interrupts after end of +transaction
          • +
        • Update I2C_Slave_ISR_IT(), I2C_Slave_ISR_DMA() and I2C_ITSlaveCplt() +to prevent the call of HAL_I2C_ListenCpltCallback() twice
          • +
        • Update I2C_WaitOnRXNEFlagUntilTimeout() to check I2C_FLAG_AF +independently from I2C_FLAG_RXNE
        • Update HAL_I2C_IsDeviceReady() function to remove unusable code
      • HAL ICACHE driver
        • Update description of HAL_ICACHE_Enable() function
          • -
        • Update HAL_ICACHE_DeInit() to set registers to their reset value
          • -
        • Update HAL_ICACHE_Invalidate() to prevent launching an invalidation if one has already been launched
          • +
        • Update HAL_ICACHE_DeInit() to set registers to their reset +value
          • +
        • Update HAL_ICACHE_Invalidate() to prevent launching an invalidation +if one has already been launched
      • HAL PKA driver
          -
        • Update HAL_PKA_IRQHandler() to fix MISRA C:2012-Rule-10.3, and Rule-10.4_a warnings
          • +
        • Update HAL_PKA_IRQHandler() to fix MISRA C:2012-Rule-10.3, and +Rule-10.4_a warnings
      • HAL RCC driver
          -
        • Rename RCC_SYSTICKCLKSOURCE_HSI to RCC_SYSTICKCLKSOURCE_HSI_DIV4
          • +
        • Rename RCC_SYSTICKCLKSOURCE_HSI to +RCC_SYSTICKCLKSOURCE_HSI_DIV4
        • Update HAL_RCC_NMI_IRQHandler() to clear flag before callback
      • HAL SAI driver @@ -447,35 +943,48 @@

        HAL Drivers updates

    • HAL SPI driver
        -
      • In Full Duplex mode, calling HAL_SPI_TransmitReceive_DMA() can generate a RX HDMA busy if HDMA TX is not well initialized. To avoid this, now a DMA abort is done on RX path to reset HDMA RX to ready state.
        • +
      • In Full Duplex mode, calling HAL_SPI_TransmitReceive_DMA() can +generate a RX HDMA busy if HDMA TX is not well initialized. To avoid +this, now a DMA abort is done on RX path to reset HDMA RX to ready +state.
      • Add a check before send a Tx to not exceed RxFifo capacity
      • Update IT API to enable interrupts after process unlock
        • -
      • Remove HAL Lock/UnLock mechanism inside HAL_SPI_RegisterCallback and HAL_xxx_UnRegisterCallback functions
        • +
      • Remove HAL Lock/UnLock mechanism inside HAL_SPI_RegisterCallback and +HAL_xxx_UnRegisterCallback functions
    • HAL SYSCFG driver
        -
      • Update assert macro in HAL_SYSCFG_GetConfigAttributes() for accurate argument filtering
        • -
      • Allow HAL_SYSCFG_GetConfigAttributes() to be available in both secure and non-secure mode
        • +
      • Update assert macro in HAL_SYSCFG_GetConfigAttributes() for accurate +argument filtering
        • +
      • Allow HAL_SYSCFG_GetConfigAttributes() to be available in both +secure and non-secure mode
    • HAL TIM driver
      • Fix MISRA warning in TIM_CCxNChannelCmd
      • Generalize bidirectional break input(s) configuration
        • -
      • Update HAL_TIM_IRQHandler() to clear System break interrupt flag
        • -
      • Update TIM_Base_SetConfig() to clear IUF flag after a software update triggered by HAL
        • -
      • Update HAL_TIMEx_OCN_Stop_IT() and HAL_TIMEx_PWMN_Stop_IT() using TIM_CCER_CCxNE_MASK definitions
        • +
      • Update HAL_TIM_IRQHandler() to clear System break interrupt +flag
        • +
      • Update TIM_Base_SetConfig() to clear IUF flag after a software +update triggered by HAL
        • +
      • Update HAL_TIMEx_OCN_Stop_IT() and HAL_TIMEx_PWMN_Stop_IT() using +TIM_CCER_CCxNE_MASK definitions
      • Improve HAL_TIMEx_ConfigBreakDeadTime() function implementation
      • Update TIM_DMAErrorCCxN() to handle CH4N support
    • HAL UART driver
        -
      • Fix incorrect gState check in HAL_UART_RegisterRxEventCallback()/HAL_UART_UnRegisterRxEventCallback() to allow user Rx Event Callback registration when a transmit is ongoing
        • -
      • Avoid RTOF flag to be cleared by a transmit process in polling mode
        • +
      • Fix incorrect gState check in +HAL_UART_RegisterRxEventCallback()/HAL_UART_UnRegisterRxEventCallback() +to allow user Rx Event Callback registration when a transmit is +ongoing
        • +
      • Avoid RTOF flag to be cleared by a transmit process in polling +mode


    -

    LL Drivers updates

    +

    LL Drivers updates

    • LL GPIO driver
        @@ -483,7 +992,8 @@

        LL Drivers updates

    • LL I2C driver
        -
      • Update LL_I2C_HandleTranfer() function to prevent undefined behavior of volatile usage before updating the CR2 register
        • +
      • Update LL_I2C_HandleTranfer() function to prevent undefined behavior +of volatile usage before updating the CR2 register
    • LL RTC driver
        @@ -494,84 +1004,110 @@

        LL Drivers updates

      • Remove support for LL_TIM_ReArmBRK() and LL_TIM_ReArmBRK2()
      • Add new function LL_TIM_CC_IsEnabledPreload()
      • Update LL_TIM_BDTR_Init() implementation
        • -
      • Update OCxConfig() functions to configure complementary channels only when supported
        • +
      • Update OCxConfig() functions to configure complementary channels +only when supported
      • Remove LL_TIM_TIM3_ETRSOURCE_TIM4_ETR definition


    -

    Supported Devices and boards

    +

    Supported Devices and +boards

    • STM32WBA52xx and STM32WBA55xx devices
    • NUCLEO-WBA52CG, NUCLEO-WBA55CG and STM32WBA55G-DK1 boards
    -

    Backward compatibility

    +

    Backward compatibility

    • Not applicable
    -

    Known Limitations

    +

    Known Limitations

    • None
    -

    Dependencies

    +

    Dependencies

    • None
    -

    Notes

    +

    Notes

    • None
    - + +
    -

    Main Changes

    -

    Official Release of STM32CubeWBA Firmware package supporting STM32WBA52xx devices

    -

    Contents

    -

    Official Release of HAL/LL Drivers for STM32WBAxx serie

    +

    Main Changes

    +

    Official +Release of STM32CubeWBA Firmware package supporting +STM32WBA52xx devices

    +

    Contents

    +

    Official +Release of HAL/LL Drivers for +STM32WBAxx serie

    • HAL/LL Drivers are available for all peripherals:
        -
      • HAL: ADC, CORTEX, CRC, CRYP, DMA, EXTI, FLASH, GPIO, GTZC, HASH, HSEM, I2C, ICACHE, IRDA, IWDG, LPTIM, PKA, PWR, RAMCFG, RCC, RNG, RTC, SMARTCARD, SMBUS, SPI, TIM, TSC, UART, USART, WWDG
        • -
      • LL: ADC, CRC, DMA, EXTI, GPIO, I2C, ICACHE, LPTIM, LPUART, PKA, PWR, RCC, RNG, RTC, SPI, TIM, USART, UTILS
        • +
      • HAL: ADC, CORTEX, CRC, CRYP, DMA, EXTI, FLASH, +GPIO, GTZC, HASH, HSEM, I2C, ICACHE, IRDA, IWDG, LPTIM, PKA, PWR, +RAMCFG, RCC, RNG, RTC, SMARTCARD, SMBUS, SPI, TIM, TSC, UART, USART, +WWDG
        • +
      • LL: ADC, CRC, DMA, EXTI, GPIO, I2C, ICACHE, LPTIM, +LPUART, PKA, PWR, RCC, RNG, RTC, SPI, TIM, USART, UTILS


    -

    HAL Drivers updates

    +

    HAL Drivers updates

    • HAL CORTEX driver
        -
      • Use synchronization barriers instead of memory barriers for MPU configuration (as recommended by ARM)
        • -
      • Update MPU_ACCESS_OUTER_SHAREABLE and LL_MPU_ACCESS_OUTER_SHAREABLE definitions
        • +
      • Use synchronization barriers instead of memory barriers for MPU +configuration (as recommended by ARM)
        • +
      • Update MPU_ACCESS_OUTER_SHAREABLE and LL_MPU_ACCESS_OUTER_SHAREABLE +definitions
    • HAL CRYP driver
        -
      • Update Crypt/Decrypt IT processes to avoid Computation Completed IRQ fires before DINR pointer increment
        • +
      • Update Crypt/Decrypt IT processes to avoid Computation Completed IRQ +fires before DINR pointer increment
    • HAL DMA driver
        -
      • Downsize LinkRegisters internal table from 8 to 6 for memory size optimization
        • +
      • Downsize LinkRegisters internal table from 8 to 6 for memory size +optimization
      • Remove 2D addressing as not supported
        • -
      • Remove RepeatBlockConfig from DMA_NodeConfTypeDef structure and internal get function as not used
        • -
      • Update Assert checking the selected request. Assert can now also check in peripheral to memory case
        • -
      • Add missing TIM3 trigger and Request/trigger when I2C1, SAI1, AES, LPTIM2 feature available
        • +
      • Remove RepeatBlockConfig from DMA_NodeConfTypeDef structure and +internal get function as not used
        • +
      • Update Assert checking the selected request. Assert can now also +check in peripheral to memory case
        • +
      • Add missing TIM3 trigger and Request/trigger when I2C1, SAI1, AES, +LPTIM2 feature available
    • HAL EXTI driver
        -
      • Fix computation of pExtiConfig->GPIOSel in HAL_EXTI_GetConfigLine()
        • +
      • Fix computation of pExtiConfig->GPIOSel in +HAL_EXTI_GetConfigLine()
    • HAL Generic driver
      • Allow redefinition of macro UNUSED(x)
        • -
      • Move HAL version definition to HAL generic header file (stm32XXxx_hal.h)
        • +
      • Move HAL version definition to HAL generic header file +(stm32XXxx_hal.h)
    • HAL I2C driver
        -
      • Update HAL_I2C_IsDeviceReady() to support 10-bit addressing mode
        • -
      • Update HAL I2C driver to disable all interrupts after end of transaction
        • -
      • Update HAL_I2C_Init() API to clear ADD10 bit in 7-bit addressing mode
        • +
      • Update HAL_I2C_IsDeviceReady() to support 10-bit addressing +mode
        • +
      • Update HAL I2C driver to disable all interrupts after end of +transaction
        • +
      • Update HAL_I2C_Init() API to clear ADD10 bit in 7-bit addressing +mode
    • HAL PWR driver
        @@ -581,39 +1117,48 @@

        HAL Drivers updates

        • Remove useless polling of RTC_ICSR_WUTWF flag
        • Remove all useless RTC Write Protection Disable/Enable usage
          • -
        • Rework of HAL_RTC_GET_FLAG() macro implementation to return flag bit status
          • -
        • Rework of macro implementation to avoid confusion with parameters input
          • +
        • Rework of HAL_RTC_GET_FLAG() macro implementation to return flag bit +status
          • +
        • Rework of macro implementation to avoid confusion with parameters +input
      • HAL TIM driver
        • Assert check for the right channels
          • -
        • Remove multiple volatile reads or writes in interrupt handler, for better performance
          • +
        • Remove multiple volatile reads or writes in interrupt handler, for +better performance
      • HAL TSC driver
          -
        • Add parameter assertion depends on Duration time restriction link to product
          • +
        • Add parameter assertion depends on Duration time restriction link to +product
      • HAL UART driver
          -
        • Update initialisation sequence for TXINV, RXINV and TXRXSWAP settings
          • +
        • Update initialisation sequence for TXINV, RXINV and TXRXSWAP +settings


      -

      LL Drivers updates

      +

      LL Drivers updates

      • LL DMA driver
          -
        • Clarifies that Linked List Address Offset can be chosen by steps of 4 bytes within 0 to 0xFFFC range
          • -
        • Fix inversion in LL_DMA_ConfigChannelTransfer description parameter
          • +
        • Clarifies that Linked List Address Offset can be chosen by steps of +4 bytes within 0 to 0xFFFC range
          • +
        • Fix inversion in LL_DMA_ConfigChannelTransfer description +parameter
      • LL ICACHE driver
          -
        • Update LL_ICACHE_GetRegionBaseAddress() to return the complete address
          • +
        • Update LL_ICACHE_GetRegionBaseAddress() to return the complete +address
      • LL RCC driver
          -
        • Add LL_RCC_HSE_IsEnabledPrescaler() to check HSE prescaler status
          • +
        • Add LL_RCC_HSE_IsEnabledPrescaler() to check HSE prescaler +status
      • LL TIM driver
          @@ -622,75 +1167,93 @@

          LL Drivers updates


        -

        Supported Devices and boards

        +

        Supported Devices and +boards

        • STM32WBA52xx devices
        • NUCLEO-WBA52CG board
        -

        Backward compatibility

        +

        Backward compatibility

        • Not applicable
        -

        Known Limitations

        +

        Known Limitations

        • None
        -

        Dependencies

        +

        Dependencies

        • None
        -

        Notes

        +

        Notes

        • None
    - + +
    -

    Main Changes

    -

    First Official Release of STM32CubeWBA Firmware package supporting STM32WBA52xx devices

    -

    Contents

    -

    First Official Release of HAL/LL Drivers for STM32WBAxx serie

    +

    Main Changes

    +

    First +Official Release of STM32CubeWBA Firmware package +supporting STM32WBA52xx devices

    +

    Contents

    +

    First +Official Release of HAL/LL Drivers for +STM32WBAxx serie

    • HAL/LL Drivers are available for all peripherals:
        -
      • HAL: ADC, CORTEX, CRC, CRYP, DMA, EXTI, FLASH, GPIO, GTZC, HASH, HSEM, I2C, ICACHE, IRDA, IWDG, LPTIM, PKA, PWR, RAMCFG, RCC, RNG, RTC, SMARTCARD, SMBUS, SPI, TIM, TSC, UART, USART, WWDG
        • -
      • LL: ADC, CRC, DMA, EXTI, GPIO, I2C, ICACHE, LPTIM, LPUART, PKA, PWR, RCC, RNG, RTC, SPI, TIM, USART, UTILS
        • +
      • HAL: ADC, CORTEX, CRC, CRYP, DMA, EXTI, FLASH, +GPIO, GTZC, HASH, HSEM, I2C, ICACHE, IRDA, IWDG, LPTIM, PKA, PWR, +RAMCFG, RCC, RNG, RTC, SMARTCARD, SMBUS, SPI, TIM, TSC, UART, USART, +WWDG
        • +
      • LL: ADC, CRC, DMA, EXTI, GPIO, I2C, ICACHE, LPTIM, +LPUART, PKA, PWR, RCC, RNG, RTC, SPI, TIM, USART, UTILS


    -

    Supported Devices and boards

    +

    Supported Devices and +boards

    • STM32WBA52xx devices
    • NUCLEO-WBA52CG board
    -

    Backward compatibility

    +

    Backward compatibility

    • Not applicable
    -

    Known Limitations

    +

    Known Limitations

    • None
    -

    Dependencies

    +

    Dependencies

    • None
    -

    Notes

    +

    Notes

    • None
    -
    +