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amd : ACP_7_0 : Add sw support for the platform ACP_7_0.
amd : ACP_7_0 : Add SW support for the platform ACP_7_0. Signed-off-by: SaiSurya Ch <saisurya.chakkaveeravenkatanaga@amd.com>
1 parent 2bd7e9d commit 115ae1e

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8 files changed

+291
-17
lines changed

8 files changed

+291
-17
lines changed

‎src/drivers/amd/rembrandt/acp_sw_audio_dma.c‎

Lines changed: 65 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -12,12 +12,18 @@
1212
#include <sof/lib/uuid.h>
1313
#include <sof/trace/trace.h>
1414

15-
#ifdef CONFIG_ACP_6_3
15+
#if defined(CONFIG_ACP_6_3) || defined(CONFIG_ACP_7_0)
1616

1717
SOF_DEFINE_REG_UUID(acp_sw_audio);
1818

1919
DECLARE_TR_CTX(acp_sw_audio_tr, SOF_UUID(acp_sw_audio_uuid), LOG_LEVEL_INFO);
2020

21+
#if defined(CONFIG_ACP_6_3)
22+
#define DMA_CH_COUNT 8
23+
#elif defined(CONFIG_ACP_7_0)
24+
#define DMA_CH_COUNT 12
25+
#endif
26+
2127
//initialization of soundwire-0 fifos(Audio, BT and HS)
2228
#define SW0_AUDIO_FIFO_SIZE 128
2329
#define SW0_AUDIO_TX_FIFO_ADDR 0
@@ -31,10 +37,18 @@ DECLARE_TR_CTX(acp_sw_audio_tr, SOF_UUID(acp_sw_audio_uuid), LOG_LEVEL_INFO);
3137
#define SW0_HS_TX_FIFO_ADDR (SW0_BT_RX_FIFO_ADDR + SW0_BT_FIFO_SIZE)
3238
#define SW0_HS_RX_FIFO_ADDR (SW0_HS_TX_FIFO_ADDR + SW0_HS_FIFO_SIZE)
3339

34-
//initialization of soundwire-1 fifo
35-
#define SW1_FIFO_SIZE 128
36-
#define SW1_TX_FIFO_ADDR (SW0_HS_RX_FIFO_ADDR + SW1_FIFO_SIZE)
37-
#define SW1_RX_FIFO_ADDR (SW1_TX_FIFO_ADDR + SW1_FIFO_SIZE)
40+
//initialization of soundwire-1 fifos(Audio, BT and HS)
41+
#define SW1_AUDIO_FIFO_SIZE 128
42+
#define SW1_AUDIO_TX_FIFO_ADDR (SW0_HS_RX_FIFO_ADDR + SW0_HS_FIFO_SIZE)
43+
#define SW1_AUDIO_RX_FIFO_ADDR (SW1_AUDIO_TX_FIFO_ADDR + SW1_AUDIO_FIFO_SIZE)
44+
45+
#define SW1_BT_FIFO_SIZE 128
46+
#define SW1_BT_TX_FIFO_ADDR (SW1_AUDIO_RX_FIFO_ADDR + SW1_AUDIO_FIFO_SIZE)
47+
#define SW1_BT_RX_FIFO_ADDR (SW1_BT_TX_FIFO_ADDR + SW1_BT_FIFO_SIZE)
48+
49+
#define SW1_HS_FIFO_SIZE 128
50+
#define SW1_HS_TX_FIFO_ADDR (SW1_BT_RX_FIFO_ADDR + SW1_BT_FIFO_SIZE)
51+
#define SW1_HS_RX_FIFO_ADDR (SW1_HS_TX_FIFO_ADDR + SW1_HS_FIFO_SIZE)
3852

3953
static uint32_t sw_audio_buff_size_playback;
4054
static uint32_t sw_audio_buff_size_capture;
@@ -55,7 +69,7 @@ struct sw_dev_register {
5569
uint32_t statusindex;
5670
};
5771

58-
static struct sw_dev_register sw_dev[8] = {
72+
static struct sw_dev_register sw_dev[DMA_CH_COUNT] = {
5973
{ACP_SW_HS_RX_EN, ACP_SW_HS_RX_EN_STATUS, ACP_HS_RX_FIFOADDR, SW0_HS_RX_FIFO_ADDR,
6074
ACP_HS_RX_FIFOSIZE, SW0_HS_FIFO_SIZE, ACP_HS_RX_RINGBUFADDR, ACP_HS_RX_RINGBUFSIZE,
6175
ACP_HS_RX_DMA_SIZE, ACP_HS_RX_INTR_WATERMARK_SIZE, ACP_DSP0_INTR_STAT, ACP_DSP0_INTR_CNTL, 0},
@@ -64,13 +78,13 @@ ACP_HS_RX_DMA_SIZE, ACP_HS_RX_INTR_WATERMARK_SIZE, ACP_DSP0_INTR_STAT, ACP_DSP0_
6478
ACP_HS_TX_FIFOSIZE, SW0_HS_FIFO_SIZE, ACP_HS_TX_RINGBUFADDR, ACP_HS_TX_RINGBUFSIZE,
6579
ACP_HS_TX_DMA_SIZE, ACP_HS_TX_INTR_WATERMARK_SIZE, ACP_DSP0_INTR_STAT, ACP_DSP0_INTR_CNTL, 1},
6680

67-
{ACP_P1_SW_BT_RX_EN, ACP_P1_SW_BT_RX_EN_STATUS, ACP_P1_BT_RX_FIFOADDR, SW1_RX_FIFO_ADDR,
68-
ACP_P1_BT_RX_FIFOSIZE, SW1_FIFO_SIZE, ACP_P1_BT_RX_RINGBUFADDR, ACP_P1_BT_RX_RINGBUFSIZE,
81+
{ACP_P1_SW_BT_RX_EN, ACP_P1_SW_BT_RX_EN_STATUS, ACP_P1_BT_RX_FIFOADDR, SW1_BT_RX_FIFO_ADDR,
82+
ACP_P1_BT_RX_FIFOSIZE, SW1_BT_FIFO_SIZE, ACP_P1_BT_RX_RINGBUFADDR, ACP_P1_BT_RX_RINGBUFSIZE,
6983
ACP_P1_BT_RX_DMA_SIZE, ACP_P1_BT_RX_INTR_WATERMARK_SIZE, ACP_DSP0_INTR_STAT1, ACP_DSP0_INTR_CNTL1,
7084
2},
7185

72-
{ACP_P1_SW_BT_TX_EN, ACP_P1_SW_BT_TX_EN_STATUS, ACP_P1_BT_TX_FIFOADDR, SW1_TX_FIFO_ADDR,
73-
ACP_P1_BT_TX_FIFOSIZE, SW1_FIFO_SIZE, ACP_P1_BT_TX_RINGBUFADDR, ACP_P1_BT_TX_RINGBUFSIZE,
86+
{ACP_P1_SW_BT_TX_EN, ACP_P1_SW_BT_TX_EN_STATUS, ACP_P1_BT_TX_FIFOADDR, SW1_BT_TX_FIFO_ADDR,
87+
ACP_P1_BT_TX_FIFOSIZE, SW1_BT_FIFO_SIZE, ACP_P1_BT_TX_RINGBUFADDR, ACP_P1_BT_TX_RINGBUFSIZE,
7488
ACP_P1_BT_TX_DMA_SIZE, ACP_P1_BT_TX_INTR_WATERMARK_SIZE, ACP_DSP0_INTR_STAT1, ACP_DSP0_INTR_CNTL1,
7589
3},
7690

@@ -88,7 +102,29 @@ ACP_BT_RX_DMA_SIZE, ACP_BT_RX_INTR_WATERMARK_SIZE, ACP_DSP0_INTR_STAT, ACP_DSP0_
88102

89103
{ACP_SW_BT_TX_EN, ACP_SW_BT_TX_EN_STATUS, ACP_BT_TX_FIFOADDR, SW0_BT_TX_FIFO_ADDR,
90104
ACP_BT_TX_FIFOSIZE, SW0_BT_FIFO_SIZE, ACP_BT_TX_RINGBUFADDR, ACP_BT_TX_RINGBUFSIZE,
91-
ACP_BT_TX_DMA_SIZE, ACP_BT_TX_INTR_WATERMARK_SIZE, ACP_DSP0_INTR_STAT, ACP_DSP0_INTR_CNTL, 3}
105+
ACP_BT_TX_DMA_SIZE, ACP_BT_TX_INTR_WATERMARK_SIZE, ACP_DSP0_INTR_STAT, ACP_DSP0_INTR_CNTL, 3},
106+
107+
#if defined(CONFIG_ACP_7_0)
108+
{ACP_P1_SW_Audio_RX_EN, ACP_P1_SW_Audio_RX_EN_STATUS, ACP_P1_AUDIO_RX_FIFOADDR, SW1_AUDIO_RX_FIFO_ADDR,
109+
ACP_P1_AUDIO_RX_FIFOSIZE, SW1_AUDIO_FIFO_SIZE, ACP_P1_AUDIO_RX_RINGBUFADDR, ACP_P1_AUDIO_RX_RINGBUFSIZE,
110+
ACP_P1_AUDIO_RX_DMA_SIZE, ACP_P1_AUDIO_RX_INTR_WATERMARK_SIZE, ACP_DSP0_INTR_STAT1, ACP_DSP0_INTR_CNTL1,
111+
4},
112+
113+
{ACP_P1_SW_Audio_TX_EN, ACP_P1_SW_Audio_TX_EN_STATUS, ACP_P1_AUDIO_TX_FIFOADDR, SW1_AUDIO_TX_FIFO_ADDR,
114+
ACP_P1_AUDIO_TX_FIFOSIZE, SW1_AUDIO_FIFO_SIZE, ACP_P1_AUDIO_TX_RINGBUFADDR, ACP_P1_AUDIO_TX_RINGBUFSIZE,
115+
ACP_P1_AUDIO_TX_DMA_SIZE, ACP_P1_AUDIO_TX_INTR_WATERMARK_SIZE, ACP_DSP0_INTR_STAT1, ACP_DSP0_INTR_CNTL1,
116+
5},
117+
118+
{ACP_P1_SW_Headset_RX_EN, ACP_P1_SW_Headset_RX_EN_STATUS, ACP_P1_HS_RX_FIFOADDR, SW1_HS_RX_FIFO_ADDR,
119+
ACP_P1_HS_RX_FIFOSIZE, SW1_HS_FIFO_SIZE, ACP_P1_HS_RX_RINGBUFADDR, ACP_P1_HS_RX_RINGBUFSIZE,
120+
ACP_P1_HS_RX_DMA_SIZE, ACP_P1_HS_RX_INTR_WATERMARK_SIZE, ACP_DSP0_INTR_STAT1, ACP_DSP0_INTR_CNTL1,
121+
0},
122+
123+
{ACP_P1_SW_Headset_TX_EN, ACP_P1_SW_Headset_TX_EN_STATUS, ACP_P1_HS_TX_FIFOADDR, SW1_HS_TX_FIFO_ADDR,
124+
ACP_P1_HS_TX_FIFOSIZE, SW1_HS_FIFO_SIZE, ACP_P1_HS_TX_RINGBUFADDR, ACP_P1_HS_TX_RINGBUFSIZE,
125+
ACP_P1_HS_TX_DMA_SIZE, ACP_P1_HS_TX_INTR_WATERMARK_SIZE, ACP_DSP0_INTR_STAT1, ACP_DSP0_INTR_CNTL1,
126+
1},
127+
#endif
92128
};
93129

94130
/* allocate next free DMA channel */
@@ -136,7 +172,7 @@ static int acp_dai_sw_audio_dma_start(struct dma_chan_data *channel)
136172
uint32_t acp_pdm_en;
137173
int i;
138174

139-
for (i = 0; i < 8; i += 2) {
175+
for (i = 0; i < DMA_CH_COUNT; i += 2) {
140176
sw0_audio_tx_en |= io_reg_read(PU_REGISTER_BASE + sw_dev[i].sw_dev_en);
141177
sw0_audio_rx_en |= io_reg_read(PU_REGISTER_BASE + sw_dev[i + 1].sw_dev_en);
142178
}
@@ -208,7 +244,7 @@ static int acp_dai_sw_audio_dma_stop(struct dma_chan_data *channel)
208244
return -EINVAL;
209245
}
210246

211-
for (i = 0; i < 8; i += 2) {
247+
for (i = 0; i < DMA_CH_COUNT; i += 2) {
212248
sw0_audio_tx_en |= io_reg_read(PU_REGISTER_BASE + sw_dev[i].sw_dev_en);
213249
sw0_audio_rx_en |= io_reg_read(PU_REGISTER_BASE + sw_dev[i + 1].sw_dev_en);
214250
}
@@ -420,6 +456,10 @@ static int acp_dai_sw_audio_dma_interrupt(struct dma_chan_data *channel, enum dm
420456
switch (channel->index) {
421457
case SDW1_ACP_P1_SW_BT_TX_EN_CH:
422458
case SDW1_ACP_P1_SW_BT_RX_EN_CH:
459+
case SDW1_ACP_P1_SW_AUDIO_RX_EN_CH:
460+
case SDW1_ACP_P1_SW_AUDIO_TX_EN_CH:
461+
case SDW1_ACP_P1_SW_HS_RX_EN_CH:
462+
case SDW1_ACP_P1_SW_HS_TX_EN_CH:
423463
acp_intr_stat1 = (acp_dsp0_intr_stat1_t)dma_reg_read(channel->dma,
424464
sw_dev[channel->index].sw_dev_dma_intr_status);
425465
status = acp_intr_stat1.bits.audio_buffer_int_stat;
@@ -435,6 +475,10 @@ static int acp_dai_sw_audio_dma_interrupt(struct dma_chan_data *channel, enum dm
435475
switch (channel->index) {
436476
case SDW1_ACP_P1_SW_BT_TX_EN_CH:
437477
case SDW1_ACP_P1_SW_BT_RX_EN_CH:
478+
case SDW1_ACP_P1_SW_AUDIO_RX_EN_CH:
479+
case SDW1_ACP_P1_SW_AUDIO_TX_EN_CH:
480+
case SDW1_ACP_P1_SW_HS_RX_EN_CH:
481+
case SDW1_ACP_P1_SW_HS_TX_EN_CH:
438482
acp_intr_stat1.u32all = 0;
439483
acp_intr_stat1.bits.audio_buffer_int_stat =
440484
(1 << sw_dev[channel->index].statusindex);
@@ -456,6 +500,10 @@ static int acp_dai_sw_audio_dma_interrupt(struct dma_chan_data *channel, enum dm
456500
switch (channel->index) {
457501
case SDW1_ACP_P1_SW_BT_TX_EN_CH:
458502
case SDW1_ACP_P1_SW_BT_RX_EN_CH:
503+
case SDW1_ACP_P1_SW_AUDIO_RX_EN_CH:
504+
case SDW1_ACP_P1_SW_AUDIO_TX_EN_CH:
505+
case SDW1_ACP_P1_SW_HS_RX_EN_CH:
506+
case SDW1_ACP_P1_SW_HS_TX_EN_CH:
459507
acp_intr_cntl1 = (acp_dsp0_intr_cntl1_t)dma_reg_read(channel->dma,
460508
sw_dev[channel->index].sw_dev_dma_intr_cntl);
461509
acp_intr_cntl1.bits.audio_buffer_int_mask &=
@@ -479,6 +527,10 @@ static int acp_dai_sw_audio_dma_interrupt(struct dma_chan_data *channel, enum dm
479527
switch (channel->index) {
480528
case SDW1_ACP_P1_SW_BT_TX_EN_CH:
481529
case SDW1_ACP_P1_SW_BT_RX_EN_CH:
530+
case SDW1_ACP_P1_SW_AUDIO_RX_EN_CH:
531+
case SDW1_ACP_P1_SW_AUDIO_TX_EN_CH:
532+
case SDW1_ACP_P1_SW_HS_RX_EN_CH:
533+
case SDW1_ACP_P1_SW_HS_TX_EN_CH:
482534
acp_intr_cntl1 = (acp_dsp0_intr_cntl1_t)dma_reg_read(channel->dma,
483535
sw_dev[channel->index].sw_dev_dma_intr_cntl);
484536
acp_intr_cntl1.bits.audio_buffer_int_mask |=

‎src/platform/amd/acp_7_0/include/platform/chip_offset_byte.h‎

Lines changed: 48 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -136,6 +136,21 @@
136136
#define ACP_WOV_MISC_CTRL 0x1242C5C
137137
#define ACP_WOV_CLK_CTRL 0x1242C60
138138

139+
#define ACP_SW_EN 0x1243000
140+
#define ACP_SW_EN_STATUS 0x1243004
141+
#define ACP_SW_AUDIO_TX_EN 0x1243010
142+
#define ACP_SW_AUDIO_TX_EN_STATUS 0x1243014
143+
#define ACP_SW_BT_TX_EN 0x1243050
144+
#define ACP_SW_BT_TX_EN_STATUS 0x1243054
145+
#define ACP_SW_HS_TX_EN 0x124306C
146+
#define ACP_SW_HS_TX_EN_STATUS 0x1243070
147+
#define ACP_SW_AUDIO_RX_EN 0x1243088
148+
#define ACP_SW_AUDIO_RX_EN_STATUS 0x124308C
149+
#define ACP_SW_BT_RX_EN 0x1243128
150+
#define ACP_SW_BT_RX_EN_STATUS 0x124312C
151+
#define ACP_SW_HS_RX_EN 0x1243144
152+
#define ACP_SW_HS_RX_EN_STATUS 0x1243148
153+
139154
/* Registers from ACP_P1_AUDIO_BUFFERS block */
140155
#define ACP_P1_I2S_RX_RINGBUFADDR 0x1243A00
141156
#define ACP_P1_I2S_RX_RINGBUFSIZE 0x1243A04
@@ -153,6 +168,24 @@
153168
#define ACP_P1_I2S_TX_LINEARPOSITIONCNTR_HIGH 0x1243A3C
154169
#define ACP_P1_I2S_TX_LINEARPOSITIONCNTR_LOW 0x1243A40
155170
#define ACP_P1_I2S_TX_INTR_WATERMARK_SIZE 0x1243A44
171+
172+
#define ACP_P1_AUDIO_RX_RINGBUFADDR 0x1243A00
173+
#define ACP_P1_AUDIO_RX_RINGBUFSIZE 0x1243A04
174+
#define ACP_P1_AUDIO_RX_FIFOADDR 0x1243A0C
175+
#define ACP_P1_AUDIO_RX_FIFOSIZE 0x1243A10
176+
#define ACP_P1_AUDIO_RX_DMA_SIZE 0x1243A14
177+
#define ACP_P1_AUDIO_RX_LINEARPOSITIONCNTR_HIGH 0x1243A18
178+
#define ACP_P1_AUDIO_RX_LINEARPOSITIONCNTR_LOW 0x1243A1C
179+
#define ACP_P1_AUDIO_RX_INTR_WATERMARK_SIZE 0x1243A20
180+
#define ACP_P1_AUDIO_TX_RINGBUFADDR 0x1243A24
181+
#define ACP_P1_AUDIO_TX_RINGBUFSIZE 0x1243A28
182+
#define ACP_P1_AUDIO_TX_FIFOADDR 0x1243A30
183+
#define ACP_P1_AUDIO_TX_FIFOSIZE 0x1243A34
184+
#define ACP_P1_AUDIO_TX_DMA_SIZE 0x1243A38
185+
#define ACP_P1_AUDIO_TX_LINEARPOSITIONCNTR_HIGH 0x1243A3C
186+
#define ACP_P1_AUDIO_TX_LINEARPOSITIONCNTR_LOW 0x1243A40
187+
#define ACP_P1_AUDIO_TX_INTR_WATERMARK_SIZE 0x1243A44
188+
156189
#define ACP_P1_BT_RX_RINGBUFADDR 0x1243A48
157190
#define ACP_P1_BT_RX_RINGBUFSIZE 0x1243A4C
158191
#define ACP_P1_BT_RX_FIFOADDR 0x1243A54
@@ -186,6 +219,21 @@
186219
#define ACP_P1_HS_TX_LINEARPOSITIONCNTR_LOW 0x1243AD0
187220
#define ACP_P1_HS_TX_INTR_WATERMARK_SIZE 0x1243AD4
188221

222+
#define ACP_P1_SW_Audio_TX_EN 0x1243C10
223+
#define ACP_P1_SW_Audio_TX_EN_STATUS 0x1243C14
224+
#define ACP_P1_SW_Audio_RX_EN 0x1243C88
225+
#define ACP_P1_SW_Audio_RX_EN_STATUS 0x1243C8C
226+
227+
#define ACP_P1_SW_BT_TX_EN 0x1243C50
228+
#define ACP_P1_SW_BT_TX_EN_STATUS 0x1243C54
229+
#define ACP_P1_SW_BT_RX_EN 0x1243D28
230+
#define ACP_P1_SW_BT_RX_EN_STATUS 0x1243D2C
231+
232+
#define ACP_P1_SW_Headset_TX_EN 0x1243C6C
233+
#define ACP_P1_SW_Headset_TX_EN_STATUS 0x1243C70
234+
#define ACP_P1_SW_Headset_RX_EN 0x1243D44
235+
#define ACP_P1_SW_Headset_RX_EN_STATUS 0x1243D48
236+
189237
#define MP1_SMN_C2PMSG_69 0x58A14
190238
#define MP1_SMN_C2PMSG_85 0x58A54
191239
#define MP1_SMN_C2PMSG_93 0x58A74

‎src/platform/amd/acp_7_0/include/platform/lib/memory.h‎

Lines changed: 11 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,7 @@
2626
#define DRAM1_BASE 0xE0010000
2727
#define DRAM1_SIZE 0x10000
2828
#define SRAM1_BASE 0x6000C000
29-
#define SRAM1_SIZE 0x27A000
29+
#define SRAM1_SIZE 0x274000
3030

3131
#define DMA0_BASE PU_REGISTER_BASE
3232
#define DMA0_SIZE 0x4
@@ -35,12 +35,22 @@
3535
#define DAI_BASE (PU_REGISTER_BASE + ACP_I2S_RX_RINGBUFADDR)
3636
#define DAI_BASE_REM (PU_REGISTER_BASE + ACP_P1_I2S_RX_RINGBUFADDR)
3737
#define DAI_SIZE 0x4
38+
39+
#define SW1_AUDIO_TX_FIFO_OFFST (ACP_P1_AUDIO_TX_FIFOADDR - ACP_P1_AUDIO_RX_RINGBUFADDR)
40+
#define SW1_AUDIO_RX_FIFO_OFFST (ACP_P1_AUDIO_RX_FIFOADDR - ACP_P1_AUDIO_RX_RINGBUFADDR)
41+
3842
#define BT_TX_FIFO_OFFST (ACP_P1_BT_TX_FIFOADDR - ACP_P1_I2S_RX_RINGBUFADDR)
3943
#define BT_RX_FIFO_OFFST (ACP_P1_BT_RX_FIFOADDR - ACP_P1_I2S_RX_RINGBUFADDR)
4044

45+
#define SW1_HS_TX_FIFO_OFFST (ACP_P1_HS_TX_FIFOADDR - ACP_P1_HS_RX_RINGBUFADDR)
46+
#define SW1_HS_RX_FIFO_OFFST (ACP_P1_HS_RX_FIFOADDR - ACP_P1_HS_RX_RINGBUFADDR)
47+
4148
#define HS_TX_FIFO_OFFST (ACP_P1_HS_TX_FIFOADDR - ACP_P1_I2S_RX_RINGBUFADDR)
4249
#define HS_RX_FIFO_OFFST (ACP_P1_HS_TX_FIFOADDR - ACP_P1_I2S_RX_RINGBUFADDR)
4350

51+
#define SW0_AUDIO_TX_FIFO_OFFST (ACP_AUDIO_TX_FIFOADDR - ACP_AUDIO_RX_RINGBUFADDR)
52+
#define SW0_AUDIO_RX_FIFO_OFFST (ACP_AUDIO_RX_FIFOADDR - ACP_AUDIO_RX_RINGBUFADDR)
53+
4454
#define BT0_TX_FIFO_OFFST (ACP_BT_TX_FIFOADDR - ACP_AUDIO_RX_RINGBUFADDR)
4555
#define BT0_RX_FIFO_OFFST (ACP_BT_RX_FIFOADDR - ACP_AUDIO_RX_RINGBUFADDR)
4656

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