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Commit ee8398b

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AlexLanzanoAlexLanzano
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[core, drivers] Change register field definitions to CMSIS style
1 parent 52f0af4 commit ee8398b

25 files changed

Lines changed: 811 additions & 536 deletions

‎examples/pic32cz/pic32cz_curiosity_ultra.c‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -72,7 +72,8 @@ static whal_Pic32czClock_Clk uartClk = {
7272
.gclkPeriphChannel = 25, /* SERCOM 4 */
7373
.gclkPeriphSrc = 0, /* GEN 0 */
7474
.mclkEnableInst = 1, /* Peripheral BUS Clock Enable Mask1 Register */
75-
.mclkEnableMask = WHAL_MASK(3), /* SERCOM 4 enable mask */
75+
.mclkEnableMask = (1UL << 3), /* SERCOM 4 enable mask */
76+
.mclkEnablePos = 3,
7677
};
7778

7879
whal_Uart g_whalUart = {

‎src/clock/pic32cz_clock.c‎

Lines changed: 67 additions & 44 deletions
Original file line numberDiff line numberDiff line change
@@ -17,55 +17,76 @@
1717

1818
/* PLL Control Register - enables PLL and selects reference/bandwidth */
1919
#define OSCCTRL_PLLxCTRL_REG(pllInst) (0x40 + (pllInst * 20))
20-
#define OSCCTRL_PLLxCTRL_ENABLE WHAL_MASK(1) /* PLL enable */
21-
#define OSCCTRL_PLLxCTRL_REFSEL WHAL_MASK_RANGE(10, 8) /* Reference select */
22-
#define OSCCTRL_PLLxCTRL_BWSEL WHAL_MASK_RANGE(13, 11) /* Bandwidth select */
20+
#define OSCCTRL_PLLxCTRL_ENABLE_Pos 1 /* PLL enable */
21+
#define OSCCTRL_PLLxCTRL_ENABLE_Msk (1UL << OSCCTRL_PLLxCTRL_ENABLE_Pos)
22+
23+
#define OSCCTRL_PLLxCTRL_REFSEL_Pos 8 /* Reference select */
24+
#define OSCCTRL_PLLxCTRL_REFSEL_Msk (WHAL_BITMASK(3) << OSCCTRL_PLLxCTRL_REFSEL_Pos)
25+
26+
#define OSCCTRL_PLLxCTRL_BWSEL_Pos 11 /* Bandwidth select */
27+
#define OSCCTRL_PLLxCTRL_BWSEL_Msk (WHAL_BITMASK(3) << OSCCTRL_PLLxCTRL_BWSEL_Pos)
2328

2429
/* PLL Feedback Divider Register - sets VCO multiplication factor */
2530
#define OSCCTRL_PLLxFBDIV_REG(pllInst) (0x44 + (pllInst * 20))
26-
#define OSCCTRL_PLLxFBDIV WHAL_MASK_RANGE(9, 0) /* Feedback divider (16-1023) */
31+
#define OSCCTRL_PLLxFBDIV_Pos 0 /* Feedback divider (16-1023) */
32+
#define OSCCTRL_PLLxFBDIV_Msk (WHAL_BITMASK(10) << OSCCTRL_PLLxFBDIV_Pos)
2733

2834
/* PLL Reference Divider Register - divides input reference clock */
2935
#define OSCCTRL_PLLxREFDIV_REG(pllInst) (0x48 + (pllInst * 20))
30-
#define OSCCTRL_PLLxREFDIV WHAL_MASK_RANGE(5, 0) /* Reference divider (1-63) */
36+
#define OSCCTRL_PLLxREFDIV_Pos 0 /* Reference divider (1-63) */
37+
#define OSCCTRL_PLLxREFDIV_Msk (WHAL_BITMASK(6) << OSCCTRL_PLLxREFDIV_Pos)
3138

3239
/* PLL Post-Divider A Register - divides VCO for each output */
3340
#define OSCCTRL_PLLxPOSTDIVA_REG(pllInst) (0x4C + (pllInst * 20))
34-
#define OSCCTRL_PLLxPOSTDIVA_POSTDIV0 WHAL_MASK_RANGE(5, 0) /* Output 0 divider */
35-
#define OSCCTRL_PLLxPOSTDIVA_OUTEN0 WHAL_MASK(7) /* Output 0 enable */
41+
#define OSCCTRL_PLLxPOSTDIVA_POSTDIV0_Pos 0 /* Output 0 divider */
42+
#define OSCCTRL_PLLxPOSTDIVA_POSTDIV0_Msk (WHAL_BITMASK(6) << OSCCTRL_PLLxPOSTDIVA_POSTDIV0_Pos)
43+
#define OSCCTRL_PLLxPOSTDIVA_OUTEN0_Pos 7 /* Output 0 enable */
44+
#define OSCCTRL_PLLxPOSTDIVA_OUTEN0_Msk (1UL << OSCCTRL_PLLxPOSTDIVA_OUTEN0_Pos)
3645

3746
/* OSCCTRL Status Register - PLL lock and oscillator ready flags */
3847
#define OSCCTRL_STATUS_REG (OSCCTRL + 0x10)
39-
#define OSCCTRL_STATUS_PLLxLOCK(pllInst) WHAL_MASK((24 + (pllInst)))
48+
#define OSCCTRL_STATUS_PLLxLOCK_Pos(pllInst) (24 + (pllInst))
49+
#define OSCCTRL_STATUS_PLLxLOCK_Msk(pllInst) (1UL << (OSCCTRL_STATUS_PLLxLOCK_Pos(pllInst)))
4050

4151
/* GCLK - Generic Clock Controller (base offset 0x10000) */
4252
#define GCLK 0x10000
4353

4454
/* Generator Control Register - configures clock source and divider per generator */
4555
#define GCLK_GENCTRLx_REG(gclkInst) ((GCLK + 0x20 + (gclkInst * 0x4)))
46-
#define GCLK_GENCTRLx_SRC WHAL_MASK_RANGE(4, 0) /* Source selection */
47-
#define GCLK_GENCTRLx_GENEN WHAL_MASK(8) /* Generator enable */
48-
#define GCLK_GENCTRLx_DIV WHAL_MASK_RANGE(31, 16) /* Division factor */
56+
#define GCLK_GENCTRLx_SRC_Pos 0 /* Source selection */
57+
#define GCLK_GENCTRLx_SRC_Msk (WHAL_BITMASK(5) << GCLK_GENCTRLx_SRC_Pos)
58+
59+
#define GCLK_GENCTRLx_GENEN_Pos 8 /* Generator enable */
60+
#define GCLK_GENCTRLx_GENEN_Msk (1UL << GCLK_GENCTRLx_GENEN_Pos)
61+
62+
#define GCLK_GENCTRLx_DIV_Pos 16 /* Division factor */
63+
#define GCLK_GENCTRLx_DIV_Msk (WHAL_BITMASK(16) << GCLK_GENCTRLx_DIV_Pos)
4964

5065
/* Peripheral Channel Control Register - connects generator to peripheral */
5166
#define GCLK_PCHCTRLx_REG(periphChannel) (GCLK + 0x80 + (periphChannel * 0x4))
52-
#define GCLK_PCHCTRLx_GEN WHAL_MASK_RANGE(3, 0) /* Generator selection */
53-
#define GCLK_PCHCTRLx_CHEN WHAL_MASK(6) /* Channel enable */
67+
#define GCLK_PCHCTRLx_GEN_Pos 0 /* Generator selection */
68+
#define GCLK_PCHCTRLx_GEN_Msk (WHAL_BITMASK(4) << GCLK_PCHCTRLx_GEN_Pos)
69+
70+
#define GCLK_PCHCTRLx_CHEN_Pos 6 /* Channel enable */
71+
#define GCLK_PCHCTRLx_CHEN_Msk (1UL << GCLK_PCHCTRLx_CHEN_Pos)
5472

5573
/* GCLK Synchronization Busy Register - poll after writing GENCTRLx */
5674
#define GCLK_SYNCBUSY_REG (GCLK + 0x04)
57-
#define GCLK_SYNCBUSY_GENCTRLx(gclkInst) WHAL_MASK((2 + (gclkInst)))
75+
#define GCLK_SYNCBUSY_GENCTRLx_Pos(gclkInst) (2 + (gclkInst))
76+
#define GCLK_SYNCBUSY_GENCTRLx_Msk(gclkInst) (1UL << (GCLK_SYNCBUSY_GENCTRLx_Pos(gclkInst)))
5877

5978
/* MCLK - Main Clock Controller (base offset 0x12000) */
6079
#define MCLK 0x12000
6180

6281
/* MCLK Interrupt Flag Register - clock ready status */
6382
#define MCLK_INTFLAG_REG (MCLK + 0x08)
64-
#define MCLK_INTFLAG_CKRDY WHAL_MASK(0) /* Clock ready */
83+
#define MCLK_INTFLAG_CKRDY_Pos 0 /* Clock ready */
84+
#define MCLK_INTFLAG_CKRDY_Msk (1UL << MCLK_INTFLAG_CKRDY_Pos)
6585

6686
/* CPU Clock Divider Register */
6787
#define MCLK_DIV1_REG (MCLK + 0x10)
68-
#define MCLK_DIV1 WHAL_MASK_RANGE(7, 0) /* CPU clock divider */
88+
#define MCLK_DIV1_Pos 0 /* CPU clock divider */
89+
#define MCLK_DIV1_Msk (WHAL_BITMASK(8) << MCLK_DIV1_Pos)
6990

7091
/* Peripheral Clock Mask Registers - enable/disable bus clocks to peripherals */
7192
#define MCLK_CLKxMSK_REG(enableInst) (MCLK + 0x3C + (enableInst * 0x4))
@@ -107,7 +128,7 @@
107128
* .gclkPeriphChannel = 23, // SERCOM0_CORE
108129
* .gclkPeriphSrc = 0, // Use generator 0
109130
* .mclkEnableInst = 2, // APBBMASK register
110-
* .mclkEnableMask = WHAL_MASK(1), // SERCOM0 bit
131+
* .mclkEnableMask = (1UL << 1), // SERCOM0 bit
111132
* };
112133
*/
113134

@@ -141,58 +162,60 @@ whal_Error whal_Pic32czClockPll_Init(whal_Clock *clkDev)
141162
whal_Supply_Enable(oscCtrlCfg->supplyCtrl, oscCtrlCfg->supply);
142163

143164
/* Configure PLL feedback divider (sets VCO multiplication factor) */
144-
whal_Reg_Update(clkDev->regmap.base, PLLxFBDIV_REG, OSCCTRL_PLLxFBDIV,
145-
whal_SetBits(OSCCTRL_PLLxFBDIV, oscCtrlCfg->fbDiv));
165+
whal_Reg_Update(clkDev->regmap.base, PLLxFBDIV_REG, OSCCTRL_PLLxFBDIV_Msk,
166+
whal_SetBits(OSCCTRL_PLLxFBDIV_Msk, OSCCTRL_PLLxFBDIV_Pos, oscCtrlCfg->fbDiv));
146167

147168
/* Configure PLL reference divider (divides input clock before PLL) */
148-
whal_Reg_Update(clkDev->regmap.base, PLLxREFDIV_REG, OSCCTRL_PLLxREFDIV,
149-
whal_SetBits(OSCCTRL_PLLxREFDIV, oscCtrlCfg->refDiv));
169+
whal_Reg_Update(clkDev->regmap.base, PLLxREFDIV_REG, OSCCTRL_PLLxREFDIV_Msk,
170+
whal_SetBits(OSCCTRL_PLLxREFDIV_Msk, OSCCTRL_PLLxREFDIV_Pos, oscCtrlCfg->refDiv));
150171

151172
/* Configure each PLL output with its post-divider and enable it */
152173
for (uint8_t i = 0; i < oscCtrlCfg->outCfgCount; ++i) {
153174
whal_Pic32czClockPll_OutCfg *outCfg = &oscCtrlCfg->outCfg[i];
154175
whal_Reg_Update(clkDev->regmap.base, PLLxPOSTDIVA_REG,
155176
outCfg->outEnMask | outCfg->postDivMask,
156-
whal_SetBits(outCfg->outEnMask, 1) |
157-
whal_SetBits(outCfg->postDivMask, outCfg->postDiv));
177+
outCfg->outEnMask |
178+
whal_SetBits(outCfg->postDivMask, __builtin_ctz(outCfg->postDivMask), outCfg->postDiv));
158179
}
159180

160181
/* Enable PLL with selected reference source and loop filter bandwidth */
161182
whal_Reg_Update(clkDev->regmap.base, PLLxCTRL_REG,
162-
OSCCTRL_PLLxCTRL_ENABLE | OSCCTRL_PLLxCTRL_REFSEL | OSCCTRL_PLLxCTRL_BWSEL,
163-
whal_SetBits(OSCCTRL_PLLxCTRL_ENABLE, 1) |
164-
whal_SetBits(OSCCTRL_PLLxCTRL_REFSEL, oscCtrlCfg->refSel) |
165-
whal_SetBits(OSCCTRL_PLLxCTRL_BWSEL, oscCtrlCfg->bwSel));
183+
OSCCTRL_PLLxCTRL_ENABLE_Msk | OSCCTRL_PLLxCTRL_REFSEL_Msk | OSCCTRL_PLLxCTRL_BWSEL_Msk,
184+
whal_SetBits(OSCCTRL_PLLxCTRL_ENABLE_Msk, OSCCTRL_PLLxCTRL_ENABLE_Pos, 1) |
185+
whal_SetBits(OSCCTRL_PLLxCTRL_REFSEL_Msk, OSCCTRL_PLLxCTRL_REFSEL_Pos, oscCtrlCfg->refSel) |
186+
whal_SetBits(OSCCTRL_PLLxCTRL_BWSEL_Msk, OSCCTRL_PLLxCTRL_BWSEL_Pos, oscCtrlCfg->bwSel));
166187

167188
/* Wait for PLL to lock */
168189
do {
169190
whal_Reg_Get(clkDev->regmap.base, OSCCTRL_STATUS_REG,
170-
OSCCTRL_STATUS_PLLxLOCK(oscCtrlCfg->pllInst), &status);
191+
OSCCTRL_STATUS_PLLxLOCK_Msk(oscCtrlCfg->pllInst),
192+
OSCCTRL_STATUS_PLLxLOCK_Pos(oscCtrlCfg->pllInst), &status);
171193
} while (!status);
172194

173195
/* Configure CPU clock divider in MCLK */
174-
whal_Reg_Update(clkDev->regmap.base, MCLK_DIV1_REG, MCLK_DIV1,
175-
whal_SetBits(MCLK_DIV1, mclkCfg->div));
196+
whal_Reg_Update(clkDev->regmap.base, MCLK_DIV1_REG, MCLK_DIV1_Msk,
197+
whal_SetBits(MCLK_DIV1_Msk, MCLK_DIV1_Pos, mclkCfg->div));
176198

177199
/* Wait for clock divider change to take effect */
178200
do {
179201
whal_Reg_Get(clkDev->regmap.base, MCLK_INTFLAG_REG,
180-
MCLK_INTFLAG_CKRDY, &status);
202+
MCLK_INTFLAG_CKRDY_Msk, MCLK_INTFLAG_CKRDY_Pos, &status);
181203
} while (!status);
182204

183205
/* Configure each GCLK generator with its source and divider */
184206
for (uint8_t i = 0; i < cfg->gclkCfgCount; ++i) {
185207
whal_Pic32czClock_GclkCfg *gclkCfg = &cfg->gclkCfg[i];
186208
whal_Reg_Update(clkDev->regmap.base, GCLK_GENCTRLx_REG(gclkCfg->gen),
187-
GCLK_GENCTRLx_SRC | GCLK_GENCTRLx_GENEN | GCLK_GENCTRLx_DIV,
188-
whal_SetBits(GCLK_GENCTRLx_SRC, gclkCfg->genSrc) |
189-
whal_SetBits(GCLK_GENCTRLx_GENEN, 1) |
190-
whal_SetBits(GCLK_GENCTRLx_DIV, gclkCfg->genDiv));
209+
GCLK_GENCTRLx_SRC_Msk | GCLK_GENCTRLx_GENEN_Msk | GCLK_GENCTRLx_DIV_Msk,
210+
whal_SetBits(GCLK_GENCTRLx_SRC_Msk, GCLK_GENCTRLx_SRC_Pos, gclkCfg->genSrc) |
211+
whal_SetBits(GCLK_GENCTRLx_GENEN_Msk, GCLK_GENCTRLx_GENEN_Pos, 1) |
212+
whal_SetBits(GCLK_GENCTRLx_DIV_Msk, GCLK_GENCTRLx_DIV_Pos, gclkCfg->genDiv));
191213

192214
/* Wait for generator synchronization */
193215
do {
194216
whal_Reg_Get(clkDev->regmap.base, GCLK_SYNCBUSY_REG,
195-
GCLK_SYNCBUSY_GENCTRLx(gclkCfg->gen), &status);
217+
GCLK_SYNCBUSY_GENCTRLx_Msk(gclkCfg->gen),
218+
GCLK_SYNCBUSY_GENCTRLx_Pos(gclkCfg->gen), &status);
196219
} while (status);
197220
}
198221

@@ -224,14 +247,14 @@ whal_Error whal_Pic32czClock_Enable(whal_Clock *clkDev, const void *clk)
224247

225248
/* Enable GCLK peripheral channel and connect to specified generator */
226249
whal_Reg_Update(clkDev->regmap.base, GCLK_PCHCTRLx_REG(pic32Clk->gclkPeriphChannel),
227-
GCLK_PCHCTRLx_GEN | GCLK_PCHCTRLx_CHEN,
228-
whal_SetBits(GCLK_PCHCTRLx_GEN, pic32Clk->gclkPeriphSrc) |
229-
whal_SetBits(GCLK_PCHCTRLx_CHEN, 1));
250+
GCLK_PCHCTRLx_GEN_Msk | GCLK_PCHCTRLx_CHEN_Msk,
251+
whal_SetBits(GCLK_PCHCTRLx_GEN_Msk, GCLK_PCHCTRLx_GEN_Pos, pic32Clk->gclkPeriphSrc) |
252+
whal_SetBits(GCLK_PCHCTRLx_CHEN_Msk, GCLK_PCHCTRLx_CHEN_Pos, 1));
230253

231254
/* Enable bus clock for peripheral in MCLK mask register */
232255
whal_Reg_Update(clkDev->regmap.base, MCLK_CLKxMSK_REG(pic32Clk->mclkEnableInst),
233256
pic32Clk->mclkEnableMask,
234-
whal_SetBits(pic32Clk->mclkEnableMask, 1));
257+
whal_SetBits(pic32Clk->mclkEnableMask, pic32Clk->mclkEnablePos, 1));
235258

236259
return WHAL_SUCCESS;
237260
}
@@ -247,13 +270,13 @@ whal_Error whal_Pic32czClock_Disable(whal_Clock *clkDev, const void *clk)
247270
/* Disable bus clock for peripheral in MCLK mask register */
248271
whal_Reg_Update(clkDev->regmap.base, MCLK_CLKxMSK_REG(pic32Clk->mclkEnableInst),
249272
pic32Clk->mclkEnableMask,
250-
whal_SetBits(pic32Clk->mclkEnableMask, 0));
273+
whal_SetBits(pic32Clk->mclkEnableMask, pic32Clk->mclkEnablePos, 0));
251274

252275
/* Disable GCLK peripheral channel */
253276
whal_Reg_Update(clkDev->regmap.base, GCLK_PCHCTRLx_REG(pic32Clk->gclkPeriphChannel),
254-
GCLK_PCHCTRLx_GEN | GCLK_PCHCTRLx_CHEN,
255-
whal_SetBits(GCLK_PCHCTRLx_GEN, pic32Clk->gclkPeriphSrc) |
256-
whal_SetBits(GCLK_PCHCTRLx_CHEN, 0));
277+
GCLK_PCHCTRLx_GEN_Msk | GCLK_PCHCTRLx_CHEN_Msk,
278+
whal_SetBits(GCLK_PCHCTRLx_GEN_Msk, GCLK_PCHCTRLx_GEN_Pos, pic32Clk->gclkPeriphSrc) |
279+
whal_SetBits(GCLK_PCHCTRLx_CHEN_Msk, GCLK_PCHCTRLx_CHEN_Pos, 0));
257280

258281
return WHAL_SUCCESS;
259282
}

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