diff --git a/examples/pic32cz/pic32cz_curiosity_ultra.c b/examples/pic32cz/pic32cz_curiosity_ultra.c index b95b232..91e9991 100644 --- a/examples/pic32cz/pic32cz_curiosity_ultra.c +++ b/examples/pic32cz/pic32cz_curiosity_ultra.c @@ -23,8 +23,10 @@ whal_Clock g_whalClock = { .outCfgCount = 1, .outCfg = &(whal_Pic32czClockPll_OutCfg) { - .postDivMask = WHAL_PIC32CZ_POSTDIVMASK0, - .outEnMask = WHAL_PIC32CZ_OUTENMASK0, + .postDivMask = WHAL_PIC32CZ_POSTDIV0_Msk, + .postDivPos = WHAL_PIC32CZ_POSTDIV0_Pos, + .outEnMask = WHAL_PIC32CZ_OUTEN0_Msk, + .outEnPos = WHAL_PIC32CZ_OUTEN0_Pos, .postDiv = 3, }, }, @@ -72,7 +74,8 @@ static whal_Pic32czClock_Clk uartClk = { .gclkPeriphChannel = 25, /* SERCOM 4 */ .gclkPeriphSrc = 0, /* GEN 0 */ .mclkEnableInst = 1, /* Peripheral BUS Clock Enable Mask1 Register */ - .mclkEnableMask = WHAL_MASK(3), /* SERCOM 4 enable mask */ + .mclkEnableMask = (1UL << 3), /* SERCOM 4 enable mask */ + .mclkEnablePos = 3, }; whal_Uart g_whalUart = { diff --git a/src/clock/pic32cz_clock.c b/src/clock/pic32cz_clock.c index 862dd70..dd969cf 100644 --- a/src/clock/pic32cz_clock.c +++ b/src/clock/pic32cz_clock.c @@ -13,103 +13,84 @@ */ /* OSCCTRL - Oscillator Controller (base offset 0x00000) */ -#define PIC32CZ_OSCCTRL 0x00000 +#define OSCCTRL 0x00000 /* PLL Control Register - enables PLL and selects reference/bandwidth */ -#define PIC32CZ_OSCCTRL_PLLxCTRL_REG(pllInst) (0x40 + (pllInst * 20)) -#define PIC32CZ_OSCCTRL_PLLxCTRL_ENABLE WHAL_MASK(1) /* PLL enable */ -#define PIC32CZ_OSCCTRL_PLLxCTRL_REFSEL WHAL_MASK_RANGE(10, 8) /* Reference select */ -#define PIC32CZ_OSCCTRL_PLLxCTRL_BWSEL WHAL_MASK_RANGE(13, 11) /* Bandwidth select */ +#define OSCCTRL_PLLxCTRL_REG(pllInst) (0x40 + (pllInst * 20)) +#define OSCCTRL_PLLxCTRL_ENABLE_Pos 1 /* PLL enable */ +#define OSCCTRL_PLLxCTRL_ENABLE_Msk (1UL << OSCCTRL_PLLxCTRL_ENABLE_Pos) + +#define OSCCTRL_PLLxCTRL_REFSEL_Pos 8 /* Reference select */ +#define OSCCTRL_PLLxCTRL_REFSEL_Msk (WHAL_BITMASK(3) << OSCCTRL_PLLxCTRL_REFSEL_Pos) + +#define OSCCTRL_PLLxCTRL_BWSEL_Pos 11 /* Bandwidth select */ +#define OSCCTRL_PLLxCTRL_BWSEL_Msk (WHAL_BITMASK(3) << OSCCTRL_PLLxCTRL_BWSEL_Pos) /* PLL Feedback Divider Register - sets VCO multiplication factor */ -#define PIC32CZ_OSCCTRL_PLLxFBDIV_REG(pllInst) (0x44 + (pllInst * 20)) -#define PIC32CZ_OSCCTRL_PLLxFBDIV WHAL_MASK_RANGE(9, 0) /* Feedback divider (16-1023) */ +#define OSCCTRL_PLLxFBDIV_REG(pllInst) (0x44 + (pllInst * 20)) +#define OSCCTRL_PLLxFBDIV_Pos 0 /* Feedback divider (16-1023) */ +#define OSCCTRL_PLLxFBDIV_Msk (WHAL_BITMASK(10) << OSCCTRL_PLLxFBDIV_Pos) /* PLL Reference Divider Register - divides input reference clock */ -#define PIC32CZ_OSCCTRL_PLLxREFDIV_REG(pllInst) (0x48 + (pllInst * 20)) -#define PIC32CZ_OSCCTRL_PLLxREFDIV WHAL_MASK_RANGE(5, 0) /* Reference divider (1-63) */ +#define OSCCTRL_PLLxREFDIV_REG(pllInst) (0x48 + (pllInst * 20)) +#define OSCCTRL_PLLxREFDIV_Pos 0 /* Reference divider (1-63) */ +#define OSCCTRL_PLLxREFDIV_Msk (WHAL_BITMASK(6) << OSCCTRL_PLLxREFDIV_Pos) /* PLL Post-Divider A Register - divides VCO for each output */ -#define PIC32CZ_OSCCTRL_PLLxPOSTDIVA_REG(pllInst) (0x4C + (pllInst * 20)) -#define PIC32CZ_OSCCTRL_PLLxPOSTDIVA_POSTDIV0 WHAL_MASK_RANGE(5, 0) /* Output 0 divider */ -#define PIC32CZ_OSCCTRL_PLLxPOSTDIVA_OUTEN0 WHAL_MASK(7) /* Output 0 enable */ +#define OSCCTRL_PLLxPOSTDIVA_REG(pllInst) (0x4C + (pllInst * 20)) +#define OSCCTRL_PLLxPOSTDIVA_POSTDIV0_Pos 0 /* Output 0 divider */ +#define OSCCTRL_PLLxPOSTDIVA_POSTDIV0_Msk (WHAL_BITMASK(6) << OSCCTRL_PLLxPOSTDIVA_POSTDIV0_Pos) + +#define OSCCTRL_PLLxPOSTDIVA_OUTEN0_Pos 7 /* Output 0 enable */ +#define OSCCTRL_PLLxPOSTDIVA_OUTEN0_Msk (1UL << OSCCTRL_PLLxPOSTDIVA_OUTEN0_Pos) /* OSCCTRL Status Register - PLL lock and oscillator ready flags */ -#define PIC32CZ_OSCCTRL_STATUS_REG (PIC32CZ_OSCCTRL + 0x10) -#define PIC32CZ_OSCCTRL_STATUS_PLLxLOCK(pllInst) WHAL_MASK((24 + (pllInst))) +#define OSCCTRL_STATUS_REG (OSCCTRL + 0x10) +#define OSCCTRL_STATUS_PLLxLOCK_Pos(pllInst) (24 + (pllInst)) +#define OSCCTRL_STATUS_PLLxLOCK_Msk(pllInst) (1UL << (OSCCTRL_STATUS_PLLxLOCK_Pos(pllInst))) /* GCLK - Generic Clock Controller (base offset 0x10000) */ -#define PIC32CZ_GCLK 0x10000 +#define GCLK 0x10000 /* Generator Control Register - configures clock source and divider per generator */ -#define PIC32CZ_GCLK_GENCTRLx_REG(gclkInst) ((PIC32CZ_GCLK + 0x20 + (gclkInst * 0x4))) -#define PIC32CZ_GCLK_GENCTRLx_SRC WHAL_MASK_RANGE(4, 0) /* Source selection */ -#define PIC32CZ_GCLK_GENCTRLx_GENEN WHAL_MASK(8) /* Generator enable */ -#define PIC32CZ_GCLK_GENCTRLx_DIV WHAL_MASK_RANGE(31, 16) /* Division factor */ +#define GCLK_GENCTRLx_REG(gclkInst) ((GCLK + 0x20 + (gclkInst * 0x4))) +#define GCLK_GENCTRLx_SRC_Pos 0 /* Source selection */ +#define GCLK_GENCTRLx_SRC_Msk (WHAL_BITMASK(5) << GCLK_GENCTRLx_SRC_Pos) + +#define GCLK_GENCTRLx_GENEN_Pos 8 /* Generator enable */ +#define GCLK_GENCTRLx_GENEN_Msk (1UL << GCLK_GENCTRLx_GENEN_Pos) + +#define GCLK_GENCTRLx_DIV_Pos 16 /* Division factor */ +#define GCLK_GENCTRLx_DIV_Msk (WHAL_BITMASK(16) << GCLK_GENCTRLx_DIV_Pos) /* Peripheral Channel Control Register - connects generator to peripheral */ -#define PIC32CZ_GCLK_PCHCTRLx_REG(periphChannel) (PIC32CZ_GCLK + 0x80 + (periphChannel * 0x4)) -#define PIC32CZ_GCLK_PCHCTRLx_GEN WHAL_MASK_RANGE(3, 0) /* Generator selection */ -#define PIC32CZ_GCLK_PCHCTRLx_CHEN WHAL_MASK(6) /* Channel enable */ +#define GCLK_PCHCTRLx_REG(periphChannel) (GCLK + 0x80 + (periphChannel * 0x4)) +#define GCLK_PCHCTRLx_GEN_Pos 0 /* Generator selection */ +#define GCLK_PCHCTRLx_GEN_Msk (WHAL_BITMASK(4) << GCLK_PCHCTRLx_GEN_Pos) + +#define GCLK_PCHCTRLx_CHEN_Pos 6 /* Channel enable */ +#define GCLK_PCHCTRLx_CHEN_Msk (1UL << GCLK_PCHCTRLx_CHEN_Pos) /* GCLK Synchronization Busy Register - poll after writing GENCTRLx */ -#define PIC32CZ_GCLK_SYNCBUSY_REG (PIC32CZ_GCLK + 0x04) -#define PIC32CZ_GCLK_SYNCBUSY_GENCTRLx(gclkInst) WHAL_MASK((2 + (gclkInst))) +#define GCLK_SYNCBUSY_REG (GCLK + 0x04) +#define GCLK_SYNCBUSY_GENCTRLx_Pos(gclkInst) (2 + (gclkInst)) +#define GCLK_SYNCBUSY_GENCTRLx_Msk(gclkInst) (1UL << (GCLK_SYNCBUSY_GENCTRLx_Pos(gclkInst))) /* MCLK - Main Clock Controller (base offset 0x12000) */ -#define PIC32CZ_MCLK 0x12000 +#define MCLK 0x12000 /* MCLK Interrupt Flag Register - clock ready status */ -#define PIC32CZ_MCLK_INTFLAG_REG (PIC32CZ_MCLK + 0x08) -#define PIC32CZ_MCLK_INTFLAG_CKRDY WHAL_MASK(0) /* Clock ready */ +#define MCLK_INTFLAG_REG (MCLK + 0x08) +#define MCLK_INTFLAG_CKRDY_Pos 0 /* Clock ready */ +#define MCLK_INTFLAG_CKRDY_Msk (1UL << MCLK_INTFLAG_CKRDY_Pos) /* CPU Clock Divider Register */ -#define PIC32CZ_MCLK_DIV1_REG (PIC32CZ_MCLK + 0x10) -#define PIC32CZ_MCLK_DIV1 WHAL_MASK_RANGE(7, 0) /* CPU clock divider */ +#define MCLK_DIV1_REG (MCLK + 0x10) +#define MCLK_DIV1_Pos 0 /* CPU clock divider */ +#define MCLK_DIV1_Msk (WHAL_BITMASK(8) << MCLK_DIV1_Pos) /* Peripheral Clock Mask Registers - enable/disable bus clocks to peripherals */ -#define PIC32CZ_MCLK_CLKxMSK_REG(enableInst) (PIC32CZ_MCLK + 0x3C + (enableInst * 0x4)) - -/* - * Example configuration for 150MHz CPU clock from DFLL48M: - * - * whal_Clock clk = { - * .regmap = { .base = 0x44000000 }, // Clock controller base - * .driver = &whal_Pic32czClockPll_Driver, - * .cfg = &(whal_Pic32czClock_Cfg) { - * .oscCtrlCfg = &(whal_Pic32czClockPll_OscCtrlCfg) { - * .pllInst = WHAL_PIC32CZ_PLL0, - * .refSel = WHAL_PIC32CZ_REFSEL_DFLL48M, - * .bwSel = WHAL_PIC32CZ_BWSEL_10MHz_TO_20MHz, - * .fbDiv = 225, // VCO = (48MHz / 12) * 225 = 900MHz - * .refDiv = 12, - * .outCfgCount = 1, - * .outCfg = &(whal_Pic32czClockPll_OutCfg) { - * .postDivMask = WHAL_PIC32CZ_POSTDIVMASK0, - * .outEnMask = WHAL_PIC32CZ_OUTENMASK0, - * .postDiv = 3, // 900MHz / 3 = 300MHz - * }, - * }, - * .mclkCfg = &(whal_Pic32czClock_MclkCfg) { - * .div = 2, // CPU clock = 300MHz / 2 = 150MHz - * }, - * .gclkCfgCount = 1, - * .gclkCfg = &(whal_Pic32czClock_GclkCfg) { - * .gen = 0, - * .genSrc = WHAL_PIC32CZ_GENSRC_PLL0_CLOCKOUT0, - * .genDiv = 1, - * }, - * }, - * }; - * - * // Peripheral clock for SERCOM0 - * whal_Pic32czClock_Clk sercom0Clk = { - * .gclkPeriphChannel = 23, // SERCOM0_CORE - * .gclkPeriphSrc = 0, // Use generator 0 - * .mclkEnableInst = 2, // APBBMASK register - * .mclkEnableMask = WHAL_MASK(1), // SERCOM0 bit - * }; - */ +#define MCLK_CLKxMSK_REG(enableInst) (MCLK + 0x3C + (enableInst * 0x4)) whal_Error whal_Pic32czClockPll_Init(whal_Clock *clkDev) { @@ -132,67 +113,69 @@ whal_Error whal_Pic32czClockPll_Init(whal_Clock *clkDev) mclkCfg = cfg->mclkCfg; /* Calculate register addresses for the selected PLL instance */ - PLLxCTRL_REG = PIC32CZ_OSCCTRL_PLLxCTRL_REG(oscCtrlCfg->pllInst); - PLLxFBDIV_REG = PIC32CZ_OSCCTRL_PLLxFBDIV_REG(oscCtrlCfg->pllInst); - PLLxREFDIV_REG = PIC32CZ_OSCCTRL_PLLxREFDIV_REG(oscCtrlCfg->pllInst); - PLLxPOSTDIVA_REG = PIC32CZ_OSCCTRL_PLLxPOSTDIVA_REG(oscCtrlCfg->pllInst); + PLLxCTRL_REG = OSCCTRL_PLLxCTRL_REG(oscCtrlCfg->pllInst); + PLLxFBDIV_REG = OSCCTRL_PLLxFBDIV_REG(oscCtrlCfg->pllInst); + PLLxREFDIV_REG = OSCCTRL_PLLxREFDIV_REG(oscCtrlCfg->pllInst); + PLLxPOSTDIVA_REG = OSCCTRL_PLLxPOSTDIVA_REG(oscCtrlCfg->pllInst); /* Enable power supply for the PLL */ whal_Supply_Enable(oscCtrlCfg->supplyCtrl, oscCtrlCfg->supply); /* Configure PLL feedback divider (sets VCO multiplication factor) */ - whal_Reg_Update(clkDev->regmap.base, PLLxFBDIV_REG, PIC32CZ_OSCCTRL_PLLxFBDIV, - whal_SetBits(PIC32CZ_OSCCTRL_PLLxFBDIV, oscCtrlCfg->fbDiv)); + whal_Reg_Update(clkDev->regmap.base, PLLxFBDIV_REG, OSCCTRL_PLLxFBDIV_Msk, + whal_SetBits(OSCCTRL_PLLxFBDIV_Msk, OSCCTRL_PLLxFBDIV_Pos, oscCtrlCfg->fbDiv)); /* Configure PLL reference divider (divides input clock before PLL) */ - whal_Reg_Update(clkDev->regmap.base, PLLxREFDIV_REG, PIC32CZ_OSCCTRL_PLLxREFDIV, - whal_SetBits(PIC32CZ_OSCCTRL_PLLxREFDIV, oscCtrlCfg->refDiv)); + whal_Reg_Update(clkDev->regmap.base, PLLxREFDIV_REG, OSCCTRL_PLLxREFDIV_Msk, + whal_SetBits(OSCCTRL_PLLxREFDIV_Msk, OSCCTRL_PLLxREFDIV_Pos, oscCtrlCfg->refDiv)); /* Configure each PLL output with its post-divider and enable it */ for (uint8_t i = 0; i < oscCtrlCfg->outCfgCount; ++i) { whal_Pic32czClockPll_OutCfg *outCfg = &oscCtrlCfg->outCfg[i]; whal_Reg_Update(clkDev->regmap.base, PLLxPOSTDIVA_REG, outCfg->outEnMask | outCfg->postDivMask, - whal_SetBits(outCfg->outEnMask, 1) | - whal_SetBits(outCfg->postDivMask, outCfg->postDiv)); + whal_SetBits(outCfg->postDivMask, outCfg->postDivPos, outCfg->postDiv) | + whal_SetBits(outCfg->outEnMask, outCfg->outEnPos, 1)); } /* Enable PLL with selected reference source and loop filter bandwidth */ whal_Reg_Update(clkDev->regmap.base, PLLxCTRL_REG, - PIC32CZ_OSCCTRL_PLLxCTRL_ENABLE | PIC32CZ_OSCCTRL_PLLxCTRL_REFSEL | PIC32CZ_OSCCTRL_PLLxCTRL_BWSEL, - whal_SetBits(PIC32CZ_OSCCTRL_PLLxCTRL_ENABLE, 1) | - whal_SetBits(PIC32CZ_OSCCTRL_PLLxCTRL_REFSEL, oscCtrlCfg->refSel) | - whal_SetBits(PIC32CZ_OSCCTRL_PLLxCTRL_BWSEL, oscCtrlCfg->bwSel)); + OSCCTRL_PLLxCTRL_ENABLE_Msk | OSCCTRL_PLLxCTRL_REFSEL_Msk | OSCCTRL_PLLxCTRL_BWSEL_Msk, + whal_SetBits(OSCCTRL_PLLxCTRL_ENABLE_Msk, OSCCTRL_PLLxCTRL_ENABLE_Pos, 1) | + whal_SetBits(OSCCTRL_PLLxCTRL_REFSEL_Msk, OSCCTRL_PLLxCTRL_REFSEL_Pos, oscCtrlCfg->refSel) | + whal_SetBits(OSCCTRL_PLLxCTRL_BWSEL_Msk, OSCCTRL_PLLxCTRL_BWSEL_Pos, oscCtrlCfg->bwSel)); /* Wait for PLL to lock */ do { - whal_Reg_Get(clkDev->regmap.base, PIC32CZ_OSCCTRL_STATUS_REG, - PIC32CZ_OSCCTRL_STATUS_PLLxLOCK(oscCtrlCfg->pllInst), &status); + whal_Reg_Get(clkDev->regmap.base, OSCCTRL_STATUS_REG, + OSCCTRL_STATUS_PLLxLOCK_Msk(oscCtrlCfg->pllInst), + OSCCTRL_STATUS_PLLxLOCK_Pos(oscCtrlCfg->pllInst), &status); } while (!status); /* Configure CPU clock divider in MCLK */ - whal_Reg_Update(clkDev->regmap.base, PIC32CZ_MCLK_DIV1_REG, PIC32CZ_MCLK_DIV1, - whal_SetBits(PIC32CZ_MCLK_DIV1, mclkCfg->div)); + whal_Reg_Update(clkDev->regmap.base, MCLK_DIV1_REG, MCLK_DIV1_Msk, + whal_SetBits(MCLK_DIV1_Msk, MCLK_DIV1_Pos, mclkCfg->div)); /* Wait for clock divider change to take effect */ do { - whal_Reg_Get(clkDev->regmap.base, PIC32CZ_MCLK_INTFLAG_REG, - PIC32CZ_MCLK_INTFLAG_CKRDY, &status); + whal_Reg_Get(clkDev->regmap.base, MCLK_INTFLAG_REG, + MCLK_INTFLAG_CKRDY_Msk, MCLK_INTFLAG_CKRDY_Pos, &status); } while (!status); /* Configure each GCLK generator with its source and divider */ for (uint8_t i = 0; i < cfg->gclkCfgCount; ++i) { whal_Pic32czClock_GclkCfg *gclkCfg = &cfg->gclkCfg[i]; - whal_Reg_Update(clkDev->regmap.base, PIC32CZ_GCLK_GENCTRLx_REG(gclkCfg->gen), - PIC32CZ_GCLK_GENCTRLx_SRC | PIC32CZ_GCLK_GENCTRLx_GENEN | PIC32CZ_GCLK_GENCTRLx_DIV, - whal_SetBits(PIC32CZ_GCLK_GENCTRLx_SRC, gclkCfg->genSrc) | - whal_SetBits(PIC32CZ_GCLK_GENCTRLx_GENEN, 1) | - whal_SetBits(PIC32CZ_GCLK_GENCTRLx_DIV, gclkCfg->genDiv)); + whal_Reg_Update(clkDev->regmap.base, GCLK_GENCTRLx_REG(gclkCfg->gen), + GCLK_GENCTRLx_SRC_Msk | GCLK_GENCTRLx_GENEN_Msk | GCLK_GENCTRLx_DIV_Msk, + whal_SetBits(GCLK_GENCTRLx_SRC_Msk, GCLK_GENCTRLx_SRC_Pos, gclkCfg->genSrc) | + whal_SetBits(GCLK_GENCTRLx_GENEN_Msk, GCLK_GENCTRLx_GENEN_Pos, 1) | + whal_SetBits(GCLK_GENCTRLx_DIV_Msk, GCLK_GENCTRLx_DIV_Pos, gclkCfg->genDiv)); /* Wait for generator synchronization */ do { - whal_Reg_Get(clkDev->regmap.base, PIC32CZ_GCLK_SYNCBUSY_REG, - PIC32CZ_GCLK_SYNCBUSY_GENCTRLx(gclkCfg->gen), &status); + whal_Reg_Get(clkDev->regmap.base, GCLK_SYNCBUSY_REG, + GCLK_SYNCBUSY_GENCTRLx_Msk(gclkCfg->gen), + GCLK_SYNCBUSY_GENCTRLx_Pos(gclkCfg->gen), &status); } while (status); } @@ -223,15 +206,15 @@ whal_Error whal_Pic32czClock_Enable(whal_Clock *clkDev, const void *clk) */ /* Enable GCLK peripheral channel and connect to specified generator */ - whal_Reg_Update(clkDev->regmap.base, PIC32CZ_GCLK_PCHCTRLx_REG(pic32Clk->gclkPeriphChannel), - PIC32CZ_GCLK_PCHCTRLx_GEN | PIC32CZ_GCLK_PCHCTRLx_CHEN, - whal_SetBits(PIC32CZ_GCLK_PCHCTRLx_GEN, pic32Clk->gclkPeriphSrc) | - whal_SetBits(PIC32CZ_GCLK_PCHCTRLx_CHEN, 1)); + whal_Reg_Update(clkDev->regmap.base, GCLK_PCHCTRLx_REG(pic32Clk->gclkPeriphChannel), + GCLK_PCHCTRLx_GEN_Msk | GCLK_PCHCTRLx_CHEN_Msk, + whal_SetBits(GCLK_PCHCTRLx_GEN_Msk, GCLK_PCHCTRLx_GEN_Pos, pic32Clk->gclkPeriphSrc) | + whal_SetBits(GCLK_PCHCTRLx_CHEN_Msk, GCLK_PCHCTRLx_CHEN_Pos, 1)); /* Enable bus clock for peripheral in MCLK mask register */ - whal_Reg_Update(clkDev->regmap.base, PIC32CZ_MCLK_CLKxMSK_REG(pic32Clk->mclkEnableInst), + whal_Reg_Update(clkDev->regmap.base, MCLK_CLKxMSK_REG(pic32Clk->mclkEnableInst), pic32Clk->mclkEnableMask, - whal_SetBits(pic32Clk->mclkEnableMask, 1)); + whal_SetBits(pic32Clk->mclkEnableMask, pic32Clk->mclkEnablePos, 1)); return WHAL_SUCCESS; } @@ -245,15 +228,15 @@ whal_Error whal_Pic32czClock_Disable(whal_Clock *clkDev, const void *clk) } /* Disable bus clock for peripheral in MCLK mask register */ - whal_Reg_Update(clkDev->regmap.base, PIC32CZ_MCLK_CLKxMSK_REG(pic32Clk->mclkEnableInst), + whal_Reg_Update(clkDev->regmap.base, MCLK_CLKxMSK_REG(pic32Clk->mclkEnableInst), pic32Clk->mclkEnableMask, - whal_SetBits(pic32Clk->mclkEnableMask, 0)); + whal_SetBits(pic32Clk->mclkEnableMask, pic32Clk->mclkEnablePos, 0)); /* Disable GCLK peripheral channel */ - whal_Reg_Update(clkDev->regmap.base, PIC32CZ_GCLK_PCHCTRLx_REG(pic32Clk->gclkPeriphChannel), - PIC32CZ_GCLK_PCHCTRLx_GEN | PIC32CZ_GCLK_PCHCTRLx_CHEN, - whal_SetBits(PIC32CZ_GCLK_PCHCTRLx_GEN, pic32Clk->gclkPeriphSrc) | - whal_SetBits(PIC32CZ_GCLK_PCHCTRLx_CHEN, 0)); + whal_Reg_Update(clkDev->regmap.base, GCLK_PCHCTRLx_REG(pic32Clk->gclkPeriphChannel), + GCLK_PCHCTRLx_GEN_Msk | GCLK_PCHCTRLx_CHEN_Msk, + whal_SetBits(GCLK_PCHCTRLx_GEN_Msk, GCLK_PCHCTRLx_GEN_Pos, pic32Clk->gclkPeriphSrc) | + whal_SetBits(GCLK_PCHCTRLx_CHEN_Msk, GCLK_PCHCTRLx_CHEN_Pos, 0)); return WHAL_SUCCESS; } diff --git a/src/clock/stm32wb_rcc.c b/src/clock/stm32wb_rcc.c index de33c34..94da36d 100644 --- a/src/clock/stm32wb_rcc.c +++ b/src/clock/stm32wb_rcc.c @@ -16,68 +16,129 @@ */ /* Clock Control Register - oscillator enables and status */ -#define ST_RCC_CR_REG 0x000 -#define ST_RCC_CR_MSIRANGE WHAL_MASK_RANGE(7, 4) /* MSI frequency range */ -#define ST_RCC_CR_HSION_MASK WHAL_MASK(8) /* HSI enable */ -#define ST_RCC_CR_PLLON_MASK WHAL_MASK(24) /* PLL enable */ +#define RCC_CR_REG 0x000 +#define RCC_CR_MSIRANGE_Pos 4 /* MSI frequency range */ +#define RCC_CR_MSIRANGE_Msk (WHAL_BITMASK(4) << RCC_CR_MSIRANGE_Pos) + +#define RCC_CR_HSION_Pos 8 /* HSI enable */ +#define RCC_CR_HSION_Msk (1UL << RCC_CR_HSION_Pos) + +#define RCC_CR_PLLON_Pos 24 /* PLL enable */ +#define RCC_CR_PLLON_Msk (1UL << RCC_CR_PLLON_Pos) /* Clock Configuration Register - clock source and prescaler selection */ -#define ST_RCC_CFGR_REG 0x008 -#define ST_RCC_CFGR_SW WHAL_MASK_RANGE(1, 0) /* System clock switch */ -#define ST_RCC_CFGR_SWS WHAL_MASK_RANGE(3, 2) /* System clock switch status */ -#define ST_RCC_CFGR_HPRE WHAL_MASK_RANGE(7, 4) /* AHB prescaler */ -#define ST_RCC_CFGR_PPRE1 WHAL_MASK_RANGE(10, 8) /* APB1 prescaler */ -#define ST_RCC_CFGR_PPRE2 WHAL_MASK_RANGE(13, 11) /* APB2 prescaler */ -#define ST_RCC_CFGR_STOPWUCK WHAL_MASK(15) /* Wakeup clock after stop */ -#define ST_RCC_CFGR_HPREF WHAL_MASK(16) /* AHB prescaler flag */ -#define ST_RCC_CFGR_PPRE1F WHAL_MASK(17) /* APB1 prescaler flag */ -#define ST_RCC_CFGR_PPRE2F WHAL_MASK(18) /* APB2 prescaler flag */ -#define ST_RCC_CFGR_MCOSEL WHAL_MASK_RANGE(27, 24) /* MCO source selection */ -#define ST_RCC_CFGR_MCOPRE WHAL_MASK_RANGE(30, 28) /* MCO prescaler */ +#define RCC_CFGR_REG 0x008 +#define RCC_CFGR_SW_Pos 0 /* System clock switch */ +#define RCC_CFGR_SW_Msk (WHAL_BITMASK(2) << RCC_CFGR_SW_Pos) + +#define RCC_CFGR_SWS_Pos 2 /* System clock switch status */ +#define RCC_CFGR_SWS_Msk (WHAL_BITMASK(2) << RCC_CFGR_SWS_Pos) + +#define RCC_CFGR_HPRE_Pos 4 /* AHB prescaler */ +#define RCC_CFGR_HPRE_Msk (WHAL_BITMASK(4) << RCC_CFGR_HPRE_Pos) + +#define RCC_CFGR_PPRE1_Pos 8 /* APB1 prescaler */ +#define RCC_CFGR_PPRE1_Msk (WHAL_BITMASK(3) << RCC_CFGR_PPRE1_Pos) + +#define RCC_CFGR_PPRE2_Pos 11 /* APB2 prescaler */ +#define RCC_CFGR_PPRE2_Msk (WHAL_BITMASK(3) << RCC_CFGR_PPRE2_Pos) + +#define RCC_CFGR_STOPWUCK_Pos 15 /* Wakeup clock after stop */ +#define RCC_CFGR_STOPWUCK_Msk (1UL << RCC_CFGR_STOPWUCK_Pos) + +#define RCC_CFGR_HPREF_Pos 16 /* AHB prescaler flag */ +#define RCC_CFGR_HPREF_Msk (1UL << RCC_CFGR_HPREF_Pos) + +#define RCC_CFGR_PPRE1F_Pos 17 /* APB1 prescaler flag */ +#define RCC_CFGR_PPRE1F_Msk (1UL << RCC_CFGR_PPRE1F_Pos) + +#define RCC_CFGR_PPRE2F_Pos 18 /* APB2 prescaler flag */ +#define RCC_CFGR_PPRE2F_Msk (1UL << RCC_CFGR_PPRE2F_Pos) + +#define RCC_CFGR_MCOSEL_Pos 24 /* MCO source selection */ +#define RCC_CFGR_MCOSEL_Msk (WHAL_BITMASK(4) << RCC_CFGR_MCOSEL_Pos) + +#define RCC_CFGR_MCOPRE_Pos 28 /* MCO prescaler */ +#define RCC_CFGR_MCOPRE_Msk (WHAL_BITMASK(3) << RCC_CFGR_MCOPRE_Pos) /* PLL Configuration Register */ -#define ST_RCC_PLLCFGR_REG 0x00C -#define ST_RCC_PLLCFGR_PLLSRC_MASK WHAL_MASK_RANGE(1, 0) /* PLL input source */ -#define ST_RCC_PLLCFGR_PLLM_MASK WHAL_MASK_RANGE(6, 4) /* PLL input divider */ -#define ST_RCC_PLLCFGR_PLLN_MASK WHAL_MASK_RANGE(14, 8) /* PLL VCO multiplier */ -#define ST_RCC_PLLCFGR_PLLP_MASK WHAL_MASK_RANGE(21, 17) /* PLLP output divider */ -#define ST_RCC_PLLCFGR_PLLQ_MASK WHAL_MASK_RANGE(27, 25) /* PLLQ output divider */ -#define ST_RCC_PLLCFGR_PLLREN_MASK WHAL_MASK(28) /* PLLR output enable */ -#define ST_RCC_PLLCFGR_PLLR_MASK WHAL_MASK_RANGE(31, 29) /* PLLR output divider */ - -#define ST_RCC_PLLCFGR_MASK \ - ST_RCC_PLLCFGR_PLLSRC_MASK | \ - ST_RCC_PLLCFGR_PLLM_MASK | \ - ST_RCC_PLLCFGR_PLLN_MASK | \ - ST_RCC_PLLCFGR_PLLP_MASK | \ - ST_RCC_PLLCFGR_PLLQ_MASK | \ - ST_RCC_PLLCFGR_PLLREN_MASK | \ - ST_RCC_PLLCFGR_PLLR_MASK +#define RCC_PLLCFGR_REG 0x00C +#define RCC_PLLCFGR_PLLSRC_Pos 0 /* PLL input source */ +#define RCC_PLLCFGR_PLLSRC_Msk (WHAL_BITMASK(2) << RCC_PLLCFGR_PLLSRC_Pos) + +#define RCC_PLLCFGR_PLLM_Pos 4 /* PLL input divider */ +#define RCC_PLLCFGR_PLLM_Msk (WHAL_BITMASK(3) << RCC_PLLCFGR_PLLM_Pos) + +#define RCC_PLLCFGR_PLLN_Pos 8 /* PLL VCO multiplier */ +#define RCC_PLLCFGR_PLLN_Msk (WHAL_BITMASK(7) << RCC_PLLCFGR_PLLN_Pos) + +#define RCC_PLLCFGR_PLLP_Pos 17 /* PLLP output divider */ +#define RCC_PLLCFGR_PLLP_Msk (WHAL_BITMASK(5) << RCC_PLLCFGR_PLLP_Pos) + +#define RCC_PLLCFGR_PLLQ_Pos 25 /* PLLQ output divider */ +#define RCC_PLLCFGR_PLLQ_Msk (WHAL_BITMASK(3) << RCC_PLLCFGR_PLLQ_Pos) + +#define RCC_PLLCFGR_PLLREN_Pos 28 /* PLLR output enable */ +#define RCC_PLLCFGR_PLLREN_Msk (1UL << RCC_PLLCFGR_PLLREN_Pos) + +#define RCC_PLLCFGR_PLLR_Pos 29 /* PLLR output divider */ +#define RCC_PLLCFGR_PLLR_Msk (WHAL_BITMASK(3) << RCC_PLLCFGR_PLLR_Pos) + +#define RCC_PLLCFGR_Msk \ + (RCC_PLLCFGR_PLLSRC_Msk | \ + RCC_PLLCFGR_PLLM_Msk | \ + RCC_PLLCFGR_PLLN_Msk | \ + RCC_PLLCFGR_PLLP_Msk | \ + RCC_PLLCFGR_PLLQ_Msk | \ + RCC_PLLCFGR_PLLREN_Msk | \ + RCC_PLLCFGR_PLLR_Msk) /* AHB2 Peripheral Clock Enable Register */ -#define ST_RCC_AHB2ENR_REG 0x04C -#define ST_RCC_AHB2ENR_GPIOAEN WHAL_MASK(0) /* GPIOA clock enable */ -#define ST_RCC_AHB2ENR_GPIOBEN WHAL_MASK(1) /* GPIOB clock enable */ -#define ST_RCC_AHB2ENR_GPIOCEN WHAL_MASK(2) /* GPIOC clock enable */ -#define ST_RCC_AHB2ENR_GPIODEN WHAL_MASK(3) /* GPIOD clock enable */ -#define ST_RCC_AHB2ENR_GPIOEEN WHAL_MASK(4) /* GPIOE clock enable */ -#define ST_RCC_AHB2ENR_GPIOHEN WHAL_MASK(7) /* GPIOH clock enable */ -#define ST_RCC_AHB2ENR_ADCEN WHAL_MASK(13) /* ADC clock enable */ -#define ST_RCC_AHB2ENR_AES1EN WHAL_MASK(16) /* AES1 clock enable */ +#define RCC_AHB2ENR_REG 0x04C +#define RCC_AHB2ENR_GPIOAEN_Pos 0 /* GPIOA clock enable */ +#define RCC_AHB2ENR_GPIOAEN_Msk (1UL << RCC_AHB2ENR_GPIOAEN_Pos) + +#define RCC_AHB2ENR_GPIOBEN_Pos 1 /* GPIOB clock enable */ +#define RCC_AHB2ENR_GPIOBEN_Msk (1UL << RCC_AHB2ENR_GPIOBEN_Pos) + +#define RCC_AHB2ENR_GPIOCEN_Pos 2 /* GPIOC clock enable */ +#define RCC_AHB2ENR_GPIOCEN_Msk (1UL << RCC_AHB2ENR_GPIOCEN_Pos) + +#define RCC_AHB2ENR_GPIODEN_Pos 3 /* GPIOD clock enable */ +#define RCC_AHB2ENR_GPIODEN_Msk (1UL << RCC_AHB2ENR_GPIODEN_Pos) + +#define RCC_AHB2ENR_GPIOEEN_Pos 4 /* GPIOE clock enable */ +#define RCC_AHB2ENR_GPIOEEN_Msk (1UL << RCC_AHB2ENR_GPIOEEN_Pos) + +#define RCC_AHB2ENR_GPIOHEN_Pos 7 /* GPIOH clock enable */ +#define RCC_AHB2ENR_GPIOHEN_Msk (1UL << RCC_AHB2ENR_GPIOHEN_Pos) + +#define RCC_AHB2ENR_ADCEN_Pos 13 /* ADC clock enable */ +#define RCC_AHB2ENR_ADCEN_Msk (1UL << RCC_AHB2ENR_ADCEN_Pos) + +#define RCC_AHB2ENR_AES1EN_Pos 16 /* AES1 clock enable */ +#define RCC_AHB2ENR_AES1EN_Msk (1UL << RCC_AHB2ENR_AES1EN_Pos) /* AHB3 Peripheral Clock Enable Register */ -#define ST_RCC_AHB3ENR_REG 0x50 -#define ST_RCC_AHB3ENR_FLASHEN WHAL_MASK(25) /* Flash interface clock enable */ +#define RCC_AHB3ENR_REG 0x50 +#define RCC_AHB3ENR_FLASHEN_Pos 25 /* Flash interface clock enable */ +#define RCC_AHB3ENR_FLASHEN_Msk (1UL << RCC_AHB3ENR_FLASHEN_Pos) /* APB1 Peripheral Clock Enable Register 2 */ -#define ST_RCC_APB1ENR2_REG 0x05C -#define ST_RCC_APB1ENR2_LPUART1EN WHAL_MASK(0) /* LPUART1 clock enable */ -#define ST_RCC_APB1ENR2_LPTIM2EN WHAL_MASK(5) /* LPTIM2 clock enable */ +#define RCC_APB1ENR2_REG 0x05C +#define RCC_APB1ENR2_LPUART1EN_Pos 0 /* LPUART1 clock enable */ +#define RCC_APB1ENR2_LPUART1EN_Msk (1UL << RCC_APB1ENR2_LPUART1EN_Pos) + +#define RCC_APB1ENR2_LPTIM2EN_Pos 5 /* LPTIM2 clock enable */ +#define RCC_APB1ENR2_LPTIM2EN_Msk (1UL << RCC_APB1ENR2_LPTIM2EN_Pos) /* Clock Recovery RC Register - HSI48 oscillator control */ -#define ST_RCC_CRRCR_REG 0x098 -#define ST_RCC_CRRCR_HSI48ON_MASK WHAL_MASK(0) /* HSI48 oscillator enable */ -#define ST_RCC_CRRCR_HSI48RDY_MASK WHAL_MASK(1) /* HSI48 oscillator ready */ +#define RCC_CRRCR_REG 0x098 +#define RCC_CRRCR_HSI48ON_Pos 0 /* HSI48 oscillator enable */ +#define RCC_CRRCR_HSI48ON_Msk (1UL << RCC_CRRCR_HSI48ON_Pos) + +#define RCC_CRRCR_HSI48RDY_Pos 1 /* HSI48 oscillator ready */ +#define RCC_CRRCR_HSI48RDY_Msk (1UL << RCC_CRRCR_HSI48RDY_Pos) whal_Error whal_Stm32wbRccPll_Init(whal_Clock *clkDev) { @@ -101,24 +162,24 @@ whal_Error whal_Stm32wbRccPll_Init(whal_Clock *clkDev) } /* Select system clock source (PLL in this case) */ - whal_Reg_Update(clkDev->regmap.base, ST_RCC_CFGR_REG, ST_RCC_CFGR_SW, - whal_SetBits(ST_RCC_CFGR_SW, cfg->sysClkSrc)); + whal_Reg_Update(clkDev->regmap.base, RCC_CFGR_REG, RCC_CFGR_SW_Msk, + whal_SetBits(RCC_CFGR_SW_Msk, RCC_CFGR_SW_Pos, cfg->sysClkSrc)); /* Configure PLL: source, dividers, and multiplier */ whal_Reg_Update(clkDev->regmap.base, - ST_RCC_PLLCFGR_REG, ST_RCC_PLLCFGR_MASK, - whal_SetBits(ST_RCC_PLLCFGR_PLLSRC_MASK, pllCfg->clkSrc) | - whal_SetBits(ST_RCC_PLLCFGR_PLLM_MASK, pllCfg->m) | - whal_SetBits(ST_RCC_PLLCFGR_PLLN_MASK, pllCfg->n) | - whal_SetBits(ST_RCC_PLLCFGR_PLLP_MASK, pllCfg->p) | - whal_SetBits(ST_RCC_PLLCFGR_PLLQ_MASK, pllCfg->q) | - whal_SetBits(ST_RCC_PLLCFGR_PLLREN_MASK, 1) | - whal_SetBits(ST_RCC_PLLCFGR_PLLR_MASK, pllCfg->r)); + RCC_PLLCFGR_REG, RCC_PLLCFGR_Msk, + whal_SetBits(RCC_PLLCFGR_PLLSRC_Msk, RCC_PLLCFGR_PLLSRC_Pos, pllCfg->clkSrc) | + whal_SetBits(RCC_PLLCFGR_PLLM_Msk, RCC_PLLCFGR_PLLM_Pos, pllCfg->m) | + whal_SetBits(RCC_PLLCFGR_PLLN_Msk, RCC_PLLCFGR_PLLN_Pos, pllCfg->n) | + whal_SetBits(RCC_PLLCFGR_PLLP_Msk, RCC_PLLCFGR_PLLP_Pos, pllCfg->p) | + whal_SetBits(RCC_PLLCFGR_PLLQ_Msk, RCC_PLLCFGR_PLLQ_Pos, pllCfg->q) | + whal_SetBits(RCC_PLLCFGR_PLLREN_Msk, RCC_PLLCFGR_PLLREN_Pos, 1) | + whal_SetBits(RCC_PLLCFGR_PLLR_Msk, RCC_PLLCFGR_PLLR_Pos, pllCfg->r)); /* Enable the PLL */ - whal_Reg_Update(clkDev->regmap.base, ST_RCC_CR_REG, - ST_RCC_CR_PLLON_MASK, - whal_SetBits(ST_RCC_CR_PLLON_MASK, 1)); + whal_Reg_Update(clkDev->regmap.base, RCC_CR_REG, + RCC_CR_PLLON_Msk, + whal_SetBits(RCC_CR_PLLON_Msk, RCC_CR_PLLON_Pos, 1)); return WHAL_SUCCESS; } @@ -142,12 +203,12 @@ whal_Error whal_Stm32wbRccMsi_Init(whal_Clock *clkDev) } /* Select MSI as system clock source */ - whal_Reg_Update(clkDev->regmap.base, ST_RCC_CFGR_REG, ST_RCC_CFGR_SW, - whal_SetBits(ST_RCC_CFGR_SW, WHAL_STM32WB_RCC_SYSCLK_SRC_MSI)); + whal_Reg_Update(clkDev->regmap.base, RCC_CFGR_REG, RCC_CFGR_SW_Msk, + whal_SetBits(RCC_CFGR_SW_Msk, RCC_CFGR_SW_Pos, WHAL_STM32WB_RCC_SYSCLK_SRC_MSI)); /* Set MSI frequency range */ - whal_Reg_Update(clkDev->regmap.base, ST_RCC_CR_REG, ST_RCC_CR_MSIRANGE, - whal_SetBits(ST_RCC_CR_MSIRANGE, msiCfg->freq)); + whal_Reg_Update(clkDev->regmap.base, RCC_CR_REG, RCC_CR_MSIRANGE_Msk, + whal_SetBits(RCC_CR_MSIRANGE_Msk, RCC_CR_MSIRANGE_Pos, msiCfg->freq)); return WHAL_SUCCESS; } @@ -163,17 +224,17 @@ whal_Error whal_Stm32wbRccPll_Deinit(whal_Clock *clkDev) cfg = (whal_Stm32wbRcc_Cfg *)clkDev->cfg; /* Switch back to MSI before disabling PLL */ - whal_Reg_Update(clkDev->regmap.base, ST_RCC_CFGR_REG, ST_RCC_CFGR_SW, - whal_SetBits(ST_RCC_CFGR_SW, WHAL_STM32WB_RCC_SYSCLK_SRC_MSI)); + whal_Reg_Update(clkDev->regmap.base, RCC_CFGR_REG, RCC_CFGR_SW_Msk, + whal_SetBits(RCC_CFGR_SW_Msk, RCC_CFGR_SW_Pos, WHAL_STM32WB_RCC_SYSCLK_SRC_MSI)); /* Reset MSI to default 4 MHz */ - whal_Reg_Update(clkDev->regmap.base, ST_RCC_CR_REG, ST_RCC_CR_MSIRANGE, - whal_SetBits(ST_RCC_CR_MSIRANGE, WHAL_STM32WB_RCC_MSIRANGE_4MHz)); + whal_Reg_Update(clkDev->regmap.base, RCC_CR_REG, RCC_CR_MSIRANGE_Msk, + whal_SetBits(RCC_CR_MSIRANGE_Msk, RCC_CR_MSIRANGE_Pos, WHAL_STM32WB_RCC_MSIRANGE_4MHz)); /* Disable the PLL */ - whal_Reg_Update(clkDev->regmap.base, ST_RCC_CR_REG, - ST_RCC_CR_PLLON_MASK, - whal_SetBits(ST_RCC_CR_PLLON_MASK, 0)); + whal_Reg_Update(clkDev->regmap.base, RCC_CR_REG, + RCC_CR_PLLON_Msk, + whal_SetBits(RCC_CR_PLLON_Msk, RCC_CR_PLLON_Pos, 0)); /* Reduce flash latency now that clock is slower */ whal_Stm32wbFlash_Ext_SetLatency(cfg->flash, WHAL_STM32WB_FLASH_LATENCY_0); @@ -191,11 +252,11 @@ whal_Error whal_Stm32wbRccMsi_Deinit(whal_Clock *clkDev) cfg = (whal_Stm32wbRcc_Cfg *)clkDev->cfg; - whal_Reg_Update(clkDev->regmap.base, ST_RCC_CFGR_REG, ST_RCC_CFGR_SW, - whal_SetBits(ST_RCC_CFGR_SW, WHAL_STM32WB_RCC_SYSCLK_SRC_MSI)); + whal_Reg_Update(clkDev->regmap.base, RCC_CFGR_REG, RCC_CFGR_SW_Msk, + whal_SetBits(RCC_CFGR_SW_Msk, RCC_CFGR_SW_Pos, WHAL_STM32WB_RCC_SYSCLK_SRC_MSI)); - whal_Reg_Update(clkDev->regmap.base, ST_RCC_CR_REG, ST_RCC_CR_MSIRANGE, - whal_SetBits(ST_RCC_CR_MSIRANGE, WHAL_STM32WB_RCC_MSIRANGE_4MHz)); + whal_Reg_Update(clkDev->regmap.base, RCC_CR_REG, RCC_CR_MSIRANGE_Msk, + whal_SetBits(RCC_CR_MSIRANGE_Msk, RCC_CR_MSIRANGE_Pos, WHAL_STM32WB_RCC_MSIRANGE_4MHz)); whal_Stm32wbFlash_Ext_SetLatency(cfg->flash, WHAL_STM32WB_FLASH_LATENCY_0); @@ -208,7 +269,7 @@ whal_Error whal_Stm32wbRcc_Enable(whal_Clock *clkDev, const void *clk) /* Set the peripheral's enable bit in the appropriate RCC enable register */ whal_Reg_Update(clkDev->regmap.base, stClk->regOffset, stClk->enableMask, - whal_SetBits(stClk->enableMask, 1)); + whal_SetBits(stClk->enableMask, stClk->enablePos, 1)); return WHAL_SUCCESS; } @@ -219,7 +280,7 @@ whal_Error whal_Stm32wbRcc_Disable(whal_Clock *clkDev, const void *clk) /* Clear the peripheral's enable bit to gate its clock */ whal_Reg_Update(clkDev->regmap.base, stClk->regOffset, stClk->enableMask, - whal_SetBits(stClk->enableMask, 0)); + whal_SetBits(stClk->enableMask, stClk->enablePos, 0)); return WHAL_SUCCESS; } @@ -265,7 +326,8 @@ whal_Error whal_Stm32wbRccMsi_GetRate(whal_Clock *clkDev, size_t *rateOut) } /* Read current MSI range from hardware */ - whal_Reg_Get(clkDev->regmap.base, ST_RCC_CR_REG, ST_RCC_CR_MSIRANGE, &msiRange); + whal_Reg_Get(clkDev->regmap.base, RCC_CR_REG, RCC_CR_MSIRANGE_Msk, + RCC_CR_MSIRANGE_Pos, &msiRange); /* Map range setting to frequency in Hz */ switch (msiRange) { @@ -316,14 +378,14 @@ whal_Error whal_Stm32wbRcc_Ext_EnableHsi48(whal_Clock *clkDev, uint8_t enable) return WHAL_EINVAL; } - whal_Reg_Update(clkDev->regmap.base, ST_RCC_CRRCR_REG, ST_RCC_CRRCR_HSI48ON_MASK, - whal_SetBits(ST_RCC_CRRCR_HSI48ON_MASK, enable)); + whal_Reg_Update(clkDev->regmap.base, RCC_CRRCR_REG, RCC_CRRCR_HSI48ON_Msk, + whal_SetBits(RCC_CRRCR_HSI48ON_Msk, RCC_CRRCR_HSI48ON_Pos, enable)); if (enable) { size_t rdy; do { - whal_Reg_Get(clkDev->regmap.base, ST_RCC_CRRCR_REG, - ST_RCC_CRRCR_HSI48RDY_MASK, &rdy); + whal_Reg_Get(clkDev->regmap.base, RCC_CRRCR_REG, + RCC_CRRCR_HSI48RDY_Msk, RCC_CRRCR_HSI48RDY_Pos, &rdy); } while (!rdy); } diff --git a/src/flash/pic32cz_flash.c b/src/flash/pic32cz_flash.c index 9334bd2..23217cc 100644 --- a/src/flash/pic32cz_flash.c +++ b/src/flash/pic32cz_flash.c @@ -23,39 +23,67 @@ #define FCW_DATA_REG(n) (0x28 + ((n) * 4)) /* CTRLA: NVM operation command and pre-program bit */ -#define FCW_CTRLA_NVMOP_MASK WHAL_MASK_RANGE(3, 0) +#define FCW_CTRLA_NVMOP_Pos 0 +#define FCW_CTRLA_NVMOP_Msk (WHAL_BITMASK(4) << FCW_CTRLA_NVMOP_Pos) #define FCW_CTRLA_NVMOP_SINGLE_DWORD 0x1 #define FCW_CTRLA_NVMOP_QUAD_DWORD 0x2 #define FCW_CTRLA_NVMOP_PAGE_ERASE 0x4 -#define FCW_CTRLA_PREPG WHAL_MASK(7) + +#define FCW_CTRLA_PREPG_Pos 7 +#define FCW_CTRLA_PREPG_Msk (1UL << FCW_CTRLA_PREPG_Pos) /* MUTEX: NVM locking and ownership values */ -#define FCW_MUTEX_LOCK WHAL_MASK(0) -#define FCW_MUTEX_OWNER WHAL_MASK_RANGE(2, 1) +#define FCW_MUTEX_LOCK_Pos 0 +#define FCW_MUTEX_LOCK_Msk (1UL << FCW_MUTEX_LOCK_Pos) + +#define FCW_MUTEX_OWNER_Pos 1 +#define FCW_MUTEX_OWNER_Msk (WHAL_BITMASK(2) << FCW_MUTEX_OWNER_Pos) /* INTFLAG: operation completion and error flags (write-1-to-clear) */ -#define FCW_INTFLAG_DONE WHAL_MASK(0) -#define FCW_INTFLAG_KEYERR WHAL_MASK(1) -#define FCW_INTFLAG_CFGERR WHAL_MASK(2) -#define FCW_INTFLAG_FIFOERR WHAL_MASK(3) -#define FCW_INTFLAG_BUSERR WHAL_MASK(4) -#define FCW_INTFLAG_WPERR WHAL_MASK(5) -#define FCW_INTFLAG_OPERR WHAL_MASK(6) -#define FCW_INTFLAG_SECERR WHAL_MASK(7) -#define FCW_INTFLAG_HTDPGM WHAL_MASK(8) -#define FCW_INTFLAG_BORERR WHAL_MASK(12) -#define FCW_INTFLAG_WRERR WHAL_MASK(13) - -#define FCW_INTFLAG_ALL_ERR (FCW_INTFLAG_KEYERR | FCW_INTFLAG_CFGERR | \ - FCW_INTFLAG_FIFOERR | FCW_INTFLAG_BUSERR | \ - FCW_INTFLAG_WPERR | FCW_INTFLAG_OPERR | \ - FCW_INTFLAG_SECERR | FCW_INTFLAG_HTDPGM | \ - FCW_INTFLAG_BORERR | FCW_INTFLAG_WRERR) - -#define FCW_INTFLAG_ALL (FCW_INTFLAG_DONE | FCW_INTFLAG_ALL_ERR) +#define FCW_INTFLAG_DONE_Pos 0 +#define FCW_INTFLAG_DONE_Msk (1UL << FCW_INTFLAG_DONE_Pos) + +#define FCW_INTFLAG_KEYERR_Pos 1 +#define FCW_INTFLAG_KEYERR_Msk (1UL << FCW_INTFLAG_KEYERR_Pos) + +#define FCW_INTFLAG_CFGERR_Pos 2 +#define FCW_INTFLAG_CFGERR_Msk (1UL << FCW_INTFLAG_CFGERR_Pos) + +#define FCW_INTFLAG_FIFOERR_Pos 3 +#define FCW_INTFLAG_FIFOERR_Msk (1UL << FCW_INTFLAG_FIFOERR_Pos) + +#define FCW_INTFLAG_BUSERR_Pos 4 +#define FCW_INTFLAG_BUSERR_Msk (1UL << FCW_INTFLAG_BUSERR_Pos) + +#define FCW_INTFLAG_WPERR_Pos 5 +#define FCW_INTFLAG_WPERR_Msk (1UL << FCW_INTFLAG_WPERR_Pos) + +#define FCW_INTFLAG_OPERR_Pos 6 +#define FCW_INTFLAG_OPERR_Msk (1UL << FCW_INTFLAG_OPERR_Pos) + +#define FCW_INTFLAG_SECERR_Pos 7 +#define FCW_INTFLAG_SECERR_Msk (1UL << FCW_INTFLAG_SECERR_Pos) + +#define FCW_INTFLAG_HTDPGM_Pos 8 +#define FCW_INTFLAG_HTDPGM_Msk (1UL << FCW_INTFLAG_HTDPGM_Pos) + +#define FCW_INTFLAG_BORERR_Pos 12 +#define FCW_INTFLAG_BORERR_Msk (1UL << FCW_INTFLAG_BORERR_Pos) + +#define FCW_INTFLAG_WRERR_Pos 13 +#define FCW_INTFLAG_WRERR_Msk (1UL << FCW_INTFLAG_WRERR_Pos) + +#define FCW_INTFLAG_ALL_ERR (FCW_INTFLAG_KEYERR_Msk | FCW_INTFLAG_CFGERR_Msk | \ + FCW_INTFLAG_FIFOERR_Msk | FCW_INTFLAG_BUSERR_Msk | \ + FCW_INTFLAG_WPERR_Msk | FCW_INTFLAG_OPERR_Msk | \ + FCW_INTFLAG_SECERR_Msk | FCW_INTFLAG_HTDPGM_Msk | \ + FCW_INTFLAG_BORERR_Msk | FCW_INTFLAG_WRERR_Msk) + +#define FCW_INTFLAG_ALL (FCW_INTFLAG_DONE_Msk | FCW_INTFLAG_ALL_ERR) /* STATUS: busy flag */ -#define FCW_STATUS_BUSY WHAL_MASK(0) +#define FCW_STATUS_BUSY_Pos 0 +#define FCW_STATUS_BUSY_Msk (1UL << FCW_STATUS_BUSY_Pos) /* KEY: unlock value for write/erase operations */ #define FCW_UNLOCK_WRKEY 0x91C32C01 @@ -69,26 +97,26 @@ static void whal_Pic32czFlash_MutexLock(const whal_Regmap *reg) { size_t locked = 1; while (locked) { - whal_Reg_Get(reg->base, FCW_MUTEX_REG, FCW_MUTEX_LOCK, &locked); + whal_Reg_Get(reg->base, FCW_MUTEX_REG, FCW_MUTEX_LOCK_Msk, FCW_MUTEX_LOCK_Pos, &locked); } - whal_Reg_Update(reg->base, FCW_MUTEX_REG, FCW_MUTEX_LOCK | FCW_MUTEX_OWNER, - whal_SetBits(FCW_MUTEX_LOCK, 1) | - whal_SetBits(FCW_MUTEX_OWNER, 1)); + whal_Reg_Update(reg->base, FCW_MUTEX_REG, FCW_MUTEX_LOCK_Msk | FCW_MUTEX_OWNER_Msk, + whal_SetBits(FCW_MUTEX_LOCK_Msk, FCW_MUTEX_LOCK_Pos, 1) | + whal_SetBits(FCW_MUTEX_OWNER_Msk, FCW_MUTEX_OWNER_Pos, 1)); } static void whal_Pic32czFlash_MutexUnlock(const whal_Regmap *reg) { - whal_Reg_Update(reg->base, FCW_MUTEX_REG, FCW_MUTEX_LOCK | FCW_MUTEX_OWNER, - whal_SetBits(FCW_MUTEX_LOCK, 0) | - whal_SetBits(FCW_MUTEX_OWNER, 1)); + whal_Reg_Update(reg->base, FCW_MUTEX_REG, FCW_MUTEX_LOCK_Msk | FCW_MUTEX_OWNER_Msk, + whal_SetBits(FCW_MUTEX_LOCK_Msk, FCW_MUTEX_LOCK_Pos, 0) | + whal_SetBits(FCW_MUTEX_OWNER_Msk, FCW_MUTEX_OWNER_Pos, 1)); } static void whal_Pic32czFlash_WaitBusy(const whal_Regmap *reg) { size_t busy = 1; while (busy) { - whal_Reg_Get(reg->base, FCW_STATUS_REG, FCW_STATUS_BUSY, &busy); + whal_Reg_Get(reg->base, FCW_STATUS_REG, FCW_STATUS_BUSY_Msk, FCW_STATUS_BUSY_Pos, &busy); } } @@ -105,18 +133,18 @@ static whal_Error whal_Pic32czFlash_ExecCmd(const whal_Regmap *reg, size_t cmd) /* Trigger operation with pre-program enabled */ whal_Reg_Update(reg->base, FCW_CTRLA_REG, - FCW_CTRLA_NVMOP_MASK | FCW_CTRLA_PREPG, - whal_SetBits(FCW_CTRLA_NVMOP_MASK, cmd) | FCW_CTRLA_PREPG); + FCW_CTRLA_NVMOP_Msk | FCW_CTRLA_PREPG_Msk, + whal_SetBits(FCW_CTRLA_NVMOP_Msk, FCW_CTRLA_NVMOP_Pos, cmd) | FCW_CTRLA_PREPG_Msk); /* Wait for completion */ whal_Pic32czFlash_WaitBusy(reg); /* Check for errors */ - whal_Reg_Get(reg->base, FCW_INTFLAG_REG, FCW_INTFLAG_ALL_ERR, &errFlags); + whal_Reg_Get(reg->base, FCW_INTFLAG_REG, FCW_INTFLAG_ALL_ERR, 0, &errFlags); /* Clear DONE flag */ - whal_Reg_Update(reg->base, FCW_INTFLAG_REG, FCW_INTFLAG_DONE, - FCW_INTFLAG_DONE); + whal_Reg_Update(reg->base, FCW_INTFLAG_REG, FCW_INTFLAG_DONE_Msk, + FCW_INTFLAG_DONE_Msk); if (errFlags) { /* Clear error flags */ diff --git a/src/flash/stm32wb_flash.c b/src/flash/stm32wb_flash.c index 4143dfc..f1ecf15 100644 --- a/src/flash/stm32wb_flash.c +++ b/src/flash/stm32wb_flash.c @@ -14,50 +14,87 @@ */ /* Access Control Register - configures latency and caches */ -#define ST_FLASH_ACR_REG 0x00 -#define ST_FLASH_ACR_LATENCY WHAL_MASK_RANGE(2, 0) /* Wait states (0-3) */ +#define FLASH_ACR_REG 0x00 +#define FLASH_ACR_LATENCY_Pos 0 /* Wait states (0-3) */ +#define FLASH_ACR_LATENCY_Msk (WHAL_BITMASK(3) << FLASH_ACR_LATENCY_Pos) /* Key Register - unlock sequence for write operations */ -#define ST_FLASH_KEYR_REG 0x08 -#define ST_FLASH_KEYR_KEY WHAL_MASK_RANGE(31, 0) +#define FLASH_KEYR_REG 0x08 +#define FLASH_KEYR_KEY_Msk (~0UL) /* Status Register - operation status and error flags */ -#define ST_FLASH_SR_REG 0x10 -#define ST_FLASH_SR_EOP WHAL_MASK(0) /* End of operation */ -#define ST_FLASH_SR_OP_ERR WHAL_MASK(1) /* Operation error */ -#define ST_FLASH_SR_PROG_ERR WHAL_MASK(3) /* Programming error */ -#define ST_FLASH_SR_WRP_ERR WHAL_MASK(4) /* Write protection error */ -#define ST_FLASH_SR_PGA_ERR WHAL_MASK(5) /* Programming alignment error */ -#define ST_FLASH_SR_SIZ_ERR WHAL_MASK(6) /* Size error */ -#define ST_FLASH_SR_PGS_ERR WHAL_MASK(7) /* Programming sequence error */ -#define ST_FLASH_SR_MISS_ERR WHAL_MASK(8) /* Fast programming miss error */ -#define ST_FLASH_SR_FAST_ERR WHAL_MASK(9) /* Fast programming error */ -#define ST_FLASH_SR_RD_ERR WHAL_MASK(14) /* Read protection error */ -#define ST_FLASH_SR_OPTV_ERR WHAL_MASK(15) /* Option validity error */ -#define ST_FLASH_SR_BSY WHAL_MASK(16) /* Busy flag */ -#define ST_FLASH_SR_CFGBSY WHAL_MASK(18) /* Configuration busy */ -#define ST_FLASH_SR_PESD WHAL_MASK(19) /* Programming/erase suspended */ +#define FLASH_SR_REG 0x10 +#define FLASH_SR_EOP_Pos 0 /* End of operation */ +#define FLASH_SR_EOP_Msk (1UL << FLASH_SR_EOP_Pos) + +#define FLASH_SR_OP_ERR_Pos 1 /* Operation error */ +#define FLASH_SR_OP_ERR_Msk (1UL << FLASH_SR_OP_ERR_Pos) + +#define FLASH_SR_PROG_ERR_Pos 3 /* Programming error */ +#define FLASH_SR_PROG_ERR_Msk (1UL << FLASH_SR_PROG_ERR_Pos) + +#define FLASH_SR_WRP_ERR_Pos 4 /* Write protection error */ +#define FLASH_SR_WRP_ERR_Msk (1UL << FLASH_SR_WRP_ERR_Pos) + +#define FLASH_SR_PGA_ERR_Pos 5 /* Programming alignment error */ +#define FLASH_SR_PGA_ERR_Msk (1UL << FLASH_SR_PGA_ERR_Pos) + +#define FLASH_SR_SIZ_ERR_Pos 6 /* Size error */ +#define FLASH_SR_SIZ_ERR_Msk (1UL << FLASH_SR_SIZ_ERR_Pos) + +#define FLASH_SR_PGS_ERR_Pos 7 /* Programming sequence error */ +#define FLASH_SR_PGS_ERR_Msk (1UL << FLASH_SR_PGS_ERR_Pos) + +#define FLASH_SR_MISS_ERR_Pos 8 /* Fast programming miss error */ +#define FLASH_SR_MISS_ERR_Msk (1UL << FLASH_SR_MISS_ERR_Pos) + +#define FLASH_SR_FAST_ERR_Pos 9 /* Fast programming error */ +#define FLASH_SR_FAST_ERR_Msk (1UL << FLASH_SR_FAST_ERR_Pos) + +#define FLASH_SR_RD_ERR_Pos 14 /* Read protection error */ +#define FLASH_SR_RD_ERR_Msk (1UL << FLASH_SR_RD_ERR_Pos) + +#define FLASH_SR_OPTV_ERR_Pos 15 /* Option validity error */ +#define FLASH_SR_OPTV_ERR_Msk (1UL << FLASH_SR_OPTV_ERR_Pos) + +#define FLASH_SR_BSY_Pos 16 /* Busy flag */ +#define FLASH_SR_BSY_Msk (1UL << FLASH_SR_BSY_Pos) + +#define FLASH_SR_CFGBSY_Pos 18 /* Configuration busy */ +#define FLASH_SR_CFGBSY_Msk (1UL << FLASH_SR_CFGBSY_Pos) + +#define FLASH_SR_PESD_Pos 19 /* Programming/erase suspended */ +#define FLASH_SR_PESD_Msk (1UL << FLASH_SR_PESD_Pos) /* Combined mask for all error flags */ -#define ST_FLASH_SR_ALL_ERR (ST_FLASH_SR_OP_ERR | ST_FLASH_SR_PROG_ERR | ST_FLASH_SR_WRP_ERR | \ - ST_FLASH_SR_PGA_ERR | ST_FLASH_SR_SIZ_ERR | ST_FLASH_SR_PGS_ERR | \ - ST_FLASH_SR_MISS_ERR | ST_FLASH_SR_FAST_ERR | ST_FLASH_SR_RD_ERR | \ - ST_FLASH_SR_OPTV_ERR) +#define FLASH_SR_ALL_ERR (FLASH_SR_OP_ERR_Msk | FLASH_SR_PROG_ERR_Msk | FLASH_SR_WRP_ERR_Msk | \ + FLASH_SR_PGA_ERR_Msk | FLASH_SR_SIZ_ERR_Msk | FLASH_SR_PGS_ERR_Msk | \ + FLASH_SR_MISS_ERR_Msk | FLASH_SR_FAST_ERR_Msk | FLASH_SR_RD_ERR_Msk | \ + FLASH_SR_OPTV_ERR_Msk) /* Control Register - enables operations and selects pages */ -#define ST_FLASH_CR_REG 0x14 -#define ST_FLASH_CR_PG WHAL_MASK(0) /* Programming enable */ -#define ST_FLASH_CR_PER WHAL_MASK(1) /* Page erase enable */ -#define ST_FLASH_CR_PNB WHAL_MASK_RANGE(10, 3) /* Page number for erase */ -#define ST_FLASH_CR_STRT WHAL_MASK(16) /* Start erase operation */ -#define ST_FLASH_CR_LOCK WHAL_MASK(31) /* Lock flash control */ +#define FLASH_CR_REG 0x14 +#define FLASH_CR_PG_Pos 0 /* Programming enable */ +#define FLASH_CR_PG_Msk (1UL << FLASH_CR_PG_Pos) + +#define FLASH_CR_PER_Pos 1 /* Page erase enable */ +#define FLASH_CR_PER_Msk (1UL << FLASH_CR_PER_Pos) + +#define FLASH_CR_PNB_Pos 3 /* Page number for erase */ +#define FLASH_CR_PNB_Msk (WHAL_BITMASK(8) << FLASH_CR_PNB_Pos) + +#define FLASH_CR_STRT_Pos 16 /* Start erase operation */ +#define FLASH_CR_STRT_Msk (1UL << FLASH_CR_STRT_Pos) + +#define FLASH_CR_LOCK_Pos 31 /* Lock flash control */ +#define FLASH_CR_LOCK_Msk (1UL << FLASH_CR_LOCK_Pos) whal_Error whal_Stm32wbFlash_Init(whal_Flash *flashDev) { whal_Error err; whal_Stm32wbFlash_Cfg *cfg = flashDev->cfg; - err = whal_Clock_Enable(cfg->clkCtrl, cfg->clk); + err = whal_Clock_Enable(cfg->clkCtrl, cfg->clk); if (err) { return err; } @@ -70,7 +107,7 @@ whal_Error whal_Stm32wbFlash_Deinit(whal_Flash *flashDev) whal_Error err; whal_Stm32wbFlash_Cfg *cfg = flashDev->cfg; - err = whal_Clock_Disable(cfg->clkCtrl, cfg->clk); + err = whal_Clock_Disable(cfg->clkCtrl, cfg->clk); if (err) { return err; } @@ -86,8 +123,8 @@ whal_Error whal_Stm32wbFlash_Lock(whal_Flash *flashDev, size_t addr, size_t len) const whal_Regmap *regmap = &flashDev->regmap; /* Setting LOCK bit prevents further flash modifications until next unlock */ - whal_Reg_Update(regmap->base, ST_FLASH_CR_REG, ST_FLASH_CR_LOCK, - whal_SetBits(ST_FLASH_CR_LOCK, 1)); + whal_Reg_Update(regmap->base, FLASH_CR_REG, FLASH_CR_LOCK_Msk, + whal_SetBits(FLASH_CR_LOCK_Msk, FLASH_CR_LOCK_Pos, 1)); return WHAL_SUCCESS; } @@ -103,8 +140,8 @@ whal_Error whal_Stm32wbFlash_Unlock(whal_Flash *flashDev, size_t addr, size_t le * Unlock sequence: write KEY1 then KEY2 to KEYR register. * Incorrect sequence or order will trigger a bus error. */ - whal_Reg_Update(regmap->base, ST_FLASH_KEYR_REG, ST_FLASH_KEYR_KEY, 0x45670123); - whal_Reg_Update(regmap->base, ST_FLASH_KEYR_REG, ST_FLASH_KEYR_KEY, 0xCDEF89AB); + whal_Reg_Update(regmap->base, FLASH_KEYR_REG, FLASH_KEYR_KEY_Msk, 0x45670123); + whal_Reg_Update(regmap->base, FLASH_KEYR_REG, FLASH_KEYR_KEY_Msk, 0xCDEF89AB); return WHAL_SUCCESS; } @@ -143,19 +180,19 @@ static whal_Error whal_Stm32wbFlash_WriteOrErase(whal_Flash *flashDev, size_t ad } /* Check if flash is busy or suspended */ - whal_Reg_Get(regmap->base, ST_FLASH_SR_REG, ST_FLASH_SR_BSY, &bsy); - whal_Reg_Get(regmap->base, ST_FLASH_SR_REG, ST_FLASH_SR_PESD, &pesd); + whal_Reg_Get(regmap->base, FLASH_SR_REG, FLASH_SR_BSY_Msk, FLASH_SR_BSY_Pos, &bsy); + whal_Reg_Get(regmap->base, FLASH_SR_REG, FLASH_SR_PESD_Msk, FLASH_SR_PESD_Pos, &pesd); if (bsy || pesd) { return WHAL_ENOTREADY; } /* Clear all error flags by writing 1 to each */ - whal_Reg_Update(regmap->base, ST_FLASH_SR_REG, ST_FLASH_SR_ALL_ERR, 0xffffffff); + whal_Reg_Update(regmap->base, FLASH_SR_REG, FLASH_SR_ALL_ERR, 0xffffffff); if (write) { /* Enable flash programming mode */ - whal_Reg_Update(regmap->base, ST_FLASH_CR_REG, ST_FLASH_CR_PG, 1); + whal_Reg_Update(regmap->base, FLASH_CR_REG, FLASH_CR_PG_Msk, 1); /* Program data in 64-bit (8 byte) double-word chunks */ for (size_t i = 0; i < dataSz; i += 8) { @@ -168,7 +205,7 @@ static whal_Error whal_Stm32wbFlash_WriteOrErase(whal_Flash *flashDev, size_t ad /* Wait for programming to complete */ do { - whal_Reg_Get(regmap->base, ST_FLASH_SR_REG, ST_FLASH_SR_CFGBSY, &cfgbsy); + whal_Reg_Get(regmap->base, FLASH_SR_REG, FLASH_SR_CFGBSY_Msk, FLASH_SR_CFGBSY_Pos, &cfgbsy); } while (cfgbsy); } } @@ -179,32 +216,32 @@ static whal_Error whal_Stm32wbFlash_WriteOrErase(whal_Flash *flashDev, size_t ad endPage = ((addr - cfg->startAddr) + dataSz) >> 12; /* Enable page erase mode */ - whal_Reg_Update(regmap->base, ST_FLASH_CR_REG, ST_FLASH_CR_PER, - whal_SetBits(ST_FLASH_CR_PER, 1)); + whal_Reg_Update(regmap->base, FLASH_CR_REG, FLASH_CR_PER_Msk, + whal_SetBits(FLASH_CR_PER_Msk, FLASH_CR_PER_Pos, 1)); /* Erase each page in the range */ for (size_t page = startPage; page <= endPage; ++page) { /* Select page number */ - whal_Reg_Update(regmap->base, ST_FLASH_CR_REG, ST_FLASH_CR_PNB, - whal_SetBits(ST_FLASH_CR_PNB, page)); + whal_Reg_Update(regmap->base, FLASH_CR_REG, FLASH_CR_PNB_Msk, + whal_SetBits(FLASH_CR_PNB_Msk, FLASH_CR_PNB_Pos, page)); /* Start erase operation */ - whal_Reg_Update(regmap->base, ST_FLASH_CR_REG, ST_FLASH_CR_STRT, - whal_SetBits(ST_FLASH_CR_STRT, 1)); + whal_Reg_Update(regmap->base, FLASH_CR_REG, FLASH_CR_STRT_Msk, + whal_SetBits(FLASH_CR_STRT_Msk, FLASH_CR_STRT_Pos, 1)); /* Wait for erase to complete */ do { - whal_Reg_Get(regmap->base, ST_FLASH_SR_REG, ST_FLASH_SR_CFGBSY, &cfgbsy); + whal_Reg_Get(regmap->base, FLASH_SR_REG, FLASH_SR_CFGBSY_Msk, FLASH_SR_CFGBSY_Pos, &cfgbsy); } while (cfgbsy); } /* Disable page erase mode */ - whal_Reg_Update(regmap->base, ST_FLASH_CR_REG, ST_FLASH_CR_PER, - whal_SetBits(ST_FLASH_CR_PER, 0)); + whal_Reg_Update(regmap->base, FLASH_CR_REG, FLASH_CR_PER_Msk, + whal_SetBits(FLASH_CR_PER_Msk, FLASH_CR_PER_Pos, 0)); } /* Disable flash programming mode */ - whal_Reg_Update(regmap->base, ST_FLASH_CR_REG, ST_FLASH_CR_PG, 0); + whal_Reg_Update(regmap->base, FLASH_CR_REG, FLASH_CR_PG_Msk, 0); return WHAL_SUCCESS; } @@ -228,7 +265,7 @@ whal_Error whal_Stm32wbFlash_Ext_SetLatency(whal_Flash *flashDev, enum whal_Stm3 } const whal_Regmap *reg = &flashDev->regmap; - whal_Reg_Update(reg->base, ST_FLASH_ACR_REG, ST_FLASH_ACR_LATENCY, latency); + whal_Reg_Update(reg->base, FLASH_ACR_REG, FLASH_ACR_LATENCY_Msk, latency); return WHAL_SUCCESS; } diff --git a/src/gpio/pic32cz_gpio.c b/src/gpio/pic32cz_gpio.c index f625aef..6729e18 100644 --- a/src/gpio/pic32cz_gpio.c +++ b/src/gpio/pic32cz_gpio.c @@ -14,13 +14,13 @@ */ /* Direction register - bit N controls pin N (1=output, 0=input) */ -#define PIC32CZ_DIR_REG(port) (0x00 + (port * 0x80)) +#define DIR_REG(port) (0x00 + (port * 0x80)) /* Output register - bit N is the output value for pin N */ -#define PIC32CZ_OUT_REG(port) (0x10 + (port * 0x80)) +#define OUT_REG(port) (0x10 + (port * 0x80)) /* Input register - bit N is the sampled input value for pin N */ -#define PIC32CZ_IN_REG(port) (0x20 + (port * 0x80)) +#define IN_REG(port) (0x20 + (port * 0x80)) /* * Peripheral multiplexer register - selects alternate function for pins. @@ -31,8 +31,9 @@ * The APB bridge only supports 32-bit access, so the offset is word-aligned * and the shift positions the pin's nibble within the 32-bit word. */ -#define PIC32CZ_PMUXx_REG(port, pin) ((0x30 + (((pin) / 8) * 4)) + ((port) * 0x80)) -#define PIC32CZ_PMUXx_MASK(pin) (0xFul << (((pin) % 8) * 4)) +#define PMUXx_REG(port, pin) ((0x30 + (((pin) / 8) * 4)) + ((port) * 0x80)) +#define PMUXx_Pos(pin) (((pin) % 8) * 4) +#define PMUXx_Msk(pin) (WHAL_BITMASK(4) << (PMUXx_Pos(pin))) /* * Pin configuration register - one byte per pin. @@ -40,10 +41,15 @@ * Word-aligned for 32-bit access through the APB bridge. The pin argument * positions each field's mask within the 32-bit word. */ -#define PIC32CZ_PINCFGx_REG(port, pin) ((0x40 + ((pin) & ~3)) + ((port) * 0x80)) -#define PIC32CZ_PINCFGx_PMUXEN(pin) (WHAL_MASK(0) << (((pin) & 3) * 8)) -#define PIC32CZ_PINCFGx_INEN(pin) (WHAL_MASK(1) << (((pin) & 3) * 8)) -#define PIC32CZ_PINCFGx_PULLEN(pin) (WHAL_MASK(2) << (((pin) & 3) * 8)) +#define PINCFGx_REG(port, pin) ((0x40 + ((pin) & ~3)) + ((port) * 0x80)) +#define PINCFGx_PMUXEN_Pos(pin) (((pin) & 3) * 8) +#define PINCFGx_PMUXEN_Msk(pin) (1UL << (PINCFGx_PMUXEN_Pos(pin))) + +#define PINCFGx_INEN_Pos(pin) (1 + (((pin) & 3) * 8)) +#define PINCFGx_INEN_Msk(pin) (1UL << (PINCFGx_INEN_Pos(pin))) + +#define PINCFGx_PULLEN_Pos(pin) (2 + (((pin) & 3) * 8)) +#define PINCFGx_PULLEN_Msk(pin) (1UL << (PINCFGx_PULLEN_Pos(pin))) whal_Error whal_Pic32czGpio_Init(whal_Gpio *gpioDev) { @@ -55,7 +61,7 @@ whal_Error whal_Pic32czGpio_Init(whal_Gpio *gpioDev) for (size_t i = 0; i < cfg->pinCfgCount; ++i) { whal_Pic32czGpio_PinCfg *pinCfg = &cfg->pinCfg[i]; - size_t pinMask = WHAL_MASK(pinCfg->pin); + size_t pinMask = (1UL << (pinCfg->pin)); if (pinCfg->pmuxEn) { /* @@ -63,18 +69,20 @@ whal_Error whal_Pic32czGpio_Init(whal_Gpio *gpioDev) * 1. Set the PMUX value to select the peripheral function * 2. Enable PMUXEN in PINCFG to route pin to peripheral */ - size_t pmuxMask = PIC32CZ_PMUXx_MASK(pinCfg->pin); - size_t pmuxenMask = PIC32CZ_PINCFGx_PMUXEN(pinCfg->pin); + size_t pmuxMask = PMUXx_Msk(pinCfg->pin); + size_t pmuxPos = PMUXx_Pos(pinCfg->pin); + size_t pmuxenMask = PINCFGx_PMUXEN_Msk(pinCfg->pin); + size_t pmuxenPos = PINCFGx_PMUXEN_Pos(pinCfg->pin); whal_Reg_Update(gpioDev->regmap.base, - PIC32CZ_PMUXx_REG(pinCfg->port, pinCfg->pin), + PMUXx_REG(pinCfg->port, pinCfg->pin), pmuxMask, - whal_SetBits(pmuxMask, pinCfg->pmux)); + whal_SetBits(pmuxMask, pmuxPos, pinCfg->pmux)); whal_Reg_Update(gpioDev->regmap.base, - PIC32CZ_PINCFGx_REG(pinCfg->port, pinCfg->pin), + PINCFGx_REG(pinCfg->port, pinCfg->pin), pmuxenMask, - whal_SetBits(pmuxenMask, 1)); + whal_SetBits(pmuxenMask, pmuxenPos, 1)); continue; } @@ -87,25 +95,27 @@ whal_Error whal_Pic32czGpio_Init(whal_Gpio *gpioDev) */ /* Set pin direction */ - whal_Reg_Update(gpioDev->regmap.base, PIC32CZ_DIR_REG(pinCfg->port), + whal_Reg_Update(gpioDev->regmap.base, DIR_REG(pinCfg->port), pinMask, - whal_SetBits(pinMask, pinCfg->dir)); + whal_SetBits(pinMask, pinCfg->pin, pinCfg->dir)); /* Set initial output value */ - whal_Reg_Update(gpioDev->regmap.base, PIC32CZ_OUT_REG(pinCfg->port), + whal_Reg_Update(gpioDev->regmap.base, OUT_REG(pinCfg->port), pinMask, - whal_SetBits(pinMask, pinCfg->out)); + whal_SetBits(pinMask, pinCfg->pin, pinCfg->out)); /* Configure input buffer and pull resistor */ { - size_t inenMask = PIC32CZ_PINCFGx_INEN(pinCfg->pin); - size_t pullenMask = PIC32CZ_PINCFGx_PULLEN(pinCfg->pin); + size_t inenMask = PINCFGx_INEN_Msk(pinCfg->pin); + size_t inenPos = PINCFGx_INEN_Pos(pinCfg->pin); + size_t pullenMask = PINCFGx_PULLEN_Msk(pinCfg->pin); + size_t pullenPos = PINCFGx_PULLEN_Pos(pinCfg->pin); whal_Reg_Update(gpioDev->regmap.base, - PIC32CZ_PINCFGx_REG(pinCfg->port, pinCfg->pin), + PINCFGx_REG(pinCfg->port, pinCfg->pin), inenMask | pullenMask, - whal_SetBits(inenMask, pinCfg->inEn) | - whal_SetBits(pullenMask, pinCfg->pullEn)); + whal_SetBits(inenMask, inenPos, pinCfg->inEn) | + whal_SetBits(pullenMask, pullenPos, pinCfg->pullEn)); } } @@ -129,7 +139,7 @@ whal_Error whal_Pic32czGpio_Get(whal_Gpio *gpioDev, size_t pin, size_t *value) const whal_Pic32czGpio_Cfg *cfg = gpioDev->cfg; whal_Pic32czGpio_PinCfg *pinCfg = &cfg->pinCfg[pin]; - size_t pinMask = WHAL_MASK(pinCfg->pin); + size_t pinMask = (1UL << (pinCfg->pin)); size_t reg; /* @@ -138,13 +148,13 @@ whal_Error whal_Pic32czGpio_Get(whal_Gpio *gpioDev, size_t pin, size_t *value) * - Input pins: Read from IN register (sampled external value) */ if (pinCfg->dir == WHAL_PIC32CZ_DIR_OUTPUT) { - reg = PIC32CZ_OUT_REG(pinCfg->port); + reg = OUT_REG(pinCfg->port); } else { - reg = PIC32CZ_IN_REG(pinCfg->port); + reg = IN_REG(pinCfg->port); } - whal_Reg_Get(gpioDev->regmap.base, reg, pinMask, value); + whal_Reg_Get(gpioDev->regmap.base, reg, pinMask, pinCfg->pin, value); return WHAL_SUCCESS; } @@ -157,12 +167,12 @@ whal_Error whal_Pic32czGpio_Set(whal_Gpio *gpioDev, size_t pin, size_t value) const whal_Pic32czGpio_Cfg *cfg = gpioDev->cfg; whal_Pic32czGpio_PinCfg *pinCfg = &cfg->pinCfg[pin]; - size_t pinMask = WHAL_MASK(pinCfg->pin); + size_t pinMask = (1UL << (pinCfg->pin)); /* Update the output register to drive the new value */ - whal_Reg_Update(gpioDev->regmap.base, PIC32CZ_OUT_REG(pinCfg->port), + whal_Reg_Update(gpioDev->regmap.base, OUT_REG(pinCfg->port), pinMask, - whal_SetBits(pinMask, value)); + whal_SetBits(pinMask, pinCfg->pin, value)); return WHAL_SUCCESS; } diff --git a/src/gpio/stm32wb_gpio.c b/src/gpio/stm32wb_gpio.c index 61cdd1c..433da0c 100644 --- a/src/gpio/stm32wb_gpio.c +++ b/src/gpio/stm32wb_gpio.c @@ -13,24 +13,24 @@ */ /* Size of each GPIO port register block */ -#define STGPIO_PORT_SIZE 0x400 +#define GPIO_PORT_SIZE 0x400 /* Mode register - 2 bits per pin, selects input/output/altfn/analog */ -#define STGPIO_GPIOx_MODE_REG 0x00 +#define GPIO_MODE_REG 0x00 /* Output type register - 1 bit per pin, push-pull or open-drain */ -#define STGPIO_GPIOx_OUTTYPE_REG 0x04 +#define GPIO_OUTTYPE_REG 0x04 /* Output speed register - 2 bits per pin */ -#define STGPIO_GPIOx_SPEED_REG 0x08 +#define GPIO_SPEED_REG 0x08 /* Pull-up/pull-down register - 2 bits per pin */ -#define STGPIO_GPIOx_PULL_REG 0x0C +#define GPIO_PULL_REG 0x0C /* Input data register - read-only, 1 bit per pin */ -#define STGPIO_GPIOx_IDR_REG 0x10 +#define GPIO_IDR_REG 0x10 /* Output data register - 1 bit per pin */ -#define STGPIO_GPIOx_ODR_REG 0x14 +#define GPIO_ODR_REG 0x14 /* Alternate function low register - 4 bits per pin for pins 0-7 */ -#define STGPIO_GPIOx_ALTFNL_REG 0x20 +#define GPIO_ALTFNL_REG 0x20 /* Alternate function high register - 4 bits per pin for pins 8-15 */ -#define STGPIO_GPIOx_ALTFNH_REG 0x24 +#define GPIO_ALTFNH_REG 0x24 /* * Configure alternate function for a pin. @@ -47,11 +47,11 @@ static inline void whal_Stm32wbGpio_InitAltFn(whal_Regmap *portReg, whal_Stm32wb /* Each pin uses 4 bits: pin 0 = bits 0-3, pin 1 = bits 4-7, etc. */ maskBit = pin << 2; - mask = WHAL_MASK_RANGE(maskBit + 3, maskBit); + mask = (WHAL_BITMASK(4) << maskBit); /* Access AFRL and AFRH as a single 64-bit register */ - uint64_t *reg = (uint64_t *)(portReg->base + STGPIO_GPIOx_ALTFNL_REG); - *reg = (*reg & ~mask) | (whal_SetBits(mask, pinCfg->altFn) & mask); + uint64_t *reg = (uint64_t *)(portReg->base + GPIO_ALTFNL_REG); + *reg = (*reg & ~mask) | (whal_SetBits(mask, maskBit, pinCfg->altFn) & mask); } /* @@ -66,27 +66,27 @@ static inline whal_Error whal_Stm32wbGpio_InitPin(whal_Gpio *gpioDev, whal_Stm32 } /* Calculate port base address */ - portReg.size = STGPIO_PORT_SIZE; - portReg.base = (size_t)(gpioDev->regmap.base + (pinCfg->port * STGPIO_PORT_SIZE)); + portReg.size = GPIO_PORT_SIZE; + portReg.base = (size_t)(gpioDev->regmap.base + (pinCfg->port * GPIO_PORT_SIZE)); uint8_t pin = pinCfg->pin; /* 2-bit field mask for MODE, SPEED, PULL registers */ uint8_t maskBit = pin << 1; - size_t mask1 = WHAL_MASK_RANGE(maskBit + 1, maskBit); + size_t mask1 = (WHAL_BITMASK(2) << maskBit); /* 1-bit mask for OUTTYPE register */ - size_t mask2 = WHAL_MASK(pin); + size_t mask2 = (1UL << pin); /* Configure pin mode (input/output/altfn/analog) */ - whal_Reg_Update(portReg.base, STGPIO_GPIOx_MODE_REG, mask1, - whal_SetBits(mask1, pinCfg->mode)); + whal_Reg_Update(portReg.base, GPIO_MODE_REG, mask1, + whal_SetBits(mask1, maskBit, pinCfg->mode)); /* Configure output speed */ - whal_Reg_Update(portReg.base, STGPIO_GPIOx_SPEED_REG, mask1, - whal_SetBits(mask1, pinCfg->speed)); + whal_Reg_Update(portReg.base, GPIO_SPEED_REG, mask1, + whal_SetBits(mask1, maskBit, pinCfg->speed)); /* Configure output type (push-pull or open-drain) */ - whal_Reg_Update(portReg.base, STGPIO_GPIOx_OUTTYPE_REG, mask2, - whal_SetBits(mask2, pinCfg->outType)); + whal_Reg_Update(portReg.base, GPIO_OUTTYPE_REG, mask2, + whal_SetBits(mask2, pin, pinCfg->outType)); /* Configure alternate function if in ALTFN mode */ if (pinCfg->mode == WHAL_STM32WB_GPIO_MODE_ALTFN) { @@ -171,18 +171,18 @@ static whal_Error whal_Stm32wbGpio_SetOrGet(whal_Gpio *gpioDev, size_t pin, size } /* Calculate port base address from config */ - portReg.size = STGPIO_PORT_SIZE; - portReg.base = (size_t)(gpioDev->regmap.base + (pinCfg[pin].port * STGPIO_PORT_SIZE)); + portReg.size = GPIO_PORT_SIZE; + portReg.base = (size_t)(gpioDev->regmap.base + (pinCfg[pin].port * GPIO_PORT_SIZE)); - mask = WHAL_MASK(pinCfg[pin].pin); + mask = (1UL << (pinCfg[pin].pin)); if (set) { /* Write to output data register */ - whal_Reg_Update(portReg.base, STGPIO_GPIOx_ODR_REG, mask, - whal_SetBits(mask, *value)); + whal_Reg_Update(portReg.base, GPIO_ODR_REG, mask, + whal_SetBits(mask, pinCfg[pin].pin, *value)); } else { /* Read from input data register */ - whal_Reg_Get(portReg.base, STGPIO_GPIOx_IDR_REG, mask, value); + whal_Reg_Get(portReg.base, GPIO_IDR_REG, mask, pinCfg[pin].pin, value); } return WHAL_SUCCESS; diff --git a/src/reg.c b/src/reg.c index 8c6d044..340603d 100644 --- a/src/reg.c +++ b/src/reg.c @@ -11,11 +11,11 @@ void whal_Reg_Update(const size_t base, const size_t offset, const size_t mask, *reg = (*reg & ~mask) | (value & mask); } -void whal_Reg_Get(const size_t base, const size_t offset, const size_t mask, size_t *value) +void whal_Reg_Get(const size_t base, const size_t offset, const size_t msk, const size_t pos, size_t *value) { size_t val; val = *(volatile size_t *)(base + offset); - *value = whal_GetBits(mask, val); + *value = whal_GetBits(msk, pos, val); } diff --git a/src/rng/stm32wb_rng.c b/src/rng/stm32wb_rng.c index 265cedd..a595324 100644 --- a/src/rng/stm32wb_rng.c +++ b/src/rng/stm32wb_rng.c @@ -15,20 +15,32 @@ */ /* Control Register */ -#define SRNG_CR_REG 0x00 -#define SRNG_CR_RNGEN WHAL_MASK(2) /* RNG enable */ -#define SRNG_CR_CED WHAL_MASK(5) /* Clock error detection disable */ +#define RNG_CR_REG 0x00 +#define RNG_CR_RNGEN_Pos 2 /* RNG enable */ +#define RNG_CR_RNGEN_Msk (1UL << RNG_CR_RNGEN_Pos) + +#define RNG_CR_CED_Pos 5 /* Clock error detection disable */ +#define RNG_CR_CED_Msk (1UL << RNG_CR_CED_Pos) /* Status Register */ -#define SRNG_SR_REG 0x04 -#define SRNG_SR_DRDY WHAL_MASK(0) /* Data ready */ -#define SRNG_SR_CECS WHAL_MASK(1) /* Clock error current status */ -#define SRNG_SR_SECS WHAL_MASK(2) /* Seed error current status */ -#define SRNG_SR_CEIS WHAL_MASK(5) /* Clock error interrupt status */ -#define SRNG_SR_SEIS WHAL_MASK(6) /* Seed error interrupt status */ +#define RNG_SR_REG 0x04 +#define RNG_SR_DRDY_Pos 0 /* Data ready */ +#define RNG_SR_DRDY_Msk (1UL << RNG_SR_DRDY_Pos) + +#define RNG_SR_CECS_Pos 1 /* Clock error current status */ +#define RNG_SR_CECS_Msk (1UL << RNG_SR_CECS_Pos) + +#define RNG_SR_SECS_Pos 2 /* Seed error current status */ +#define RNG_SR_SECS_Msk (1UL << RNG_SR_SECS_Pos) + +#define RNG_SR_CEIS_Pos 5 /* Clock error interrupt status */ +#define RNG_SR_CEIS_Msk (1UL << RNG_SR_CEIS_Pos) + +#define RNG_SR_SEIS_Pos 6 /* Seed error interrupt status */ +#define RNG_SR_SEIS_Msk (1UL << RNG_SR_SEIS_Pos) /* Data Register - 32-bit random value */ -#define SRNG_DR_REG 0x08 +#define RNG_DR_REG 0x08 whal_Error whal_Stm32wbRng_Init(whal_Rng *rngDev) { @@ -79,29 +91,29 @@ whal_Error whal_Stm32wbRng_Generate(whal_Rng *rngDev, uint8_t *rngData, size_t r size_t offset = 0; /* Enable the RNG peripheral */ - whal_Reg_Update(reg->base, SRNG_CR_REG, SRNG_CR_RNGEN, - whal_SetBits(SRNG_CR_RNGEN, 1)); + whal_Reg_Update(reg->base, RNG_CR_REG, RNG_CR_RNGEN_Msk, + whal_SetBits(RNG_CR_RNGEN_Msk, RNG_CR_RNGEN_Pos, 1)); while (offset < rngDataSz) { /* Wait for a random value to be ready */ do { /* Check for seed or clock error */ - whal_Reg_Get(reg->base, SRNG_SR_REG, SRNG_SR_SECS, &status); + whal_Reg_Get(reg->base, RNG_SR_REG, RNG_SR_SECS_Msk, RNG_SR_SECS_Pos, &status); if (status) { err = WHAL_EHARDWARE; goto exit; } - whal_Reg_Get(reg->base, SRNG_SR_REG, SRNG_SR_CECS, &status); + whal_Reg_Get(reg->base, RNG_SR_REG, RNG_SR_CECS_Msk, RNG_SR_CECS_Pos, &status); if (status) { err = WHAL_EHARDWARE; goto exit; } - whal_Reg_Get(reg->base, SRNG_SR_REG, SRNG_SR_DRDY, &status); + whal_Reg_Get(reg->base, RNG_SR_REG, RNG_SR_DRDY_Msk, RNG_SR_DRDY_Pos, &status); } while (!status); /* Read 32-bit random value */ - uint32_t rnd = *(volatile uint32_t *)(reg->base + SRNG_DR_REG); + uint32_t rnd = *(volatile uint32_t *)(reg->base + RNG_DR_REG); /* Copy bytes into output buffer */ for (size_t i = 0; i < 4 && offset < rngDataSz; i++, offset++) { @@ -111,8 +123,8 @@ whal_Error whal_Stm32wbRng_Generate(whal_Rng *rngDev, uint8_t *rngData, size_t r exit: /* Disable the RNG peripheral */ - whal_Reg_Update(reg->base, SRNG_CR_REG, SRNG_CR_RNGEN, - whal_SetBits(SRNG_CR_RNGEN, 0)); + whal_Reg_Update(reg->base, RNG_CR_REG, RNG_CR_RNGEN_Msk, + whal_SetBits(RNG_CR_RNGEN_Msk, RNG_CR_RNGEN_Pos, 0)); return err; } diff --git a/src/spi/stm32wb_spi.c b/src/spi/stm32wb_spi.c index 83c69bb..1066933 100644 --- a/src/spi/stm32wb_spi.c +++ b/src/spi/stm32wb_spi.c @@ -15,32 +15,54 @@ */ /* Control Register 1 - master config, clock, enable */ -#define SSPI_CR1_REG 0x00 -#define SSPI_CR1_CPHA WHAL_MASK(0) /* Clock phase */ -#define SSPI_CR1_CPOL WHAL_MASK(1) /* Clock polarity */ -#define SSPI_CR1_MSTR WHAL_MASK(2) /* Master selection */ -#define SSPI_CR1_BR WHAL_MASK_RANGE(5, 3) /* Baud rate prescaler */ -#define SSPI_CR1_SPE WHAL_MASK(6) /* SPI enable */ -#define SSPI_CR1_SSI WHAL_MASK(8) /* Internal slave select */ -#define SSPI_CR1_SSM WHAL_MASK(9) /* Software slave management */ +#define SPI_CR1_REG 0x00 +#define SPI_CR1_CPHA_Pos 0 /* Clock phase */ +#define SPI_CR1_CPHA_Msk (1UL << SPI_CR1_CPHA_Pos) + +#define SPI_CR1_CPOL_Pos 1 /* Clock polarity */ +#define SPI_CR1_CPOL_Msk (1UL << SPI_CR1_CPOL_Pos) + +#define SPI_CR1_MSTR_Pos 2 /* Master selection */ +#define SPI_CR1_MSTR_Msk (1UL << SPI_CR1_MSTR_Pos) + +#define SPI_CR1_BR_Pos 3 /* Baud rate prescaler */ +#define SPI_CR1_BR_Msk (WHAL_BITMASK(3) << SPI_CR1_BR_Pos) + +#define SPI_CR1_SPE_Pos 6 /* SPI enable */ +#define SPI_CR1_SPE_Msk (1UL << SPI_CR1_SPE_Pos) + +#define SPI_CR1_SSI_Pos 8 /* Internal slave select */ +#define SPI_CR1_SSI_Msk (1UL << SPI_CR1_SSI_Pos) + +#define SPI_CR1_SSM_Pos 9 /* Software slave management */ +#define SPI_CR1_SSM_Msk (1UL << SPI_CR1_SSM_Pos) /* Control Register 2 - data size, FIFO threshold */ -#define SSPI_CR2_REG 0x04 -#define SSPI_CR2_DS WHAL_MASK_RANGE(11, 8) /* Data size (0111 = 8-bit) */ -#define SSPI_CR2_FRXTH WHAL_MASK(12) /* FIFO reception threshold */ +#define SPI_CR2_REG 0x04 +#define SPI_CR2_DS_Pos 8 /* Data size (0111 = 8-bit) */ +#define SPI_CR2_DS_Msk (WHAL_BITMASK(4) << SPI_CR2_DS_Pos) + +#define SPI_CR2_FRXTH_Pos 12 /* FIFO reception threshold */ +#define SPI_CR2_FRXTH_Msk (1UL << SPI_CR2_FRXTH_Pos) /* Status Register */ -#define SSPI_SR_REG 0x08 -#define SSPI_SR_RXNE WHAL_MASK(0) /* Receive buffer not empty */ -#define SSPI_SR_TXE WHAL_MASK(1) /* Transmit buffer empty */ -#define SSPI_SR_BSY WHAL_MASK(7) /* Busy flag */ +#define SPI_SR_REG 0x08 +#define SPI_SR_RXNE_Pos 0 /* Receive buffer not empty */ +#define SPI_SR_RXNE_Msk (1UL << SPI_SR_RXNE_Pos) + +#define SPI_SR_TXE_Pos 1 /* Transmit buffer empty */ +#define SPI_SR_TXE_Msk (1UL << SPI_SR_TXE_Pos) + +#define SPI_SR_BSY_Pos 7 /* Busy flag */ +#define SPI_SR_BSY_Msk (1UL << SPI_SR_BSY_Pos) /* Data Register - 8/16-bit access */ -#define SSPI_DR_REG 0x0C -#define SSPI_DR_MASK WHAL_MASK_RANGE(7, 0) +#define SPI_DR_REG 0x0C +#define SPI_DR_Pos 0 +#define SPI_DR_Msk (WHAL_BITMASK(8) << SPI_DR_Pos) /* 8-bit data size value for DS field */ -#define SSPI_DS_8BIT 0x7 +#define SPI_DS_8BIT 0x7 /* * Calculate the baud rate prescaler index for a target baud rate. @@ -86,19 +108,19 @@ static void whal_Stm32wbSpi_ApplyComCfg(const whal_Regmap *reg, cpha = comCfg->mode & 1; /* Disable SPE before reconfiguring */ - whal_Reg_Update(reg->base, SSPI_CR1_REG, SSPI_CR1_SPE, - whal_SetBits(SSPI_CR1_SPE, 0)); + whal_Reg_Update(reg->base, SPI_CR1_REG, SPI_CR1_SPE_Msk, + whal_SetBits(SPI_CR1_SPE_Msk, SPI_CR1_SPE_Pos, 0)); /* Set mode and baud rate */ - whal_Reg_Update(reg->base, SSPI_CR1_REG, - SSPI_CR1_CPOL | SSPI_CR1_CPHA | SSPI_CR1_BR, - whal_SetBits(SSPI_CR1_CPOL, cpol) | - whal_SetBits(SSPI_CR1_CPHA, cpha) | - whal_SetBits(SSPI_CR1_BR, br)); + whal_Reg_Update(reg->base, SPI_CR1_REG, + SPI_CR1_CPOL_Msk | SPI_CR1_CPHA_Msk | SPI_CR1_BR_Msk, + whal_SetBits(SPI_CR1_CPOL_Msk, SPI_CR1_CPOL_Pos, cpol) | + whal_SetBits(SPI_CR1_CPHA_Msk, SPI_CR1_CPHA_Pos, cpha) | + whal_SetBits(SPI_CR1_BR_Msk, SPI_CR1_BR_Pos, br)); /* Re-enable SPE */ - whal_Reg_Update(reg->base, SSPI_CR1_REG, SSPI_CR1_SPE, - whal_SetBits(SSPI_CR1_SPE, 1)); + whal_Reg_Update(reg->base, SPI_CR1_REG, SPI_CR1_SPE_Msk, + whal_SetBits(SPI_CR1_SPE_Msk, SPI_CR1_SPE_Pos, 1)); } whal_Error whal_Stm32wbSpi_Init(whal_Spi *spiDev) @@ -120,17 +142,17 @@ whal_Error whal_Stm32wbSpi_Init(whal_Spi *spiDev) } /* Master mode with software slave management */ - whal_Reg_Update(reg->base, SSPI_CR1_REG, - SSPI_CR1_MSTR | SSPI_CR1_SSM | SSPI_CR1_SSI, - whal_SetBits(SSPI_CR1_MSTR, 1) | - whal_SetBits(SSPI_CR1_SSM, 1) | - whal_SetBits(SSPI_CR1_SSI, 1)); + whal_Reg_Update(reg->base, SPI_CR1_REG, + SPI_CR1_MSTR_Msk | SPI_CR1_SSM_Msk | SPI_CR1_SSI_Msk, + whal_SetBits(SPI_CR1_MSTR_Msk, SPI_CR1_MSTR_Pos, 1) | + whal_SetBits(SPI_CR1_SSM_Msk, SPI_CR1_SSM_Pos, 1) | + whal_SetBits(SPI_CR1_SSI_Msk, SPI_CR1_SSI_Pos, 1)); /* 8-bit data size and FIFO receive threshold for 8-bit */ - whal_Reg_Update(reg->base, SSPI_CR2_REG, - SSPI_CR2_DS | SSPI_CR2_FRXTH, - whal_SetBits(SSPI_CR2_DS, SSPI_DS_8BIT) | - whal_SetBits(SSPI_CR2_FRXTH, 1)); + whal_Reg_Update(reg->base, SPI_CR2_REG, + SPI_CR2_DS_Msk | SPI_CR2_FRXTH_Msk, + whal_SetBits(SPI_CR2_DS_Msk, SPI_CR2_DS_Pos, SPI_DS_8BIT) | + whal_SetBits(SPI_CR2_FRXTH_Msk, SPI_CR2_FRXTH_Pos, 1)); return WHAL_SUCCESS; } @@ -149,8 +171,8 @@ whal_Error whal_Stm32wbSpi_Deinit(whal_Spi *spiDev) cfg = (whal_Stm32wbSpi_Cfg *)spiDev->cfg; /* Disable SPI */ - whal_Reg_Update(reg->base, SSPI_CR1_REG, SSPI_CR1_SPE, - whal_SetBits(SSPI_CR1_SPE, 0)); + whal_Reg_Update(reg->base, SPI_CR1_REG, SPI_CR1_SPE_Msk, + whal_SetBits(SPI_CR1_SPE_Msk, SPI_CR1_SPE_Pos, 0)); err = whal_Clock_Disable(cfg->clkCtrl, cfg->clk); if (err) { @@ -184,22 +206,22 @@ whal_Error whal_Stm32wbSpi_SendRecv(whal_Spi *spiDev, void *spiComCfg, const uin if (txLen && tx) { /* Wait for TX buffer empty */ do { - whal_Reg_Get(reg->base, SSPI_SR_REG, SSPI_SR_TXE, &status); + whal_Reg_Get(reg->base, SPI_SR_REG, SPI_SR_TXE_Msk, SPI_SR_TXE_Pos, &status); } while (!status); /* Write data or dummy byte */ uint8_t txByte = (i >= txLen) ? tx[txLen-1] : tx[i]; - *(volatile uint8_t *)(reg->base + SSPI_DR_REG) = txByte; + *(volatile uint8_t *)(reg->base + SPI_DR_REG) = txByte; } if (rxLen && rx) { /* Wait for RX buffer not empty */ do { - whal_Reg_Get(reg->base, SSPI_SR_REG, SSPI_SR_RXNE, &status); + whal_Reg_Get(reg->base, SPI_SR_REG, SPI_SR_RXNE_Msk, SPI_SR_RXNE_Pos, &status); } while (!status); /* Read received byte */ - d = *(volatile uint8_t *)(reg->base + SSPI_DR_REG); + d = *(volatile uint8_t *)(reg->base + SPI_DR_REG); if (i < rxLen) { rx[i] = (uint8_t)d; } @@ -208,7 +230,7 @@ whal_Error whal_Stm32wbSpi_SendRecv(whal_Spi *spiDev, void *spiComCfg, const uin /* Wait for not busy */ do { - whal_Reg_Get(reg->base, SSPI_SR_REG, SSPI_SR_BSY, &status); + whal_Reg_Get(reg->base, SPI_SR_REG, SPI_SR_BSY_Msk, SPI_SR_BSY_Pos, &status); } while (status); return WHAL_SUCCESS; diff --git a/src/supply/pic32cz_supc.c b/src/supply/pic32cz_supc.c index 29de61d..9c31d1e 100644 --- a/src/supply/pic32cz_supc.c +++ b/src/supply/pic32cz_supc.c @@ -2,8 +2,9 @@ #include #include -#define PIC32CZ_VREGCTRL_REG 0x1C -#define PIC32CZ_VREGCTRL_AVREGEN WHAL_MASK_RANGE(18, 16) +#define VREGCTRL_REG 0x1C +#define VREGCTRL_AVREGEN_Pos 16 +#define VREGCTRL_AVREGEN_Msk (WHAL_BITMASK(3) << VREGCTRL_AVREGEN_Pos) whal_Error whal_Pic32czSupc_Init(whal_Supply *supplyCtrl) @@ -24,8 +25,8 @@ whal_Error whal_Pic32czSupc_Enable(whal_Supply *supplyCtrl, void *supply) whal_Pic32czSupc_Supply *picSupply = supply; - whal_Reg_Update(supplyCtrl->regmap.base, PIC32CZ_VREGCTRL_REG, picSupply->enableMask, - whal_SetBits(picSupply->enableMask, 1)); + whal_Reg_Update(supplyCtrl->regmap.base, VREGCTRL_REG, picSupply->enableMask, + whal_SetBits(picSupply->enableMask, picSupply->enablePos, 1)); return WHAL_SUCCESS; } @@ -38,8 +39,8 @@ whal_Error whal_Pic32czSupc_Disable(whal_Supply *supplyCtrl, void *supply) whal_Pic32czSupc_Supply *picSupply = supply; - whal_Reg_Update(supplyCtrl->regmap.base, PIC32CZ_VREGCTRL_REG, picSupply->enableMask, - whal_SetBits(picSupply->enableMask, 0)); + whal_Reg_Update(supplyCtrl->regmap.base, VREGCTRL_REG, picSupply->enableMask, + whal_SetBits(picSupply->enableMask, picSupply->enablePos, 0)); return WHAL_SUCCESS; } diff --git a/src/timer/systick.c b/src/timer/systick.c index 92a41ef..5dc5917 100644 --- a/src/timer/systick.c +++ b/src/timer/systick.c @@ -4,19 +4,27 @@ #include #define SYSTICK_CSR_REG 0x00 -#define SYSTICK_CSR_ENABLE WHAL_MASK(0) -#define SYSTICK_CSR_TICKINT WHAL_MASK(1) -#define SYSTICK_CSR_CLKSOURCE WHAL_MASK(2) -#define SYSTICK_CSR_COUNTFLAG WHAL_MASK(16) +#define SYSTICK_CSR_ENABLE_Pos 0 +#define SYSTICK_CSR_ENABLE_Msk (1UL << SYSTICK_CSR_ENABLE_Pos) + +#define SYSTICK_CSR_TICKINT_Pos 1 +#define SYSTICK_CSR_TICKINT_Msk (1UL << SYSTICK_CSR_TICKINT_Pos) + +#define SYSTICK_CSR_CLKSOURCE_Pos 2 +#define SYSTICK_CSR_CLKSOURCE_Msk (1UL << SYSTICK_CSR_CLKSOURCE_Pos) + +#define SYSTICK_CSR_COUNTFLAG_Pos 16 +#define SYSTICK_CSR_COUNTFLAG_Msk (1UL << SYSTICK_CSR_COUNTFLAG_Pos) #define SYSTICK_RVR_REG 0x04 -#define SYSTICK_RVR_RELOAD WHAL_MASK_RANGE(23, 0) +#define SYSTICK_RVR_RELOAD_Pos 0 +#define SYSTICK_RVR_RELOAD_Msk (WHAL_BITMASK(24) << SYSTICK_RVR_RELOAD_Pos) whal_Error SysTick_Init(whal_Timer *timerDev) { whal_SysTick_Cfg *cfg; const whal_Regmap *reg = &timerDev->regmap; - + if (!timerDev || !timerDev->cfg) { return WHAL_EINVAL; } @@ -24,13 +32,13 @@ whal_Error SysTick_Init(whal_Timer *timerDev) cfg = (whal_SysTick_Cfg *)timerDev->cfg; whal_Reg_Update(reg->base, SYSTICK_CSR_REG, - SYSTICK_CSR_CLKSOURCE | SYSTICK_CSR_TICKINT, - whal_SetBits(SYSTICK_CSR_CLKSOURCE, cfg->clkSrc) | - whal_SetBits(SYSTICK_CSR_TICKINT, cfg->tickInt)); + SYSTICK_CSR_CLKSOURCE_Msk | SYSTICK_CSR_TICKINT_Msk, + whal_SetBits(SYSTICK_CSR_CLKSOURCE_Msk, SYSTICK_CSR_CLKSOURCE_Pos, cfg->clkSrc) | + whal_SetBits(SYSTICK_CSR_TICKINT_Msk, SYSTICK_CSR_TICKINT_Pos, cfg->tickInt)); - whal_Reg_Update(reg->base, SYSTICK_RVR_REG, - SYSTICK_RVR_RELOAD, - whal_SetBits(SYSTICK_RVR_RELOAD, cfg->cyclesPerTick)); + whal_Reg_Update(reg->base, SYSTICK_RVR_REG, + SYSTICK_RVR_RELOAD_Msk, + whal_SetBits(SYSTICK_RVR_RELOAD_Msk, SYSTICK_RVR_RELOAD_Pos, cfg->cyclesPerTick)); return WHAL_SUCCESS; } @@ -43,13 +51,13 @@ whal_Error SysTick_Deinit(whal_Timer *timerDev) whal_Error SysTick_Start(whal_Timer *timerDev) { const whal_Regmap *reg = &timerDev->regmap; - + if (!timerDev || !timerDev->cfg) { return WHAL_EINVAL; } - whal_Reg_Update(reg->base, SYSTICK_CSR_REG, SYSTICK_CSR_ENABLE, - whal_SetBits(SYSTICK_CSR_ENABLE, 1)); + whal_Reg_Update(reg->base, SYSTICK_CSR_REG, SYSTICK_CSR_ENABLE_Msk, + whal_SetBits(SYSTICK_CSR_ENABLE_Msk, SYSTICK_CSR_ENABLE_Pos, 1)); return WHAL_SUCCESS; } @@ -57,13 +65,13 @@ whal_Error SysTick_Start(whal_Timer *timerDev) whal_Error SysTick_Stop(whal_Timer *timerDev) { const whal_Regmap *reg = &timerDev->regmap; - + if (!timerDev || !timerDev->cfg) { return WHAL_EINVAL; } - whal_Reg_Update(reg->base, SYSTICK_CSR_REG, SYSTICK_CSR_ENABLE, - whal_SetBits(SYSTICK_CSR_ENABLE, 0)); + whal_Reg_Update(reg->base, SYSTICK_CSR_REG, SYSTICK_CSR_ENABLE_Msk, + whal_SetBits(SYSTICK_CSR_ENABLE_Msk, SYSTICK_CSR_ENABLE_Pos, 0)); return WHAL_SUCCESS; } diff --git a/src/uart/pic32cz_uart.c b/src/uart/pic32cz_uart.c index 4656431..f457429 100644 --- a/src/uart/pic32cz_uart.c +++ b/src/uart/pic32cz_uart.c @@ -7,88 +7,164 @@ #include /* SERCOM USART Register Offsets */ -#define SERCOM_USART_CTRLA_REG 0x00 -#define SERCOM_USART_CTRLB_REG 0x04 -#define SERCOM_USART_CTRLC_REG 0x08 -#define SERCOM_USART_BAUD_REG 0x0C -#define SERCOM_USART_INTENCLR_REG 0x14 -#define SERCOM_USART_INTENSET_REG 0x16 -#define SERCOM_USART_INTFLAG_REG 0x18 -#define SERCOM_USART_STATUS_REG 0x1A -#define SERCOM_USART_SYNCBUSY_REG 0x1C -#define SERCOM_USART_DATA_REG 0x28 +#define USART_CTRLA_REG 0x00 +#define USART_CTRLB_REG 0x04 +#define USART_CTRLC_REG 0x08 +#define USART_BAUD_REG 0x0C +#define USART_INTENCLR_REG 0x14 +#define USART_INTENSET_REG 0x16 +#define USART_INTFLAG_REG 0x18 +#define USART_STATUS_REG 0x1A +#define USART_SYNCBUSY_REG 0x1C +#define USART_DATA_REG 0x28 /* CTRLA Register Bit Definitions */ -#define SERCOM_USART_CTRLA_SWRST WHAL_MASK(0) -#define SERCOM_USART_CTRLA_ENABLE WHAL_MASK(1) -#define SERCOM_USART_CTRLA_MODE_MASK WHAL_MASK_RANGE(4, 2) -#define SERCOM_USART_CTRLA_MODE_USART_INT_CLK 0x1 -#define SERCOM_USART_CTRLA_RUNSTDBY WHAL_MASK(7) -#define SERCOM_USART_CTRLA_IBON WHAL_MASK(8) -#define SERCOM_USART_CTRLA_TXINV WHAL_MASK(9) -#define SERCOM_USART_CTRLA_RXINV WHAL_MASK(10) -#define SERCOM_USART_CTRLA_SAMPR_MASK WHAL_MASK_RANGE(15, 13) -#define SERCOM_USART_CTRLA_SAMPR_16X_ARITH 0x0 -#define SERCOM_USART_CTRLA_SAMPR_16X_FRAC 0x1 -#define SERCOM_USART_CTRLA_SAMPR_8X_ARITH 0x2 -#define SERCOM_USART_CTRLA_SAMPR_8X_FRAC 0x3 -#define SERCOM_USART_CTRLA_SAMPR_3X_ARITH 0x4 -#define SERCOM_USART_CTRLA_TXPO_MASK WHAL_MASK_RANGE(17, 16) -#define SERCOM_USART_CTRLA_RXPO_MASK WHAL_MASK_RANGE(21, 20) -#define SERCOM_USART_CTRLA_SAMPA_MASK WHAL_MASK_RANGE(23, 22) -#define SERCOM_USART_CTRLA_FORM_MASK WHAL_MASK_RANGE(27, 24) -#define SERCOM_USART_CTRLA_FORM_USART 0x0 -#define SERCOM_USART_CTRLA_FORM_PARITY 0x1 -#define SERCOM_USART_CTRLA_CMODE WHAL_MASK(28) -#define SERCOM_USART_CTRLA_CPOL WHAL_MASK(29) -#define SERCOM_USART_CTRLA_DORD WHAL_MASK(30) +#define USART_CTRLA_SWRST_Pos 0 +#define USART_CTRLA_SWRST_Msk (1UL << USART_CTRLA_SWRST_Pos) + +#define USART_CTRLA_ENABLE_Pos 1 +#define USART_CTRLA_ENABLE_Msk (1UL << USART_CTRLA_ENABLE_Pos) + +#define USART_CTRLA_MODE_Pos 2 +#define USART_CTRLA_MODE_Msk (WHAL_BITMASK(3) << USART_CTRLA_MODE_Pos) +#define USART_CTRLA_MODE_USART_INT_CLK 0x1 + +#define USART_CTRLA_RUNSTDBY_Pos 7 +#define USART_CTRLA_RUNSTDBY_Msk (1UL << USART_CTRLA_RUNSTDBY_Pos) + +#define USART_CTRLA_IBON_Pos 8 +#define USART_CTRLA_IBON_Msk (1UL << USART_CTRLA_IBON_Pos) + +#define USART_CTRLA_TXINV_Pos 9 +#define USART_CTRLA_TXINV_Msk (1UL << USART_CTRLA_TXINV_Pos) + +#define USART_CTRLA_RXINV_Pos 10 +#define USART_CTRLA_RXINV_Msk (1UL << USART_CTRLA_RXINV_Pos) + +#define USART_CTRLA_SAMPR_Pos 13 +#define USART_CTRLA_SAMPR_Msk (WHAL_BITMASK(3) << USART_CTRLA_SAMPR_Pos) +#define USART_CTRLA_SAMPR_16X_ARITH 0x0 +#define USART_CTRLA_SAMPR_16X_FRAC 0x1 +#define USART_CTRLA_SAMPR_8X_ARITH 0x2 +#define USART_CTRLA_SAMPR_8X_FRAC 0x3 +#define USART_CTRLA_SAMPR_3X_ARITH 0x4 + +#define USART_CTRLA_TXPO_Pos 16 +#define USART_CTRLA_TXPO_Msk (WHAL_BITMASK(2) << USART_CTRLA_TXPO_Pos) + +#define USART_CTRLA_RXPO_Pos 20 +#define USART_CTRLA_RXPO_Msk (WHAL_BITMASK(2) << USART_CTRLA_RXPO_Pos) + +#define USART_CTRLA_SAMPA_Pos 22 +#define USART_CTRLA_SAMPA_Msk (WHAL_BITMASK(2) << USART_CTRLA_SAMPA_Pos) + +#define USART_CTRLA_FORM_Pos 24 +#define USART_CTRLA_FORM_Msk (WHAL_BITMASK(4) << USART_CTRLA_FORM_Pos) +#define USART_CTRLA_FORM_USART 0x0 +#define USART_CTRLA_FORM_PARITY 0x1 + +#define USART_CTRLA_CMODE_Pos 28 +#define USART_CTRLA_CMODE_Msk (1UL << USART_CTRLA_CMODE_Pos) + +#define USART_CTRLA_CPOL_Pos 29 +#define USART_CTRLA_CPOL_Msk (1UL << USART_CTRLA_CPOL_Pos) + +#define USART_CTRLA_DORD_Pos 30 +#define USART_CTRLA_DORD_Msk (1UL << USART_CTRLA_DORD_Pos) /* CTRLB Register Bit Definitions */ -#define SERCOM_USART_CTRLB_CHSIZE_MASK WHAL_MASK_RANGE(2, 0) -#define SERCOM_USART_CTRLB_CHSIZE_8BIT 0x0 -#define SERCOM_USART_CTRLB_CHSIZE_9BIT 0x1 -#define SERCOM_USART_CTRLB_CHSIZE_5BIT 0x5 -#define SERCOM_USART_CTRLB_CHSIZE_6BIT 0x6 -#define SERCOM_USART_CTRLB_CHSIZE_7BIT 0x7 -#define SERCOM_USART_CTRLB_SBMODE WHAL_MASK(6) -#define SERCOM_USART_CTRLB_COLDEN WHAL_MASK(8) -#define SERCOM_USART_CTRLB_SFDE WHAL_MASK(9) -#define SERCOM_USART_CTRLB_ENC WHAL_MASK(10) -#define SERCOM_USART_CTRLB_PMODE WHAL_MASK(13) -#define SERCOM_USART_CTRLB_TXEN WHAL_MASK(16) -#define SERCOM_USART_CTRLB_RXEN WHAL_MASK(17) +#define USART_CTRLB_CHSIZE_Pos 0 +#define USART_CTRLB_CHSIZE_Msk (WHAL_BITMASK(3) << USART_CTRLB_CHSIZE_Pos) +#define USART_CTRLB_CHSIZE_8BIT 0x0 +#define USART_CTRLB_CHSIZE_9BIT 0x1 +#define USART_CTRLB_CHSIZE_5BIT 0x5 +#define USART_CTRLB_CHSIZE_6BIT 0x6 +#define USART_CTRLB_CHSIZE_7BIT 0x7 + +#define USART_CTRLB_SBMODE_Pos 6 +#define USART_CTRLB_SBMODE_Msk (1UL << USART_CTRLB_SBMODE_Pos) + +#define USART_CTRLB_COLDEN_Pos 8 +#define USART_CTRLB_COLDEN_Msk (1UL << USART_CTRLB_COLDEN_Pos) + +#define USART_CTRLB_SFDE_Pos 9 +#define USART_CTRLB_SFDE_Msk (1UL << USART_CTRLB_SFDE_Pos) + +#define USART_CTRLB_ENC_Pos 10 +#define USART_CTRLB_ENC_Msk (1UL << USART_CTRLB_ENC_Pos) + +#define USART_CTRLB_PMODE_Pos 13 +#define USART_CTRLB_PMODE_Msk (1UL << USART_CTRLB_PMODE_Pos) + +#define USART_CTRLB_TXEN_Pos 16 +#define USART_CTRLB_TXEN_Msk (1UL << USART_CTRLB_TXEN_Pos) + +#define USART_CTRLB_RXEN_Pos 17 +#define USART_CTRLB_RXEN_Msk (1UL << USART_CTRLB_RXEN_Pos) /* INTFLAG Register Bit Definitions */ -#define SERCOM_USART_INTFLAG_DRE WHAL_MASK(0) -#define SERCOM_USART_INTFLAG_TXC WHAL_MASK(1) -#define SERCOM_USART_INTFLAG_RXC WHAL_MASK(2) -#define SERCOM_USART_INTFLAG_RXS WHAL_MASK(3) -#define SERCOM_USART_INTFLAG_CTSIC WHAL_MASK(4) -#define SERCOM_USART_INTFLAG_RXBRK WHAL_MASK(5) -#define SERCOM_USART_INTFLAG_ERROR WHAL_MASK(7) +#define USART_INTFLAG_DRE_Pos 0 +#define USART_INTFLAG_DRE_Msk (1UL << USART_INTFLAG_DRE_Pos) + +#define USART_INTFLAG_TXC_Pos 1 +#define USART_INTFLAG_TXC_Msk (1UL << USART_INTFLAG_TXC_Pos) + +#define USART_INTFLAG_RXC_Pos 2 +#define USART_INTFLAG_RXC_Msk (1UL << USART_INTFLAG_RXC_Pos) + +#define USART_INTFLAG_RXS_Pos 3 +#define USART_INTFLAG_RXS_Msk (1UL << USART_INTFLAG_RXS_Pos) + +#define USART_INTFLAG_CTSIC_Pos 4 +#define USART_INTFLAG_CTSIC_Msk (1UL << USART_INTFLAG_CTSIC_Pos) + +#define USART_INTFLAG_RXBRK_Pos 5 +#define USART_INTFLAG_RXBRK_Msk (1UL << USART_INTFLAG_RXBRK_Pos) + +#define USART_INTFLAG_ERROR_Pos 7 +#define USART_INTFLAG_ERROR_Msk (1UL << USART_INTFLAG_ERROR_Pos) /* STATUS Register Bit Definitions */ -#define SERCOM_USART_STATUS_PERR WHAL_MASK(0) -#define SERCOM_USART_STATUS_FERR WHAL_MASK(1) -#define SERCOM_USART_STATUS_BUFOVF WHAL_MASK(2) -#define SERCOM_USART_STATUS_CTS WHAL_MASK(3) -#define SERCOM_USART_STATUS_ISF WHAL_MASK(4) -#define SERCOM_USART_STATUS_COLL WHAL_MASK(5) -#define SERCOM_USART_STATUS_TXE WHAL_MASK(6) +#define USART_STATUS_PERR_Pos 0 +#define USART_STATUS_PERR_Msk (1UL << USART_STATUS_PERR_Pos) + +#define USART_STATUS_FERR_Pos 1 +#define USART_STATUS_FERR_Msk (1UL << USART_STATUS_FERR_Pos) + +#define USART_STATUS_BUFOVF_Pos 2 +#define USART_STATUS_BUFOVF_Msk (1UL << USART_STATUS_BUFOVF_Pos) + +#define USART_STATUS_CTS_Pos 3 +#define USART_STATUS_CTS_Msk (1UL << USART_STATUS_CTS_Pos) + +#define USART_STATUS_ISF_Pos 4 +#define USART_STATUS_ISF_Msk (1UL << USART_STATUS_ISF_Pos) + +#define USART_STATUS_COLL_Pos 5 +#define USART_STATUS_COLL_Msk (1UL << USART_STATUS_COLL_Pos) + +#define USART_STATUS_TXE_Pos 6 +#define USART_STATUS_TXE_Msk (1UL << USART_STATUS_TXE_Pos) /* SYNCBUSY Register Bit Definitions */ -#define SERCOM_USART_SYNCBUSY_SWRST WHAL_MASK(0) -#define SERCOM_USART_SYNCBUSY_ENABLE WHAL_MASK(1) -#define SERCOM_USART_SYNCBUSY_CTRLB WHAL_MASK(2) +#define USART_SYNCBUSY_SWRST_Pos 0 +#define USART_SYNCBUSY_SWRST_Msk (1UL << USART_SYNCBUSY_SWRST_Pos) + +#define USART_SYNCBUSY_ENABLE_Pos 1 +#define USART_SYNCBUSY_ENABLE_Msk (1UL << USART_SYNCBUSY_ENABLE_Pos) + +#define USART_SYNCBUSY_CTRLB_Pos 2 +#define USART_SYNCBUSY_CTRLB_Msk (1UL << USART_SYNCBUSY_CTRLB_Pos) /* DATA Register */ -#define SERCOM_USART_DATA_MASK WHAL_MASK_RANGE(8, 0) +#define USART_DATA_Pos 0 +#define USART_DATA_Msk (WHAL_BITMASK(9) << USART_DATA_Pos) -static void whal_Pic32czUart_WaitSync(const whal_Regmap *reg, size_t mask) +static void whal_Pic32czUart_WaitSync(const whal_Regmap *reg, size_t mask, size_t pos) { size_t busy = 1; while (busy) { - whal_Reg_Get(reg->base, SERCOM_USART_SYNCBUSY_REG, mask, &busy); + whal_Reg_Get(reg->base, USART_SYNCBUSY_REG, mask, pos, &busy); } } @@ -112,55 +188,55 @@ whal_Error whal_Pic32czUart_Init(whal_Uart *uartDev) } /* Configure CTRLA: internal clock, async mode, LSB first, 16x sampling */ - whal_Reg_Update(reg->base, SERCOM_USART_CTRLA_REG, - SERCOM_USART_CTRLA_MODE_MASK | - SERCOM_USART_CTRLA_SAMPR_MASK | - SERCOM_USART_CTRLA_TXPO_MASK | - SERCOM_USART_CTRLA_RXPO_MASK | - SERCOM_USART_CTRLA_FORM_MASK | - SERCOM_USART_CTRLA_CMODE | - SERCOM_USART_CTRLA_DORD, - whal_SetBits(SERCOM_USART_CTRLA_MODE_MASK, SERCOM_USART_CTRLA_MODE_USART_INT_CLK) | - whal_SetBits(SERCOM_USART_CTRLA_SAMPR_MASK, SERCOM_USART_CTRLA_SAMPR_16X_ARITH) | - whal_SetBits(SERCOM_USART_CTRLA_TXPO_MASK, cfg->txPad) | - whal_SetBits(SERCOM_USART_CTRLA_RXPO_MASK, cfg->rxPad) | - whal_SetBits(SERCOM_USART_CTRLA_FORM_MASK, SERCOM_USART_CTRLA_FORM_USART) | - whal_SetBits(SERCOM_USART_CTRLA_CMODE, 0) | /* Async mode */ - whal_SetBits(SERCOM_USART_CTRLA_DORD, 1)); /* LSB first */ + whal_Reg_Update(reg->base, USART_CTRLA_REG, + USART_CTRLA_MODE_Msk | + USART_CTRLA_SAMPR_Msk | + USART_CTRLA_TXPO_Msk | + USART_CTRLA_RXPO_Msk | + USART_CTRLA_FORM_Msk | + USART_CTRLA_CMODE_Msk | + USART_CTRLA_DORD_Msk, + whal_SetBits(USART_CTRLA_MODE_Msk, USART_CTRLA_MODE_Pos, USART_CTRLA_MODE_USART_INT_CLK) | + whal_SetBits(USART_CTRLA_SAMPR_Msk, USART_CTRLA_SAMPR_Pos, USART_CTRLA_SAMPR_16X_ARITH) | + whal_SetBits(USART_CTRLA_TXPO_Msk, USART_CTRLA_TXPO_Pos, cfg->txPad) | + whal_SetBits(USART_CTRLA_RXPO_Msk, USART_CTRLA_RXPO_Pos, cfg->rxPad) | + whal_SetBits(USART_CTRLA_FORM_Msk, USART_CTRLA_FORM_Pos, USART_CTRLA_FORM_USART) | + whal_SetBits(USART_CTRLA_CMODE_Msk, USART_CTRLA_CMODE_Pos, 0) | /* Async mode */ + whal_SetBits(USART_CTRLA_DORD_Msk, USART_CTRLA_DORD_Pos, 1)); /* LSB first */ /* Configure CTRLB: 8-bit char size, 1 stop bit, no parity */ - whal_Reg_Update(reg->base, SERCOM_USART_CTRLB_REG, - SERCOM_USART_CTRLB_CHSIZE_MASK | - SERCOM_USART_CTRLB_SBMODE | - SERCOM_USART_CTRLB_PMODE, - whal_SetBits(SERCOM_USART_CTRLB_CHSIZE_MASK, SERCOM_USART_CTRLB_CHSIZE_8BIT) | - whal_SetBits(SERCOM_USART_CTRLB_SBMODE, 0) | - whal_SetBits(SERCOM_USART_CTRLB_PMODE, 0)); + whal_Reg_Update(reg->base, USART_CTRLB_REG, + USART_CTRLB_CHSIZE_Msk | + USART_CTRLB_SBMODE_Msk | + USART_CTRLB_PMODE_Msk, + whal_SetBits(USART_CTRLB_CHSIZE_Msk, USART_CTRLB_CHSIZE_Pos, USART_CTRLB_CHSIZE_8BIT) | + whal_SetBits(USART_CTRLB_SBMODE_Msk, USART_CTRLB_SBMODE_Pos, 0) | + whal_SetBits(USART_CTRLB_PMODE_Msk, USART_CTRLB_PMODE_Pos, 0)); /* Wait for CTRLB sync */ - whal_Pic32czUart_WaitSync(reg, SERCOM_USART_SYNCBUSY_CTRLB); + whal_Pic32czUart_WaitSync(reg, USART_SYNCBUSY_CTRLB_Msk, USART_SYNCBUSY_CTRLB_Pos); /* Set baud rate */ - whal_Reg_Update(reg->base, SERCOM_USART_BAUD_REG, + whal_Reg_Update(reg->base, USART_BAUD_REG, 0xFFFF, cfg->baud); /* Enable transmitter and receiver */ - whal_Reg_Update(reg->base, SERCOM_USART_CTRLB_REG, - SERCOM_USART_CTRLB_TXEN | SERCOM_USART_CTRLB_RXEN, - whal_SetBits(SERCOM_USART_CTRLB_TXEN, 1) | - whal_SetBits(SERCOM_USART_CTRLB_RXEN, 1)); + whal_Reg_Update(reg->base, USART_CTRLB_REG, + USART_CTRLB_TXEN_Msk | USART_CTRLB_RXEN_Msk, + whal_SetBits(USART_CTRLB_TXEN_Msk, USART_CTRLB_TXEN_Pos, 1) | + whal_SetBits(USART_CTRLB_RXEN_Msk, USART_CTRLB_RXEN_Pos, 1)); /* Wait for CTRLB sync */ - whal_Pic32czUart_WaitSync(reg, SERCOM_USART_SYNCBUSY_CTRLB); + whal_Pic32czUart_WaitSync(reg, USART_SYNCBUSY_CTRLB_Msk, USART_SYNCBUSY_CTRLB_Pos); /* Enable SERCOM USART */ - whal_Reg_Update(reg->base, SERCOM_USART_CTRLA_REG, - SERCOM_USART_CTRLA_ENABLE, - whal_SetBits(SERCOM_USART_CTRLA_ENABLE, 1)); + whal_Reg_Update(reg->base, USART_CTRLA_REG, + USART_CTRLA_ENABLE_Msk, + whal_SetBits(USART_CTRLA_ENABLE_Msk, USART_CTRLA_ENABLE_Pos, 1)); /* Wait for enable sync */ - whal_Pic32czUart_WaitSync(reg, SERCOM_USART_SYNCBUSY_ENABLE); + whal_Pic32czUart_WaitSync(reg, USART_SYNCBUSY_ENABLE_Msk, USART_SYNCBUSY_ENABLE_Pos); return WHAL_SUCCESS; } @@ -179,21 +255,21 @@ whal_Error whal_Pic32czUart_Deinit(whal_Uart *uartDev) cfg = (whal_Pic32czUart_Cfg *)uartDev->cfg; /* Disable SERCOM USART */ - whal_Reg_Update(reg->base, SERCOM_USART_CTRLA_REG, - SERCOM_USART_CTRLA_ENABLE, - whal_SetBits(SERCOM_USART_CTRLA_ENABLE, 0)); + whal_Reg_Update(reg->base, USART_CTRLA_REG, + USART_CTRLA_ENABLE_Msk, + whal_SetBits(USART_CTRLA_ENABLE_Msk, USART_CTRLA_ENABLE_Pos, 0)); /* Wait for disable sync */ - whal_Pic32czUart_WaitSync(reg, SERCOM_USART_SYNCBUSY_ENABLE); + whal_Pic32czUart_WaitSync(reg, USART_SYNCBUSY_ENABLE_Msk, USART_SYNCBUSY_ENABLE_Pos); /* Disable transmitter and receiver */ - whal_Reg_Update(reg->base, SERCOM_USART_CTRLB_REG, - SERCOM_USART_CTRLB_TXEN | SERCOM_USART_CTRLB_RXEN, - whal_SetBits(SERCOM_USART_CTRLB_TXEN, 0) | - whal_SetBits(SERCOM_USART_CTRLB_RXEN, 0)); + whal_Reg_Update(reg->base, USART_CTRLB_REG, + USART_CTRLB_TXEN_Msk | USART_CTRLB_RXEN_Msk, + whal_SetBits(USART_CTRLB_TXEN_Msk, USART_CTRLB_TXEN_Pos, 0) | + whal_SetBits(USART_CTRLB_RXEN_Msk, USART_CTRLB_RXEN_Pos, 0)); /* Wait for CTRLB sync */ - whal_Pic32czUart_WaitSync(reg, SERCOM_USART_SYNCBUSY_CTRLB); + whal_Pic32czUart_WaitSync(reg, USART_SYNCBUSY_CTRLB_Msk, USART_SYNCBUSY_CTRLB_Pos); /* Disable peripheral clock */ err = whal_Clock_Disable(cfg->clkCtrl, cfg->clk); @@ -219,27 +295,27 @@ whal_Error whal_Pic32czUart_Send(whal_Uart *uartDev, const uint8_t *data, size_t /* Wait for data register to be empty */ while (!dataRegEmpty) { - whal_Reg_Get(reg->base, SERCOM_USART_INTFLAG_REG, - SERCOM_USART_INTFLAG_DRE, &dataRegEmpty); + whal_Reg_Get(reg->base, USART_INTFLAG_REG, + USART_INTFLAG_DRE_Msk, USART_INTFLAG_DRE_Pos, &dataRegEmpty); } /* Write data to transmit register */ - whal_Reg_Update(reg->base, SERCOM_USART_DATA_REG, - SERCOM_USART_DATA_MASK, - whal_SetBits(SERCOM_USART_DATA_MASK, data[i])); + whal_Reg_Update(reg->base, USART_DATA_REG, + USART_DATA_Msk, + whal_SetBits(USART_DATA_Msk, USART_DATA_Pos, data[i])); } /* Wait for transmission complete */ { size_t txComplete = 0; while (!txComplete) { - whal_Reg_Get(reg->base, SERCOM_USART_INTFLAG_REG, - SERCOM_USART_INTFLAG_TXC, &txComplete); + whal_Reg_Get(reg->base, USART_INTFLAG_REG, + USART_INTFLAG_TXC_Msk, USART_INTFLAG_TXC_Pos, &txComplete); } /* Clear TXC flag by writing 1 */ - whal_Reg_Update(reg->base, SERCOM_USART_INTFLAG_REG, - SERCOM_USART_INTFLAG_TXC, - whal_SetBits(SERCOM_USART_INTFLAG_TXC, 1)); + whal_Reg_Update(reg->base, USART_INTFLAG_REG, + USART_INTFLAG_TXC_Msk, + whal_SetBits(USART_INTFLAG_TXC_Msk, USART_INTFLAG_TXC_Pos, 1)); } return WHAL_SUCCESS; @@ -261,13 +337,13 @@ whal_Error whal_Pic32czUart_Recv(whal_Uart *uartDev, uint8_t *data, size_t dataS /* Wait for receive complete */ while (!dataReceived) { - whal_Reg_Get(reg->base, SERCOM_USART_INTFLAG_REG, - SERCOM_USART_INTFLAG_RXC, &dataReceived); + whal_Reg_Get(reg->base, USART_INTFLAG_REG, + USART_INTFLAG_RXC_Msk, USART_INTFLAG_RXC_Pos, &dataReceived); } /* Read received data */ - whal_Reg_Get(reg->base, SERCOM_USART_DATA_REG, - SERCOM_USART_DATA_MASK, &rxData); + whal_Reg_Get(reg->base, USART_DATA_REG, + USART_DATA_Msk, USART_DATA_Pos, &rxData); data[i] = (uint8_t)rxData; } diff --git a/src/uart/stm32wb_uart.c b/src/uart/stm32wb_uart.c index 38ba914..96c8b83 100644 --- a/src/uart/stm32wb_uart.c +++ b/src/uart/stm32wb_uart.c @@ -6,24 +6,37 @@ #include #include -#define STUART_CR1_REG 0x00 -#define STUART_CR1_UE WHAL_MASK(0) -#define STUART_CR1_RE WHAL_MASK(2) -#define STUART_CR1_TE WHAL_MASK(3) +#define UART_CR1_REG 0x00 +#define UART_CR1_UE_Pos 0 +#define UART_CR1_UE_Msk (1UL << UART_CR1_UE_Pos) -#define STUART_BRR_REG 0x0C -#define STUART_BRR_BRR_MASK WHAL_MASK_RANGE(19, 0) +#define UART_CR1_RE_Pos 2 +#define UART_CR1_RE_Msk (1UL << UART_CR1_RE_Pos) -#define STUART_ISR_REG 0x1C -#define STUART_ISR_RXFNE_MASK WHAL_MASK(5) -#define STUART_ISR_TC_MASK WHAL_MASK(6) -#define STUART_ISR_TXE_MASK WHAL_MASK(7) +#define UART_CR1_TE_Pos 3 +#define UART_CR1_TE_Msk (1UL << UART_CR1_TE_Pos) -#define STUART_RDR_REG 0x24 -#define STUART_RDR_RDR_MASK WHAL_MASK_RANGE(8, 0) +#define UART_BRR_REG 0x0C +#define UART_BRR_Pos 0 +#define UART_BRR_Msk (WHAL_BITMASK(20) << UART_BRR_Pos) -#define STUART_TDR_REG 0x28 -#define STUART_TDR_TDR_MASK WHAL_MASK_RANGE(8, 0) +#define UART_ISR_REG 0x1C +#define UART_ISR_RXFNE_Pos 5 +#define UART_ISR_RXFNE_Msk (1UL << UART_ISR_RXFNE_Pos) + +#define UART_ISR_TC_Pos 6 +#define UART_ISR_TC_Msk (1UL << UART_ISR_TC_Pos) + +#define UART_ISR_TXE_Pos 7 +#define UART_ISR_TXE_Msk (1UL << UART_ISR_TXE_Pos) + +#define UART_RDR_REG 0x24 +#define UART_RDR_Pos 0 +#define UART_RDR_Msk (WHAL_BITMASK(9) << UART_RDR_Pos) + +#define UART_TDR_REG 0x28 +#define UART_TDR_Pos 0 +#define UART_TDR_Msk (WHAL_BITMASK(9) << UART_TDR_Pos) whal_Error whal_Stm32wbUart_Init(whal_Uart *uartDev) { @@ -46,16 +59,16 @@ whal_Error whal_Stm32wbUart_Init(whal_Uart *uartDev) } brr = (clockFreq / cfg->baud); - - whal_Reg_Update(reg->base, STUART_BRR_REG, - STUART_BRR_BRR_MASK, - whal_SetBits(STUART_BRR_BRR_MASK, brr)); - whal_Reg_Update(reg->base, STUART_CR1_REG, - STUART_CR1_UE | STUART_CR1_RE | STUART_CR1_TE, - whal_SetBits(STUART_CR1_UE, 1) | - whal_SetBits(STUART_CR1_RE, 1) | - whal_SetBits(STUART_CR1_TE, 1)); - + + whal_Reg_Update(reg->base, UART_BRR_REG, + UART_BRR_Msk, + whal_SetBits(UART_BRR_Msk, UART_BRR_Pos, brr)); + whal_Reg_Update(reg->base, UART_CR1_REG, + UART_CR1_UE_Msk | UART_CR1_RE_Msk | UART_CR1_TE_Msk, + whal_SetBits(UART_CR1_UE_Msk, UART_CR1_UE_Pos, 1) | + whal_SetBits(UART_CR1_RE_Msk, UART_CR1_RE_Pos, 1) | + whal_SetBits(UART_CR1_TE_Msk, UART_CR1_TE_Pos, 1)); + return WHAL_SUCCESS; } @@ -80,16 +93,16 @@ whal_Error whal_Stm32wbLpuart_Init(whal_Uart *uartDev) } brr = (clockFreq / cfg->baud) * 256; - - whal_Reg_Update(reg->base, STUART_BRR_REG, - STUART_BRR_BRR_MASK, - whal_SetBits(STUART_BRR_BRR_MASK, brr)); - whal_Reg_Update(reg->base, STUART_CR1_REG, - STUART_CR1_UE | STUART_CR1_RE | STUART_CR1_TE, - whal_SetBits(STUART_CR1_UE, 1) | - whal_SetBits(STUART_CR1_RE, 1) | - whal_SetBits(STUART_CR1_TE, 1)); - + + whal_Reg_Update(reg->base, UART_BRR_REG, + UART_BRR_Msk, + whal_SetBits(UART_BRR_Msk, UART_BRR_Pos, brr)); + whal_Reg_Update(reg->base, UART_CR1_REG, + UART_CR1_UE_Msk | UART_CR1_RE_Msk | UART_CR1_TE_Msk, + whal_SetBits(UART_CR1_UE_Msk, UART_CR1_UE_Pos, 1) | + whal_SetBits(UART_CR1_RE_Msk, UART_CR1_RE_Pos, 1) | + whal_SetBits(UART_CR1_TE_Msk, UART_CR1_TE_Pos, 1)); + return WHAL_SUCCESS; } @@ -99,15 +112,15 @@ whal_Error whal_Stm32wbUart_Deinit(whal_Uart *uartDev) const whal_Regmap *reg = &uartDev->regmap; whal_Stm32wbUart_Cfg *cfg = (whal_Stm32wbUart_Cfg *)uartDev->cfg; - whal_Reg_Update(reg->base, STUART_CR1_REG, - STUART_CR1_UE | STUART_CR1_RE | STUART_CR1_TE, - whal_SetBits(STUART_CR1_UE, 0) | - whal_SetBits(STUART_CR1_RE, 0) | - whal_SetBits(STUART_CR1_TE, 0)); + whal_Reg_Update(reg->base, UART_CR1_REG, + UART_CR1_UE_Msk | UART_CR1_RE_Msk | UART_CR1_TE_Msk, + whal_SetBits(UART_CR1_UE_Msk, UART_CR1_UE_Pos, 0) | + whal_SetBits(UART_CR1_RE_Msk, UART_CR1_RE_Pos, 0) | + whal_SetBits(UART_CR1_TE_Msk, UART_CR1_TE_Pos, 0)); - whal_Reg_Update(reg->base, STUART_BRR_REG, - STUART_BRR_BRR_MASK, - whal_SetBits(STUART_BRR_BRR_MASK, 0)); + whal_Reg_Update(reg->base, UART_BRR_REG, + UART_BRR_Msk, + whal_SetBits(UART_BRR_Msk, UART_BRR_Pos, 0)); err = whal_Clock_Disable(cfg->clkCtrl, cfg->clk); if (err) { @@ -120,15 +133,15 @@ whal_Error whal_Stm32wbUart_Deinit(whal_Uart *uartDev) whal_Error whal_Stm32wbUart_Send(whal_Uart *uartDev, const uint8_t *data, size_t dataSz) { const whal_Regmap *reg = &uartDev->regmap; - + for (size_t i = 0; i < dataSz; ++i) { size_t txComplete = 0; - whal_Reg_Update(reg->base, STUART_TDR_REG, STUART_TDR_TDR_MASK, - whal_SetBits(STUART_TDR_TDR_MASK, data[i])); + whal_Reg_Update(reg->base, UART_TDR_REG, UART_TDR_Msk, + whal_SetBits(UART_TDR_Msk, UART_TDR_Pos, data[i])); while (!txComplete) { - whal_Reg_Get(reg->base, STUART_ISR_REG, STUART_ISR_TC_MASK, &txComplete); + whal_Reg_Get(reg->base, UART_ISR_REG, UART_ISR_TC_Msk, UART_ISR_TC_Pos, &txComplete); } } @@ -139,16 +152,16 @@ whal_Error whal_Stm32wbUart_Recv(whal_Uart *uartDev, uint8_t *data, size_t dataS { const whal_Regmap *reg = &uartDev->regmap; size_t d; - + for (size_t i = 0; i < dataSz; ++i) { size_t dataReceived = 0; while (!dataReceived) { - whal_Reg_Get(reg->base, STUART_ISR_REG, STUART_ISR_RXFNE_MASK, &dataReceived); + whal_Reg_Get(reg->base, UART_ISR_REG, UART_ISR_RXFNE_Msk, UART_ISR_RXFNE_Pos, &dataReceived); } - whal_Reg_Get(reg->base, STUART_RDR_REG, - STUART_RDR_RDR_MASK, &d); + whal_Reg_Get(reg->base, UART_RDR_REG, + UART_RDR_Msk, UART_RDR_Pos, &d); data[i] = d; } diff --git a/tests/pic32cz/test_clock.c b/tests/pic32cz/test_clock.c index 336db3c..3c27476 100644 --- a/tests/pic32cz/test_clock.c +++ b/tests/pic32cz/test_clock.c @@ -14,7 +14,8 @@ * Offset from clock base: 0x12000 + 0x3C + (inst * 4) */ #define GCLK_PCHCTRL_OFFSET(ch) (0x10000 + 0x80 + ((ch) * 4)) -#define GCLK_PCHCTRL_CHEN WHAL_MASK(6) +#define GCLK_PCHCTRL_CHEN_Pos 6 +#define GCLK_PCHCTRL_CHEN_Msk (1UL << GCLK_PCHCTRL_CHEN_Pos) #define MCLK_CLKMSK_OFFSET(inst) (0x12000 + 0x3C + ((inst) * 4)) @@ -25,7 +26,8 @@ static void test_clock_enable_disable(void) .gclkPeriphChannel = 25, .gclkPeriphSrc = 0, .mclkEnableInst = 1, - .mclkEnableMask = WHAL_MASK(3), + .mclkEnableMask = (1UL << 3), + .mclkEnablePos = 3, }; size_t val = 0; @@ -34,19 +36,19 @@ static void test_clock_enable_disable(void) /* Readback: GCLK PCHCTRL channel 25 CHEN bit should be set */ whal_Reg_Get(g_whalClock.regmap.base, GCLK_PCHCTRL_OFFSET(25), - GCLK_PCHCTRL_CHEN, &val); + GCLK_PCHCTRL_CHEN_Msk, GCLK_PCHCTRL_CHEN_Pos, &val); WHAL_ASSERT_EQ(val, 1); /* Readback: MCLK CLKMSK1 bit 3 should be set */ whal_Reg_Get(g_whalClock.regmap.base, MCLK_CLKMSK_OFFSET(1), - WHAL_MASK(3), &val); + (1UL << 3), 3, &val); WHAL_ASSERT_EQ(val, 1); WHAL_ASSERT_EQ(whal_Clock_Disable(&g_whalClock, &testClk), WHAL_SUCCESS); /* After disable: CHEN should be cleared */ whal_Reg_Get(g_whalClock.regmap.base, GCLK_PCHCTRL_OFFSET(25), - GCLK_PCHCTRL_CHEN, &val); + GCLK_PCHCTRL_CHEN_Msk, GCLK_PCHCTRL_CHEN_Pos, &val); WHAL_ASSERT_EQ(val, 0); /* Re-enable so UART still works for remaining tests */ diff --git a/tests/pic32cz/test_gpio.c b/tests/pic32cz/test_gpio.c index b321a24..d4661e7 100644 --- a/tests/pic32cz/test_gpio.c +++ b/tests/pic32cz/test_gpio.c @@ -27,7 +27,7 @@ static void test_gpio_dir_register(void) /* PB21 should be configured as output (bit 21 set in DIR register) */ size_t val = 0; whal_Reg_Get(g_whalGpio.regmap.base, PORT_DIR_REG(LED_PORT), - WHAL_MASK(LED_HW_PIN), &val); + (1UL << LED_HW_PIN), LED_HW_PIN, &val); WHAL_ASSERT_EQ(val, 1); } @@ -38,7 +38,7 @@ static void test_gpio_set_high(void) /* Readback OUT register bit 21 */ size_t val = 0; whal_Reg_Get(g_whalGpio.regmap.base, PORT_OUT_REG(LED_PORT), - WHAL_MASK(LED_HW_PIN), &val); + (1UL << LED_HW_PIN), LED_HW_PIN, &val); WHAL_ASSERT_EQ(val, 1); } @@ -48,7 +48,7 @@ static void test_gpio_set_low(void) size_t val = 0; whal_Reg_Get(g_whalGpio.regmap.base, PORT_OUT_REG(LED_PORT), - WHAL_MASK(LED_HW_PIN), &val); + (1UL << LED_HW_PIN), LED_HW_PIN, &val); WHAL_ASSERT_EQ(val, 0); } diff --git a/tests/sim/test_bitops.c b/tests/sim/test_bitops.c index 48d38c7..66ddc0b 100644 --- a/tests/sim/test_bitops.c +++ b/tests/sim/test_bitops.c @@ -1,87 +1,72 @@ #include #include "../test.h" -static void test_mask_bit0(void) +static void test_bitmask_4(void) { - WHAL_ASSERT_EQ(WHAL_MASK(0), 1ul); + WHAL_ASSERT_EQ(WHAL_BITMASK(4), 0xFul); } -static void test_mask_bit15(void) +static void test_bitmask_8(void) { - WHAL_ASSERT_EQ(WHAL_MASK(15), (1ul << 15)); + WHAL_ASSERT_EQ(WHAL_BITMASK(8), 0xFFul); } -static void test_mask_bit31(void) +static void test_bitmask_1(void) { - WHAL_ASSERT_EQ(WHAL_MASK(31), (1ul << 31)); -} - -static void test_mask_range_single_bit(void) -{ - WHAL_ASSERT_EQ(WHAL_MASK_RANGE(0, 0), 1ul); - WHAL_ASSERT_EQ(WHAL_MASK_RANGE(7, 7), (1ul << 7)); -} - -static void test_mask_range_multi_bit(void) -{ - WHAL_ASSERT_EQ(WHAL_MASK_RANGE(3, 0), 0xFul); - WHAL_ASSERT_EQ(WHAL_MASK_RANGE(7, 4), 0xF0ul); - WHAL_ASSERT_EQ(WHAL_MASK_RANGE(15, 8), 0xFF00ul); -} - -static void test_mask_range_full_byte(void) -{ - WHAL_ASSERT_EQ(WHAL_MASK_RANGE(7, 0), 0xFFul); + WHAL_ASSERT_EQ(WHAL_BITMASK(1), 1ul); } static void test_setbits_low(void) { - size_t mask = WHAL_MASK_RANGE(3, 0); - WHAL_ASSERT_EQ(whal_SetBits(mask, 0xA), 0xAul); + size_t msk = WHAL_BITMASK(4); + size_t pos = 0; + WHAL_ASSERT_EQ(whal_SetBits(msk, pos, 0xA), 0xAul); } static void test_setbits_shifted(void) { - size_t mask = WHAL_MASK_RANGE(7, 4); - WHAL_ASSERT_EQ(whal_SetBits(mask, 0x5), 0x50ul); + size_t msk = (WHAL_BITMASK(4) << 4); + size_t pos = 4; + WHAL_ASSERT_EQ(whal_SetBits(msk, pos, 0x5), 0x50ul); } static void test_getbits_low(void) { - size_t mask = WHAL_MASK_RANGE(3, 0); - WHAL_ASSERT_EQ(whal_GetBits(mask, 0xABul), 0xBul); + size_t msk = WHAL_BITMASK(4); + size_t pos = 0; + WHAL_ASSERT_EQ(whal_GetBits(msk, pos, 0xABul), 0xBul); } static void test_getbits_shifted(void) { - size_t mask = WHAL_MASK_RANGE(7, 4); - WHAL_ASSERT_EQ(whal_GetBits(mask, 0xABul), 0xAul); + size_t msk = (WHAL_BITMASK(4) << 4); + size_t pos = 4; + WHAL_ASSERT_EQ(whal_GetBits(msk, pos, 0xABul), 0xAul); } static void test_setbits_getbits_roundtrip(void) { - size_t mask = WHAL_MASK_RANGE(14, 8); + size_t msk = (WHAL_BITMASK(7) << 8); + size_t pos = 8; size_t val = 42; - size_t encoded = whal_SetBits(mask, val); - WHAL_ASSERT_EQ(whal_GetBits(mask, encoded), val); + size_t encoded = whal_SetBits(msk, pos, val); + WHAL_ASSERT_EQ(whal_GetBits(msk, pos, encoded), val); } static void test_setbits_single_bit(void) { - size_t mask = WHAL_MASK(24); - WHAL_ASSERT_EQ(whal_SetBits(mask, 1), (1ul << 24)); - WHAL_ASSERT_EQ(whal_SetBits(mask, 0), 0ul); + size_t msk = (1UL << 24); + size_t pos = 24; + WHAL_ASSERT_EQ(whal_SetBits(msk, pos, 1), (1UL << 24)); + WHAL_ASSERT_EQ(whal_SetBits(msk, pos, 0), 0ul); } void test_bitops(void) { WHAL_TEST_SUITE_START("bitops"); - WHAL_TEST(test_mask_bit0); - WHAL_TEST(test_mask_bit15); - WHAL_TEST(test_mask_bit31); - WHAL_TEST(test_mask_range_single_bit); - WHAL_TEST(test_mask_range_multi_bit); - WHAL_TEST(test_mask_range_full_byte); + WHAL_TEST(test_bitmask_4); + WHAL_TEST(test_bitmask_8); + WHAL_TEST(test_bitmask_1); WHAL_TEST(test_setbits_low); WHAL_TEST(test_setbits_shifted); WHAL_TEST(test_getbits_low); diff --git a/tests/stm32wb/test_clock.c b/tests/stm32wb/test_clock.c index bce9f9b..d7ded55 100644 --- a/tests/stm32wb/test_clock.c +++ b/tests/stm32wb/test_clock.c @@ -19,12 +19,12 @@ static void test_clock_enable_disable(void) /* Readback: GPIOA enable bit should be set in AHB2ENR (offset 0x4C, bit 0) */ size_t val = 0; - whal_Reg_Get(g_whalClock.regmap.base, 0x4C, (1 << 0), &val); + whal_Reg_Get(g_whalClock.regmap.base, 0x4C, (1 << 0), 0, &val); WHAL_ASSERT_EQ(val, 1); WHAL_ASSERT_EQ(whal_Clock_Disable(&g_whalClock, &testClk), WHAL_SUCCESS); - whal_Reg_Get(g_whalClock.regmap.base, 0x4C, (1 << 0), &val); + whal_Reg_Get(g_whalClock.regmap.base, 0x4C, (1 << 0), 0, &val); WHAL_ASSERT_EQ(val, 0); } diff --git a/tests/stm32wb/test_flash.c b/tests/stm32wb/test_flash.c index e283337..588063c 100644 --- a/tests/stm32wb/test_flash.c +++ b/tests/stm32wb/test_flash.c @@ -7,7 +7,8 @@ /* Flash CR register offset and LOCK bit */ #define FLASH_CR_REG 0x14 -#define FLASH_CR_LOCK WHAL_MASK(31) +#define FLASH_CR_LOCK_Pos 31 +#define FLASH_CR_LOCK_Msk (1UL << FLASH_CR_LOCK_Pos) /* Test address in the data flash area (OTP/data, not code flash) */ #define TEST_FLASH_ADDR 0x08080000 @@ -45,7 +46,7 @@ static void test_flash_lock_readback(void) WHAL_ASSERT_EQ(whal_Flash_Lock(&g_whalFlash, 0, 0), WHAL_SUCCESS); size_t val = 0; - whal_Reg_Get(g_whalFlash.regmap.base, FLASH_CR_REG, FLASH_CR_LOCK, &val); + whal_Reg_Get(g_whalFlash.regmap.base, FLASH_CR_REG, FLASH_CR_LOCK_Msk, FLASH_CR_LOCK_Pos, &val); WHAL_ASSERT_EQ(val, 1); } diff --git a/tests/stm32wb/test_gpio.c b/tests/stm32wb/test_gpio.c index cd0e224..f98c43c 100644 --- a/tests/stm32wb/test_gpio.c +++ b/tests/stm32wb/test_gpio.c @@ -16,10 +16,10 @@ static void test_gpio_mode_register(void) { /* PB5 should be configured as output (mode = 0x01) in bits [11:10] */ size_t portBase = g_whalGpio.regmap.base + GPIOB_BASE_OFFSET; - size_t mask = WHAL_MASK_RANGE(11, 10); + size_t mask = (WHAL_BITMASK(2) << 10); size_t val = 0; - whal_Reg_Get(portBase, GPIOx_MODE_REG, mask, &val); + whal_Reg_Get(portBase, GPIOx_MODE_REG, mask, 10, &val); WHAL_ASSERT_EQ(val, WHAL_STM32WB_GPIO_MODE_OUT); } @@ -30,7 +30,7 @@ static void test_gpio_set_high(void) /* Readback ODR bit 5 */ size_t portBase = g_whalGpio.regmap.base + GPIOB_BASE_OFFSET; size_t val = 0; - whal_Reg_Get(portBase, GPIOx_ODR_REG, WHAL_MASK(5), &val); + whal_Reg_Get(portBase, GPIOx_ODR_REG, (1UL << 5), 5, &val); WHAL_ASSERT_EQ(val, 1); } @@ -40,7 +40,7 @@ static void test_gpio_set_low(void) size_t portBase = g_whalGpio.regmap.base + GPIOB_BASE_OFFSET; size_t val = 0; - whal_Reg_Get(portBase, GPIOx_ODR_REG, WHAL_MASK(5), &val); + whal_Reg_Get(portBase, GPIOx_ODR_REG, (1UL << 5), 5, &val); WHAL_ASSERT_EQ(val, 0); } diff --git a/wolfHAL/bitops.h b/wolfHAL/bitops.h index 40d835e..240d31e 100644 --- a/wolfHAL/bitops.h +++ b/wolfHAL/bitops.h @@ -8,41 +8,24 @@ #include -#if defined(__GNUC__) -/* Count trailing zeros in a mask. */ -#define whal_CountTrailingZeros(mask) __builtin_ctz(mask) -#else -static size_t whal_CountTrailingZeros(mask) -{ - size_t cnt = 0; - while ((mask & 1ul) == 0ul) { - mask >>= 1; - n++; - } - - return n; -} -#endif - /* - * @brief Encode a value into a bit field described by @p mask. + * @brief Create a bitmask of @p width bits starting at bit 0. + * + * Example: WHAL_BITMASK(4) = 0xF */ -#define whal_SetBits(mask, value) \ - (((value) << whal_CountTrailingZeros(mask)) & (mask)) +#define WHAL_BITMASK(width) \ + ((1UL << (width)) - 1) /* - * @brief Extract a bit field value from a register using @p mask. + * @brief Encode a value into a bit field described by @p msk and @p pos. */ -#define whal_GetBits(mask, reg) \ - (((reg) & (mask)) >> whal_CountTrailingZeros(mask)) - -/* Create a single-bit mask for bit @p bit. */ -#define WHAL_MASK(bit) \ - (1ul << bit) +#define whal_SetBits(msk, pos, val) \ + (((val) << (pos)) & (msk)) -/* Create a mask covering bits @p high_bit down to @p low_bit (inclusive). */ -#define WHAL_MASK_RANGE(high_bit, low_bit) \ - ((~0UL >> ((sizeof(uintptr_t) * 8) - 1 - (high_bit))) & \ - (~0UL << (low_bit))) +/* + * @brief Extract a bit field value from a register using @p msk and @p pos. + */ +#define whal_GetBits(msk, pos, reg) \ + (((reg) & (msk)) >> (pos)) #endif /* WHAL_BITOPS_H */ diff --git a/wolfHAL/clock/pic32cz_clock.h b/wolfHAL/clock/pic32cz_clock.h index a04fcd2..2c0efbd 100644 --- a/wolfHAL/clock/pic32cz_clock.h +++ b/wolfHAL/clock/pic32cz_clock.h @@ -79,16 +79,30 @@ typedef enum whal_Pic32czClock_GenSrc { } whal_Pic32czClock_GenSrc; /* PLL output post-divider masks for PLLxPOSTDIVA register */ -#define WHAL_PIC32CZ_POSTDIVMASK0 WHAL_MASK_RANGE(5, 0) /* POSTDIV0[5:0] */ -#define WHAL_PIC32CZ_POSTDIVMASK1 WHAL_MASK_RANGE(13, 8) /* POSTDIV1[5:0] */ -#define WHAL_PIC32CZ_POSTDIVMASK2 WHAL_MASK_RANGE(21, 16) /* POSTDIV2[5:0] */ -#define WHAL_PIC32CZ_POSTDIVMASK3 WHAL_MASK_RANGE(29, 24) /* POSTDIV3[5:0] */ +#define WHAL_PIC32CZ_POSTDIV0_Pos (0) /* POSTDIV0[5:0] */ +#define WHAL_PIC32CZ_POSTDIV0_Msk (WHAL_BITMASK(6) << 0) + +#define WHAL_PIC32CZ_POSTDIV1_Pos (8) /* POSTDIV1[5:0] */ +#define WHAL_PIC32CZ_POSTDIV1_Msk (WHAL_BITMASK(6) << 8) + +#define WHAL_PIC32CZ_POSTDIV2_Pos (16) /* POSTDIV2[5:0] */ +#define WHAL_PIC32CZ_POSTDIV2_Msk (WHAL_BITMASK(6) << 16) + +#define WHAL_PIC32CZ_POSTDIV3_Pos (24) /* POSTDIV3[5:0] */ +#define WHAL_PIC32CZ_POSTDIV3_Msk (WHAL_BITMASK(6) << 24) /* PLL output enable masks for PLLxPOSTDIVA register */ -#define WHAL_PIC32CZ_OUTENMASK0 WHAL_MASK(7) /* OUTEN0 */ -#define WHAL_PIC32CZ_OUTENMASK1 WHAL_MASK(15) /* OUTEN1 */ -#define WHAL_PIC32CZ_OUTENMASK2 WHAL_MASK(23) /* OUTEN2 */ -#define WHAL_PIC32CZ_OUTENMASK3 WHAL_MASK(31) /* OUTEN3 */ +#define WHAL_PIC32CZ_OUTEN0_Pos (7) /* OUTEN0 */ +#define WHAL_PIC32CZ_OUTEN0_Msk (1UL << 7) + +#define WHAL_PIC32CZ_OUTEN1_Pos (15) /* OUTEN1 */ +#define WHAL_PIC32CZ_OUTEN1_Msk (1UL << 15) + +#define WHAL_PIC32CZ_OUTEN2_Pos (23) /* OUTEN2 */ +#define WHAL_PIC32CZ_OUTEN2_Msk (1UL << 23) + +#define WHAL_PIC32CZ_OUTEN3_Pos (31) /* OUTEN3 */ +#define WHAL_PIC32CZ_OUTEN3_Msk (1UL << 31) /* * @brief PLL output configuration. @@ -97,8 +111,10 @@ typedef enum whal_Pic32czClock_GenSrc { * Output frequency = VCO frequency / postDiv */ typedef struct whal_Pic32czClockPll_OutCfg { - size_t postDivMask; /* Use WHAL_PIC32CZ_POSTDIVMASKx */ - size_t outEnMask; /* Use WHAL_PIC32CZ_OUTENMASKx */ + size_t postDivMask; /* Use WHAL_PIC32CZ_POSTDIVx_Msk */ + size_t postDivPos; /* Use WHAL_PIC32CZ_POSTDIVx_Pos */ + size_t outEnMask; /* Use WHAL_PIC32CZ_OUTENx_Msk */ + size_t outEnPos; /* Use WHAL_PIC32CZ_OUTENx_Pos */ uint8_t postDiv; /* Post-divider value (1-63) */ } whal_Pic32czClockPll_OutCfg; @@ -190,6 +206,7 @@ typedef struct whal_Pic32czClock_Clk { uint8_t gclkPeriphSrc; /* GCLK generator to use as source */ size_t mclkEnableInst; /* MCLK mask register instance */ size_t mclkEnableMask; /* Bit mask within the MCLK mask register */ + size_t mclkEnablePos; /* Bit position within the MCLK mask register */ } whal_Pic32czClock_Clk; /* diff --git a/wolfHAL/clock/stm32wb_rcc.h b/wolfHAL/clock/stm32wb_rcc.h index 73893ff..8badbec 100644 --- a/wolfHAL/clock/stm32wb_rcc.h +++ b/wolfHAL/clock/stm32wb_rcc.h @@ -109,11 +109,12 @@ typedef struct whal_Stm32wbRcc_MsiClkCfg { * a peripheral's bus clock. Used with whal_Stm32wbRcc_Enable/Disable. * * Example for GPIOA: - * { .regOffset = 0x04C, .enableMask = (1 << 0) } // AHB2ENR.GPIOAEN + * { .regOffset = 0x04C, .enableMask = (1 << 0), .enablePos = 0 } // AHB2ENR.GPIOAEN */ typedef struct whal_Stm32wbRcc_Clk { size_t regOffset; /* Offset from RCC base to enable register */ size_t enableMask; /* Bit mask for the peripheral enable bit */ + size_t enablePos; /* Bit position for the peripheral enable bit */ } whal_Stm32wbRcc_Clk; /* diff --git a/wolfHAL/platform/microchip/pic32cz.h b/wolfHAL/platform/microchip/pic32cz.h index e31bb3f..6cac3eb 100644 --- a/wolfHAL/platform/microchip/pic32cz.h +++ b/wolfHAL/platform/microchip/pic32cz.h @@ -44,6 +44,7 @@ .driver = &whal_Pic32czUart_Driver #define WHAL_PIC32CZ_SUPPLY_PLL \ - .enableMask = (1 << 18) + .enableMask = (1UL << 18), \ + .enablePos = 18 #endif /* WHAL_PIC32CZ_H */ diff --git a/wolfHAL/platform/st/stm32wb55xx.h b/wolfHAL/platform/st/stm32wb55xx.h index ebc44bc..c75bf89 100644 --- a/wolfHAL/platform/st/stm32wb55xx.h +++ b/wolfHAL/platform/st/stm32wb55xx.h @@ -74,34 +74,42 @@ #define WHAL_STM32WB55_PLL_CLOCK \ .regOffset = 0x00, \ - .enableMask = (1 << 24) + .enableMask = (1UL << 24), \ + .enablePos = 24 #define WHAL_STM32WB55_GPIOA_CLOCK \ .regOffset = 0x4C, \ - .enableMask = (1 << 0) + .enableMask = (1UL << 0), \ + .enablePos = 0 #define WHAL_STM32WB55_GPIOB_CLOCK \ .regOffset = 0x4C, \ - .enableMask = (1 << 1) + .enableMask = (1UL << 1), \ + .enablePos = 1 #define WHAL_STM32WB55_RNG_CLOCK \ .regOffset = 0x50, \ - .enableMask = (1 << 18) + .enableMask = (1UL << 18), \ + .enablePos = 18 #define WHAL_STM32WB55_FLASH_CLOCK \ .regOffset = 0x50, \ - .enableMask = (1 << 25) + .enableMask = (1UL << 25), \ + .enablePos = 25 #define WHAL_STM32WB55_LPUART1_CLOCK \ .regOffset = 0x5C, \ - .enableMask = (1 << 0) + .enableMask = (1UL << 0), \ + .enablePos = 0 #define WHAL_STM32WB55_UART1_CLOCK \ .regOffset = 0x60, \ - .enableMask = (1 << 14) + .enableMask = (1UL << 14), \ + .enablePos = 14 #define WHAL_STM32WB55_SPI1_CLOCK \ .regOffset = 0x60, \ - .enableMask = (1 << 12) + .enableMask = (1UL << 12), \ + .enablePos = 12 #endif /* WHAL_STM32WB55XX_H */ diff --git a/wolfHAL/regmap.h b/wolfHAL/regmap.h index 21960f4..0e9d370 100644 --- a/wolfHAL/regmap.h +++ b/wolfHAL/regmap.h @@ -36,11 +36,12 @@ void whal_Reg_Update(size_t base, size_t offset, size_t mask, size_t value); * * @param base Base address of the register block. * @param offset Byte offset from @p base to the register. - * @param mask Bit mask selecting the field to extract. + * @param msk Bit mask selecting the field to extract. + * @param pos Bit position of the field's LSB. * @param value Output storage for the decoded field. * * @note No return value. Callers are responsible for passing valid inputs. */ -void whal_Reg_Get(size_t base, size_t offset, size_t mask, size_t *value); +void whal_Reg_Get(size_t base, size_t offset, size_t msk, size_t pos, size_t *value); #endif /* WHAL_REGMAP_H */ diff --git a/wolfHAL/supply/pic32cz_supc.h b/wolfHAL/supply/pic32cz_supc.h index 0f0d73b..b5053e2 100644 --- a/wolfHAL/supply/pic32cz_supc.h +++ b/wolfHAL/supply/pic32cz_supc.h @@ -17,6 +17,7 @@ typedef struct whal_Pic32czSupc_Cfg { typedef struct whal_Pic32czSupc_Supply { size_t enableMask; + size_t enablePos; } whal_Pic32czSupc_Supply; /*