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math: Remove WANT_SIMD_EXCEPT
Removes the WANT_SIMD_EXCEPT feature from AOR, and cleaned up AdvSIMD files.
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175 files changed

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‎config.mk.dist‎

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -136,10 +136,6 @@ else
136136
endif
137137
math-cflags += -DWANT_SVE_TESTS=$(WANT_SVE_TESTS)
138138

139-
# If set to 1, set fenv in vector math routines.
140-
WANT_SIMD_EXCEPT ?= 0
141-
math-cflags += -DWANT_SIMD_EXCEPT=$(WANT_SIMD_EXCEPT)
142-
143139
# If set to 1, enable tests for exp10.
144140
WANT_EXP10_TESTS ?= 1
145141
math-cflags += -DWANT_EXP10_TESTS=$(WANT_EXP10_TESTS)

‎math/Dir.mk‎

Lines changed: 2 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -6,9 +6,6 @@
66
.SECONDEXPANSION:
77

88
ifneq ($(OS),Linux)
9-
ifeq ($(WANT_SIMD_EXCEPT),1)
10-
$(error WANT_SIMD_EXCEPT is not supported outside Linux)
11-
endif
129
ifneq ($(USE_MPFR),1)
1310
$(warning WARNING: Double-precision ULP tests will not be usable without MPFR)
1411
endif
@@ -225,9 +222,6 @@ $(ulp-input-dir)/%.ulp_nn: $(ulp-input-dir)/%.ulp_nn.i
225222
$(ulp-input-dir)/%.fenv.i: $(math-src-dir)/%.c | $$(@D)
226223
$(CC) $(CFLAGS) $< -E -o $@
227224

228-
$(ulp-input-dir)/%.fenv: $(ulp-input-dir)/%.fenv.i
229-
{ grep "TEST_DISABLE_FENV " $< || true; } > $@
230-
231225
$(ulp-input-dir)/%.itv.i: $(math-src-dir)/%.c | $$(@D)
232226
$(CC) $(CFLAGS) $< -E -o $@
233227

@@ -246,8 +240,6 @@ $(ulp-lims): $(math-lib-lims)
246240
ulp-lims-nn = $(ulp-input-dir)/limits_nn
247241
$(ulp-lims-nn): $(math-lib-lims-nn)
248242

249-
fenv-exps := $(ulp-input-dir)/fenv
250-
$(fenv-exps): $(math-lib-fenvs)
251243

252244
generic-itvs = $(ulp-input-dir)/itvs
253245
$(generic-itvs): $(filter-out $(ulp-input-dir)/$(ARCH)/%,$(math-lib-itvs))
@@ -259,18 +251,17 @@ ulp-cvals := $(ulp-input-dir)/cvals
259251
$(ulp-cvals): $(math-lib-cvals)
260252

261253
# Remove first word, which will be TEST directive
262-
$(ulp-lims) $(ulp-lims-nn) $(fenv-exps) $(arch-itvs) $(generic-itvs) $(ulp-cvals): | $$(@D)
254+
$(ulp-lims) $(ulp-lims-nn) $(arch-itvs) $(generic-itvs) $(ulp-cvals): | $$(@D)
263255
sed "s/TEST_[^ ]* //g" $^ | sort -u > $@
264256

265257
check-math-ulp: $(ulp-lims) $(ulp-lims-nn)
266-
check-math-ulp: $(fenv-exps) $(ulp-cvals)
258+
check-math-ulp: $(ulp-cvals)
267259
check-math-ulp: $(generic-itvs) $(arch-itvs)
268260
check-math-ulp: $(math-tools)
269261
ULPFLAGS="$(math-ulpflags)" \
270262
LIMITS=../../$(ulp-lims) \
271263
ARCH_ITVS=../../$(arch-itvs) \
272264
GEN_ITVS=../../$(generic-itvs) \
273-
DISABLE_FENV=../../$(fenv-exps) \
274265
CVALS=../../$(ulp-cvals) \
275266
FUNC=$(func) \
276267
WANT_EXPERIMENTAL_MATH=$(WANT_EXPERIMENTAL_MATH) \

‎math/aarch64/advsimd/acos.c‎

Lines changed: 3 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -28,26 +28,9 @@ static const struct data
2828
.abs_mask = V2 (0x7fffffffffffffff),
2929
};
3030

31-
#define AllMask v_u64 (0xffffffffffffffff)
32-
#define Oneu 0x3ff0000000000000
33-
#define Small 0x3e50000000000000 /* 2^-53. */
34-
35-
#if WANT_SIMD_EXCEPT
36-
static float64x2_t VPCS_ATTR NOINLINE
37-
special_case (float64x2_t x, float64x2_t y, uint64x2_t special)
38-
{
39-
return v_call_f64 (acos, x, y, special);
40-
}
41-
#endif
42-
4331
/* Double-precision implementation of vector acos(x).
4432
45-
For |x| < Small, approximate acos(x) by pi/2 - x. Small = 2^-53 for correct
46-
rounding.
47-
If WANT_SIMD_EXCEPT = 0, Small = 0 and we proceed with the following
48-
approximation.
49-
50-
For |x| in [Small, 0.5], use an order 11 polynomial P such that the final
33+
For |x| in [0, 0.5], use an order 11 polynomial P such that the final
5134
approximation of asin is an odd polynomial:
5235
5336
acos(x) ~ pi/2 - (x + x^3 P(x^2)).
@@ -68,16 +51,6 @@ float64x2_t VPCS_ATTR V_NAME_D1 (acos) (float64x2_t x)
6851
const struct data *d = ptr_barrier (&data);
6952

7053
float64x2_t ax = vabsq_f64 (x);
71-
72-
#if WANT_SIMD_EXCEPT
73-
/* A single comparison for One, Small and QNaN. */
74-
uint64x2_t special
75-
= vcgtq_u64 (vsubq_u64 (vreinterpretq_u64_f64 (ax), v_u64 (Small)),
76-
v_u64 (Oneu - Small));
77-
if (unlikely (v_any_u64 (special)))
78-
return special_case (x, x, AllMask);
79-
#endif
80-
8154
uint64x2_t a_le_half = vcleq_f64 (ax, v_f64 (0.5));
8255

8356
/* Evaluate polynomial Q(x) = z + z * z2 * P(z2) with
@@ -130,9 +103,8 @@ float64x2_t VPCS_ATTR V_NAME_D1 (acos) (float64x2_t x)
130103

131104
TEST_SIG (V, D, 1, acos, -1.0, 1.0)
132105
TEST_ULP (V_NAME_D1 (acos), 1.00)
133-
TEST_DISABLE_FENV_IF_NOT (V_NAME_D1 (acos), WANT_SIMD_EXCEPT)
134-
TEST_INTERVAL (V_NAME_D1 (acos), 0, Small, 5000)
135-
TEST_INTERVAL (V_NAME_D1 (acos), Small, 0.5, 50000)
106+
TEST_INTERVAL (V_NAME_D1 (acos), 0, 0x1p-53, 5000)
107+
TEST_INTERVAL (V_NAME_D1 (acos), 0x1p-53, 0.5, 50000)
136108
TEST_INTERVAL (V_NAME_D1 (acos), 0.5, 1.0, 50000)
137109
TEST_INTERVAL (V_NAME_D1 (acos), 1.0, 0x1p11, 50000)
138110
TEST_INTERVAL (V_NAME_D1 (acos), 0x1p11, inf, 20000)

‎math/aarch64/advsimd/acosf.c‎

Lines changed: 2 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
/*
22
* Single-precision vector acos(x) function.
33
*
4-
* Copyright (c) 2023-2024, Arm Limited.
4+
* Copyright (c) 2023-2025, Arm Limited.
55
* SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception
66
*/
77

@@ -25,25 +25,10 @@ static const struct data
2525

2626
#define AbsMask 0x7fffffff
2727
#define Half 0x3f000000
28-
#define One 0x3f800000
29-
#define Small 0x32800000 /* 2^-26. */
30-
31-
#if WANT_SIMD_EXCEPT
32-
static float32x4_t VPCS_ATTR NOINLINE
33-
special_case (float32x4_t x, float32x4_t y, uint32x4_t special)
34-
{
35-
return v_call_f32 (acosf, x, y, special);
36-
}
37-
#endif
3828

3929
/* Single-precision implementation of vector acos(x).
4030
41-
For |x| < Small, approximate acos(x) by pi/2 - x. Small = 2^-26 for correct
42-
rounding.
43-
If WANT_SIMD_EXCEPT = 0, Small = 0 and we proceed with the following
44-
approximation.
45-
46-
For |x| in [Small, 0.5], use order 4 polynomial P such that the final
31+
For |x| in [0, 0.5], use order 4 polynomial P such that the final
4732
approximation of asin is an odd polynomial:
4833
4934
acos(x) ~ pi/2 - (x + x^3 P(x^2)).
@@ -65,14 +50,6 @@ float32x4_t VPCS_ATTR NOINLINE V_NAME_F1 (acos) (float32x4_t x)
6550
uint32x4_t ix = vreinterpretq_u32_f32 (x);
6651
uint32x4_t ia = vandq_u32 (ix, v_u32 (AbsMask));
6752

68-
#if WANT_SIMD_EXCEPT
69-
/* A single comparison for One, Small and QNaN. */
70-
uint32x4_t special
71-
= vcgtq_u32 (vsubq_u32 (ia, v_u32 (Small)), v_u32 (One - Small));
72-
if (unlikely (v_any_u32 (special)))
73-
return special_case (x, x, v_u32 (0xffffffff));
74-
#endif
75-
7653
float32x4_t ax = vreinterpretq_f32_u32 (ia);
7754
uint32x4_t a_le_half = vcleq_u32 (ia, v_u32 (Half));
7855

@@ -106,7 +83,6 @@ HALF_WIDTH_ALIAS_F1 (acos)
10683

10784
TEST_SIG (V, F, 1, acos, -1.0, 1.0)
10885
TEST_ULP (V_NAME_F1 (acos), 0.82)
109-
TEST_DISABLE_FENV_IF_NOT (V_NAME_F1 (acos), WANT_SIMD_EXCEPT)
11086
TEST_INTERVAL (V_NAME_F1 (acos), 0, 0x1p-26, 5000)
11187
TEST_INTERVAL (V_NAME_F1 (acos), 0x1p-26, 0.5, 50000)
11288
TEST_INTERVAL (V_NAME_F1 (acos), 0.5, 1.0, 50000)

‎math/aarch64/advsimd/acosh.c‎

Lines changed: 2 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
/*
22
* Double-precision vector acosh(x) function.
3-
* Copyright (c) 2023-2024, Arm Limited.
3+
* Copyright (c) 2023-2025, Arm Limited.
44
* SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception
55
*/
66

@@ -38,12 +38,6 @@ VPCS_ATTR float64x2_t V_NAME_D1 (acosh) (float64x2_t x)
3838
const struct data *d = ptr_barrier (&data);
3939
uint64x2_t special
4040
= vcgeq_u64 (vsubq_u64 (vreinterpretq_u64_f64 (x), d->one), d->thresh);
41-
float64x2_t special_arg = x;
42-
43-
#if WANT_SIMD_EXCEPT
44-
if (unlikely (v_any_u64 (special)))
45-
x = vbslq_f64 (special, vreinterpretq_f64_u64 (d->one), x);
46-
#endif
4741

4842
float64x2_t xm1 = vsubq_f64 (x, v_f64 (1.0));
4943
float64x2_t y = vaddq_f64 (x, v_f64 (1.0));
@@ -52,13 +46,12 @@ VPCS_ATTR float64x2_t V_NAME_D1 (acosh) (float64x2_t x)
5246
y = vaddq_f64 (xm1, y);
5347

5448
if (unlikely (v_any_u64 (special)))
55-
return special_case (special_arg, y, special, &d->log1p_consts);
49+
return special_case (x, y, special, &d->log1p_consts);
5650
return log1p_inline (y, &d->log1p_consts);
5751
}
5852

5953
TEST_SIG (V, D, 1, acosh, 1.0, 10.0)
6054
TEST_ULP (V_NAME_D1 (acosh), 2.53)
61-
TEST_DISABLE_FENV_IF_NOT (V_NAME_D1 (acosh), WANT_SIMD_EXCEPT)
6255
TEST_INTERVAL (V_NAME_D1 (acosh), 1, 0x1p511, 90000)
6356
TEST_INTERVAL (V_NAME_D1 (acosh), 0x1p511, inf, 10000)
6457
TEST_INTERVAL (V_NAME_D1 (acosh), 0, 1, 1000)

‎math/aarch64/advsimd/acoshf.c‎

Lines changed: 3 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
/*
22
* Single-precision vector acosh(x) function.
3-
* Copyright (c) 2023-2024, Arm Limited.
3+
* Copyright (c) 2023-2025, Arm Limited.
44
* SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception
55
*/
66

@@ -26,13 +26,8 @@ special_case (float32x4_t x, float32x4_t y, uint16x4_t special,
2626
return v_call_f32 (acoshf, x, log1pf_inline (y, d), vmovl_u16 (special));
2727
}
2828

29-
/* Vector approximation for single-precision acosh, based on log1p. Maximum
30-
error depends on WANT_SIMD_EXCEPT. With SIMD fp exceptions enabled, it
31-
is 3.00 ULP:
32-
_ZGVnN4v_acoshf(0x1.01df3ap+0) got 0x1.ef0a82p-4
33-
want 0x1.ef0a7cp-4.
34-
With exceptions disabled, we can compute u with a shorter dependency chain,
35-
which gives maximum error of 3.22 ULP:
29+
/* Vector approximation for single-precision acosh, based on log1p.
30+
The largest observed error is 3.22 ULP:
3631
_ZGVnN4v_acoshf(0x1.007ef2p+0) got 0x1.fdcdccp-5
3732
want 0x1.fdcdd2p-5. */
3833

@@ -42,19 +37,9 @@ float32x4_t VPCS_ATTR NOINLINE V_NAME_F1 (acosh) (float32x4_t x)
4237
uint32x4_t ix = vreinterpretq_u32_f32 (x);
4338
uint16x4_t special = vcge_u16 (vsubhn_u32 (ix, d->one), Thresh);
4439

45-
#if WANT_SIMD_EXCEPT
46-
/* Mask special lanes with 1 to side-step spurious invalid or overflow. Use
47-
only xm1 to calculate u, as operating on x will trigger invalid for NaN.
48-
Widening sign-extend special predicate in order to mask with it. */
49-
uint32x4_t p
50-
= vreinterpretq_u32_s32 (vmovl_s16 (vreinterpret_s16_u16 (special)));
51-
float32x4_t xm1 = v_zerofy_f32 (vsubq_f32 (x, v_f32 (1)), p);
52-
float32x4_t u = vfmaq_f32 (vaddq_f32 (xm1, xm1), xm1, xm1);
53-
#else
5440
float32x4_t xm1 = vsubq_f32 (x, vreinterpretq_f32_u32 (d->one));
5541
float32x4_t u
5642
= vmulq_f32 (xm1, vaddq_f32 (x, vreinterpretq_f32_u32 (d->one)));
57-
#endif
5843

5944
float32x4_t y = vaddq_f32 (xm1, vsqrtq_f32 (u));
6045

@@ -66,12 +51,7 @@ float32x4_t VPCS_ATTR NOINLINE V_NAME_F1 (acosh) (float32x4_t x)
6651
HALF_WIDTH_ALIAS_F1 (acosh)
6752

6853
TEST_SIG (V, F, 1, acosh, 1.0, 10.0)
69-
#if WANT_SIMD_EXCEPT
70-
TEST_ULP (V_NAME_F1 (acosh), 2.50)
71-
#else
7254
TEST_ULP (V_NAME_F1 (acosh), 2.78)
73-
#endif
74-
TEST_DISABLE_FENV_IF_NOT (V_NAME_F1 (acosh), WANT_SIMD_EXCEPT)
7555
TEST_INTERVAL (V_NAME_F1 (acosh), 0, 1, 500)
7656
TEST_INTERVAL (V_NAME_F1 (acosh), 1, SquareLim, 100000)
7757
TEST_INTERVAL (V_NAME_F1 (acosh), SquareLim, inf, 1000)

‎math/aarch64/advsimd/acospi.c‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -108,7 +108,6 @@ float64x2_t VPCS_ATTR NOINLINE V_NAME_D1 (acospi) (float64x2_t x)
108108

109109
#if WANT_C23_TESTS
110110
TEST_ULP (V_NAME_D1 (acospi), 2.05)
111-
TEST_DISABLE_FENV (V_NAME_D1 (acospi))
112111
TEST_SYM_INTERVAL (V_NAME_D1 (acospi), 0, 0x1p-31, 5000)
113112
TEST_SYM_INTERVAL (V_NAME_D1 (acospi), 0x1p-31, 0.5, 10000)
114113
TEST_SYM_INTERVAL (V_NAME_D1 (acospi), 0.5, 0x1p32f, 10000)

‎math/aarch64/advsimd/acospif.c‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -96,7 +96,6 @@ HALF_WIDTH_ALIAS_F1 (acospi)
9696

9797
#if WANT_C23_TESTS
9898
TEST_ULP (V_NAME_F1 (acospi), 2.03)
99-
TEST_DISABLE_FENV (V_NAME_F1 (acospi))
10099
TEST_SYM_INTERVAL (V_NAME_F1 (acospi), 0, 0x1p-31, 5000)
101100
TEST_SYM_INTERVAL (V_NAME_F1 (acospi), 0x1p-31, 0.5, 10000)
102101
TEST_SYM_INTERVAL (V_NAME_F1 (acospi), 0.5, 0x1p32f, 10000)

‎math/aarch64/advsimd/asin.c‎

Lines changed: 4 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
/*
22
* Double-precision vector asin(x) function.
33
*
4-
* Copyright (c) 2023-2024, Arm Limited.
4+
* Copyright (c) 2023-2025, Arm Limited.
55
* SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception
66
*/
77

@@ -27,25 +27,8 @@ static const struct data
2727
.pi_over_2 = V2 (0x1.921fb54442d18p+0), .abs_mask = V2 (0x7fffffffffffffff),
2828
};
2929

30-
#define AllMask v_u64 (0xffffffffffffffff)
31-
#define One 0x3ff0000000000000
32-
#define Small 0x3e50000000000000 /* 2^-12. */
33-
34-
#if WANT_SIMD_EXCEPT
35-
static float64x2_t VPCS_ATTR NOINLINE
36-
special_case (float64x2_t x, float64x2_t y, uint64x2_t special)
37-
{
38-
return v_call_f64 (asin, x, y, special);
39-
}
40-
#endif
41-
4230
/* Double-precision implementation of vector asin(x).
43-
44-
For |x| < Small, approximate asin(x) by x. Small = 2^-12 for correct
45-
rounding. If WANT_SIMD_EXCEPT = 0, Small = 0 and we proceed with the
46-
following approximation.
47-
48-
For |x| in [Small, 0.5], use an order 11 polynomial P such that the final
31+
For |x| in [0, 0.5], use an order 11 polynomial P such that the final
4932
approximation is an odd polynomial: asin(x) ~ x + x^3 P(x^2).
5033
5134
The largest observed error in this region is 1.01 ulps,
@@ -64,16 +47,6 @@ float64x2_t VPCS_ATTR V_NAME_D1 (asin) (float64x2_t x)
6447
const struct data *d = ptr_barrier (&data);
6548
float64x2_t ax = vabsq_f64 (x);
6649

67-
#if WANT_SIMD_EXCEPT
68-
/* Special values need to be computed with scalar fallbacks so
69-
that appropriate exceptions are raised. */
70-
uint64x2_t special
71-
= vcgtq_u64 (vsubq_u64 (vreinterpretq_u64_f64 (ax), v_u64 (Small)),
72-
v_u64 (One - Small));
73-
if (unlikely (v_any_u64 (special)))
74-
return special_case (x, x, AllMask);
75-
#endif
76-
7750
uint64x2_t a_lt_half = vcaltq_f64 (x, v_f64 (0.5));
7851

7952
/* Evaluate polynomial Q(x) = y + y * z * P(z) with
@@ -121,9 +94,8 @@ float64x2_t VPCS_ATTR V_NAME_D1 (asin) (float64x2_t x)
12194

12295
TEST_SIG (V, D, 1, asin, -1.0, 1.0)
12396
TEST_ULP (V_NAME_D1 (asin), 2.20)
124-
TEST_DISABLE_FENV_IF_NOT (V_NAME_D1 (asin), WANT_SIMD_EXCEPT)
125-
TEST_INTERVAL (V_NAME_D1 (asin), 0, Small, 5000)
126-
TEST_INTERVAL (V_NAME_D1 (asin), Small, 0.5, 50000)
97+
TEST_INTERVAL (V_NAME_D1 (asin), 0, 0x1p-12, 5000)
98+
TEST_INTERVAL (V_NAME_D1 (asin), 0x1p-12, 0.5, 50000)
12799
TEST_INTERVAL (V_NAME_D1 (asin), 0.5, 1.0, 50000)
128100
TEST_INTERVAL (V_NAME_D1 (asin), 1.0, 0x1p11, 50000)
129101
TEST_INTERVAL (V_NAME_D1 (asin), 0x1p11, inf, 20000)

‎math/aarch64/advsimd/asinf.c‎

Lines changed: 1 addition & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -23,21 +23,10 @@ static const struct data
2323
};
2424

2525
#define AbsMask 0x7fffffff
26-
#define One 0x3f800000
27-
#define Small 0x39800000 /* 2^-12. */
28-
29-
#if WANT_SIMD_EXCEPT
30-
static float32x4_t VPCS_ATTR NOINLINE
31-
special_case (float32x4_t x, float32x4_t y, uint32x4_t special)
32-
{
33-
return v_call_f32 (asinf, x, y, special);
34-
}
35-
#endif
3626

3727
/* Single-precision implementation of vector asin(x).
3828
39-
40-
For |x| <0.5, use order 4 polynomial P such that the final
29+
For |x| in [0, 0.5), use order 4 polynomial P such that the final
4130
approximation is an odd polynomial: asin(x) ~ x + x^3 P(x^2).
4231
4332
The largest observed error in this region is 0.83 ulps,
@@ -55,16 +44,6 @@ float32x4_t VPCS_ATTR NOINLINE V_NAME_F1 (asin) (float32x4_t x)
5544

5645
uint32x4_t ix = vreinterpretq_u32_f32 (x);
5746
uint32x4_t ia = vandq_u32 (ix, v_u32 (AbsMask));
58-
59-
#if WANT_SIMD_EXCEPT
60-
/* Special values need to be computed with scalar fallbacks so
61-
that appropriate fp exceptions are raised. */
62-
uint32x4_t special
63-
= vcgtq_u32 (vsubq_u32 (ia, v_u32 (Small)), v_u32 (One - Small));
64-
if (unlikely (v_any_u32 (special)))
65-
return special_case (x, x, v_u32 (0xffffffff));
66-
#endif
67-
6847
float32x4_t ax = vreinterpretq_f32_u32 (ia);
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uint32x4_t a_lt_half = vcaltq_f32 (x, v_f32 (0.5f));
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@@ -100,7 +79,6 @@ HALF_WIDTH_ALIAS_F1 (asin)
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TEST_SIG (V, F, 1, asin, -1.0, 1.0)
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TEST_ULP (V_NAME_F1 (asin), 1.91)
103-
TEST_DISABLE_FENV_IF_NOT (V_NAME_F1 (asin), WANT_SIMD_EXCEPT)
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TEST_INTERVAL (V_NAME_F1 (asin), 0, 0x1p-12, 5000)
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TEST_INTERVAL (V_NAME_F1 (asin), 0x1p-12, 0.5, 50000)
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TEST_INTERVAL (V_NAME_F1 (asin), 0.5, 1.0, 50000)

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