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T1C Architecture Documentation

T1C (Tier 1 Chip) | Alexzo | Sarthak | MIT License

1. Core Concept — D-IMC

T1C uses Digital In-Memory Computing (D-IMC). Instead of moving data from memory to a processor and back, computation happens inside the SRAM array.

Traditional Chip:
Memory → [long bus] → CPU → [long bus] → Memory
         ^^^^ This is the bottleneck ^^^^

T1C D-IMC:
Memory = CPU (computation happens inside memory)
         No bus. No bottleneck.

This eliminates the Von Neumann bottleneck — the #1 cause of inefficiency in AI chips.

2. MAAU — Core Chip Specifications

Parameter 65nm (Primary) 130nm (Free/Research)
Process GlobalFoundries 65LP IHP SG13G2 (free)
Compute Die 5×5mm = 25mm² Larger die
I/O Die 3×3mm = 9mm² 3×3mm
Transistors ~180–200M ~50–60M
Clock 500MHz 300MHz
INT4 GFLOPS 200–400 80–150
Power (target) 2–4W 3–6W
Voltage 0.75–0.90V adaptive 1.0–1.2V
Voltage Stability ±3mV (5-layer AVS) ±3mV
Cost $15–40/chip FREE (research)

2.1 On-Chip Memory

Block Size Purpose
Weight SRAM 32MB Model weights (weight-stationary)
Activation SRAM 24MB Layer activations
KV-Cache SRAM 24MB Transformer KV pairs (TurboQuant)
Instruction Cache 8MB MLIR ops cache
Scratchpad 8MB Temporary results
Total 96MB All zero-latency access

2.2 Compute Units

  • Dual MAC Array — INT2/INT4/INT8/FP8/FP16/BF16
  • Flash-Attention V2 — With GQA (LLaMA 3, Mistral, Gemma compatible)
  • TurboQuant PolarQuant — 4-bit KV-cache compression (QJL dropped)
  • Sparsity Engine — Hardware zero-skip
  • RMSNORM Unit — Dedicated hardware
  • SOFTMAX Unit — Dedicated hardware

2.3 Voltage Stability — 5-Layer AVS

The 5-layer Adaptive Voltage Stack achieves ±3mV — better than most commercial chips:

Layer Mechanism Response
1 On-chip LDO (4 domains) 50–100ns
2 On-chip MOM caps (10nF/domain) < 1ns
3 PCB 0402 ceramics (×16/MAAU) 10ns–1μs
4 PCB bulk caps (100μF) 1μs–1ms
5 I2C Adaptive VRM (TI TPS546D24A) 1ms

Result: voltage fluctuations 100–350mV (crash) → < 10mV (stable) ✅

3. Blade — Carrier Board

8 MAAAUs on a single PCB blade.

Parameter Specification
MAAU Count 8 per blade
Memory 64GB LPDDR5X (168 GB/s wide-bus)
Power 24–40W (clock gating active)
Cooling Passive < 30W / 92mm fan > 30W
Host Dual PCIe Gen4 x8 + retimer
Inter-Blade 25GbE networking
Controller Dual STM32H7 (redundant)
Storage M.2 NVMe (direct DMA)
Cost $280–$650 (verified BOM)

Memory Architecture — Wide-Bus LPDDR5X

HBM was impossible for DIY (requires TSMC CoWoS). T1C uses a smart alternative:

  • 4× LPDDR5X chips per MAAU region
  • Each chip: 32-bit bus at 6400 MT/s
  • Combined: 128-bit wide bus = 168 GB/s
  • Assembly: standard PCB reflow — fully DIY possible

4. MIM — Multi-Instance MAAU

Each physical MAAU can be partitioned into up to 4 isolated hardware slices.

Config Slices SRAM/Slice Use Case
Full 1 96MB Single large model
MIM-2 2 48MB each Two 7B models parallel
MIM-4 4 24MB each 4 small models / API server

Isolation is hardware-enforced:

  • SRAM MMU: each slice has hardware page tables
  • LDO: each slice gets dedicated power domain
  • DMA: each slice has dedicated channel
  • Clock: each slice has independent gated tree

Runtime reconfigurable: < 100ms per MAAU (no reboot)

5. TurboQuant — KV-Cache Compression

T1C implements TurboQuant (Google Research, ICLR 2026, arXiv:2504.19874).

T1C uses PolarQuant-only (QJL dropped):

  • 5+ community teams confirmed QJL hurts in practice
  • PolarQuant-only = better accuracy, simpler hardware
Mode Compression Accuracy Use
4-bit turbo4 4× Lossless all models ✅ Default
3-bit turbo3 6× Near-lossless 8B+ only Optional
2-bit turbo2 8× Noticeable loss Research only

Result: 24MB KV-Cache SRAM → 96MB effective capacity (4-bit default)

6. All Problems Fixed

Problem Fix
Voltage instability 5-layer AVS → ±3mV ✅
Thermal throttling 8 sensors/chip, honest cooling guide ✅
HBM packaging impossible Wide-bus LPDDR5X — DIY possible ✅
PCIe Gen5 signal issues Dual Gen4 + retimer ✅
TurboQuant QJL hurts PolarQuant-only ✅
MIM reboot required Runtime resize < 100ms ✅
Yield 35–45% Run 1 3-run strategy + redundancy ✅
100 PFLOPS fake claim Honest 200–400 GFLOPS/MAAU ✅

7. Fabrication Guide

Free Option — IHP Germany (130nm)

  1. Design RTL using OpenLane 2.0 + IHP 130nm PDK
  2. Submit to IHP open shuttle (free for research/open source)
  3. Wait 6–10 months
  4. Chips arrive — test and iterate

Paid Option — GlobalFoundries 65LP

  1. Design RTL using OpenLane 2.0 + GF 65LP PDK
  2. Submit to GF MPW shuttle
  3. Cost: $15–40 per chip (shared wafer)
  4. Wait 8–12 months

Tools (All Free)

  • OpenLane 2.0 — RTL to GDSII
  • Magic VLSI — layout verification
  • Verilator — simulation
  • KiCad 8 — PCB design
  • JLCPCB — PCB fabrication ($40–100)

T1C Architecture v1.0 | Alexzo | Sarthak | MIT License