2 files changed
+2
-2
lines changed- intel/Modules.tcl+2
- intel/doc/mi.rst+1-1
- intel/src/DevTree.tcl+7-1
- intel/src/comp/jtag_op_ctrl/Modules.tcl+17
- intel/src/comp/jtag_op_ctrl/jtag_op_ctrl_arch.vhd+35
- intel/src/comp/jtag_op_ctrl/jtag_op_ctrl_empty.vhd+19
- intel/src/comp/jtag_op_ctrl/jtag_op_ctrl_ent.vhd+58
- intel/src/comp/network_mod/comp/network_mod_core/network_mod_core_etile.vhd+157-331
- intel/src/comp/network_mod/comp/network_mod_logic/network_mod_logic.vhd+14-2
- intel/src/comp/network_mod/uvm/Modules.tcl+3-1
- intel/src/comp/network_mod/uvm/signals_sig.fdo+6-5
- intel/src/comp/network_mod/uvm/tbench/env/env.sv+12-9
- intel/src/comp/network_mod/uvm/tbench/env/model.sv+1
- intel/src/comp/network_mod/uvm/tbench/env/pkg.sv+4
- intel/src/comp/network_mod/uvm/tbench/env/reg_sequence.sv+314
- intel/src/comp/network_mod/uvm/tbench/env/registers.sv+29
- intel/src/comp/network_mod/uvm/tbench/env/regmodel.sv+119
- intel/src/comp/network_mod/uvm/tbench/env/sequence.sv+77-35
- intel/src/comp/network_mod/uvm/tbench/env/sequencer.sv+13-1
- intel/src/comp/network_mod/uvm/top_level.fdo+2-10
- intel/src/fpga_common.vhd+24
- intel/src/mi_addr_space_pkg.vhd+2-2
- comp/debug/jtag_op_client/DevTree.tcl+11
- comp/debug/jtag_op_client/Modules.tcl+16
- comp/debug/jtag_op_client/jtag_op_client.vhd+199
- comp/debug/jtag_op_client/jtag_op_ip.ip+2.7k
- comp/debug/jtag_op_client/readme.rst+87
- comp/debug/jtag_op_client/sw/jtag_op_mgmt.py+91
- comp/debug/jtag_op_client/synth/Makefile+18
- comp/mfb_tools/flow/enabler/enabler.vhd+8-7
- comp/nic/mac_lite/rx_mac_lite/rx_mac_lite.vhd+7-3
- comp/nic/mac_lite/rx_mac_lite/uvm/Modules.tcl+9
- comp/nic/mac_lite/rx_mac_lite/uvm/base.sv+170
- comp/nic/mac_lite/rx_mac_lite/uvm/pkg.sv+21
- comp/nic/mac_lite/rx_mac_lite/uvm/registers.sv+236
- comp/nic/mac_lite/rx_mac_lite/uvm/regmodel.sv+160
- comp/nic/mac_lite/rx_mac_lite/uvm/rfc.sv+258
- comp/nic/mac_lite/tx_mac_lite/uvm/Modules.tcl+9
- comp/nic/mac_lite/tx_mac_lite/uvm/pkg.sv+19
- comp/nic/mac_lite/tx_mac_lite/uvm/registers.sv+96
- comp/nic/mac_lite/tx_mac_lite/uvm/regmodel.sv+117
- comp/uvm/common/pkg.sv+1
- comp/uvm/common/sync.sv+56
- comp/uvm/logic_vector_array_avst/sequence.sv+1-1
- comp/uvm/mi/reg2bus_convert.sv+70-10
- comp/uvm/probe/cbs.sv+3
- comp/uvm/reset/sequence.sv+19-5
- doc/source/debug.rst+1
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