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PeterJhonPeterJhon
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Add CherryUSB & Add PWM5配置
1 parent 74ae71e commit 03f30a1

20 files changed

Lines changed: 851 additions & 47 deletions

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‎.gitmodules‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -11,3 +11,6 @@
1111
[submodule "src/lib/dronecan/libcanard"]
1212
path = src/lib/dronecan/libcanard
1313
url = https://github.com/dronecan/libcanard.git
14+
[submodule "src/lib/cherryusb"]
15+
path = src/lib/cherryusb
16+
url = https://github.com/Firmament-Autopilot/CherryUSB.git

‎target/infineon/edge-e83/libraries/SConscript‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -8,5 +8,7 @@ list = os.listdir(cwd)
88

99
if GetDepend(['BSP_USING_FREERTOS']):
1010
objs = objs + SConscript('abstraction-rtos/SConscript')
11-
12-
Return('objs')
11+
12+
if GetDepend('PKG_USING_CHERRYUSB') or GetDepend('RT_USING_CHERRYUSB'):
13+
objs = objs + SConscript('../../../../../../../src/lib/cherryusb/SConscript')
14+
Return('objs')

‎target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_peripheral_clocks.c‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -60,9 +60,9 @@ void init_cycfg_peripheral_clocks(void)
6060
Cy_SysClk_PeriPclkDisableDivider((en_clk_dst_t)CYBSP_BT_UART_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_16_5_BIT, 0U);
6161
Cy_SysClk_PeriPclkSetFracDivider((en_clk_dst_t)CYBSP_BT_UART_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_16_5_BIT, 0U, 107U, 16U);
6262
Cy_SysClk_PeriPclkEnableDivider((en_clk_dst_t)CYBSP_BT_UART_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_16_5_BIT, 0U);
63-
Cy_SysClk_PeriPclkDisableDivider((en_clk_dst_t)CYBSP_SMARTIO_PWM_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_16_5_BIT, 1U);
64-
Cy_SysClk_PeriPclkSetFracDivider((en_clk_dst_t)CYBSP_SMARTIO_PWM_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_16_5_BIT, 1U, 4999U, 0U);
65-
Cy_SysClk_PeriPclkEnableDivider((en_clk_dst_t)CYBSP_SMARTIO_PWM_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_16_5_BIT, 1U);
63+
Cy_SysClk_PeriPclkDisableDivider((en_clk_dst_t)CYBSP_PWM_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_16_5_BIT, 1U);
64+
Cy_SysClk_PeriPclkSetFracDivider((en_clk_dst_t)CYBSP_PWM_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_16_5_BIT, 1U, 4999U, 0U);
65+
Cy_SysClk_PeriPclkEnableDivider((en_clk_dst_t)CYBSP_PWM_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_16_5_BIT, 1U);
6666
Cy_SysClk_PeriPclkDisableDivider((en_clk_dst_t)CYBSP_SMART_IO_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_24_5_BIT, 0U);
6767
Cy_SysClk_PeriPclkSetFracDivider((en_clk_dst_t)CYBSP_SMART_IO_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_24_5_BIT, 0U, 505049U, 0U);
6868
Cy_SysClk_PeriPclkEnableDivider((en_clk_dst_t)CYBSP_SMART_IO_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_24_5_BIT, 0U);

‎target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_peripheral_clocks.h‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -155,18 +155,18 @@ extern "C" {
155155
#define CYBSP_BT_UART_CLK_DIV_GRP_NUM CYBSP_BT_UART_CLK_DIV_GRP_NUM
156156
#endif /* !defined (CYBSP_BT_UART_CLK_DIV_GRP_NUM) */
157157

158-
#define CYBSP_SMARTIO_PWM_CLK_DIV_ENABLED 1U
158+
#define CYBSP_PWM_CLK_DIV_ENABLED 1U
159159

160160
#if !defined (CY_USING_HAL) && !defined (CY_USING_HAL_LITE)
161-
#define CYBSP_SMARTIO_PWM_CLK_DIV_HW CY_SYSCLK_DIV_16_5_BIT
161+
#define CYBSP_PWM_CLK_DIV_HW CY_SYSCLK_DIV_16_5_BIT
162162
#endif /* !defined (CY_USING_HAL) && !defined (CY_USING_HAL_LITE) */
163163

164-
#define CYBSP_SMARTIO_PWM_CLK_DIV_NUM 1U
165-
#define CYBSP_SMARTIO_PWM_CLK_DIV_GRP_NUM ((1U << PERI_PCLK_GR_NUM_Pos) | (0U << PERI_PCLK_INST_NUM_Pos))
164+
#define CYBSP_PWM_CLK_DIV_NUM 1U
165+
#define CYBSP_PWM_CLK_DIV_GRP_NUM ((1U << PERI_PCLK_GR_NUM_Pos) | (0U << PERI_PCLK_INST_NUM_Pos))
166166

167-
#if !defined (CYBSP_SMARTIO_PWM_CLK_DIV_GRP_NUM)
168-
#define CYBSP_SMARTIO_PWM_CLK_DIV_GRP_NUM CYBSP_SMARTIO_PWM_CLK_DIV_GRP_NUM
169-
#endif /* !defined (CYBSP_SMARTIO_PWM_CLK_DIV_GRP_NUM) */
167+
#if !defined (CYBSP_PWM_CLK_DIV_GRP_NUM)
168+
#define CYBSP_PWM_CLK_DIV_GRP_NUM CYBSP_PWM_CLK_DIV_GRP_NUM
169+
#endif /* !defined (CYBSP_PWM_CLK_DIV_GRP_NUM) */
170170

171171
#define CYBSP_SMART_IO_CLK_DIV_ENABLED 1U
172172

‎target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_peripherals.c‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1152,8 +1152,8 @@ const cy_stc_tcpwm_pwm_config_t tcpwm_0_group_0_cnt_5_config =
11521152
const mtb_hal_peri_div_t tcpwm_0_group_0_cnt_5_clock_ref =
11531153
{
11541154
.clk_dst = (en_clk_dst_t)PCLK_TCPWM0_CLOCK_COUNTER_EN5,
1155-
.div_type = CY_SYSCLK_DIV_16_BIT,
1156-
.div_num = 3,
1155+
.div_type = CY_SYSCLK_DIV_16_5_BIT,
1156+
.div_num = 1,
11571157
};
11581158
const mtb_hal_clock_t tcpwm_0_group_0_cnt_5_hal_clock =
11591159
{
@@ -1401,7 +1401,7 @@ void init_cycfg_peripherals(void)
14011401
#if defined (CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE)
14021402
Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_TCPWM0_PERI_NR, CY_MMIO_TCPWM0_GROUP_NR, CY_MMIO_TCPWM0_SLAVE_NR, CY_MMIO_TCPWM0_CLK_HF_NR);
14031403
#endif /* defined (CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE) */
1404-
Cy_SysClk_PeriphAssignDivider(PCLK_TCPWM0_CLOCK_COUNTER_EN5, CY_SYSCLK_DIV_16_BIT, 3U);
1404+
Cy_SysClk_PeriphAssignDivider(PCLK_TCPWM0_CLOCK_COUNTER_EN5, CY_SYSCLK_DIV_16_5_BIT, 1U);
14051405
#if defined (CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE)
14061406
Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_TCPWM0_PERI_NR, CY_MMIO_TCPWM0_GROUP_NR, CY_MMIO_TCPWM0_SLAVE_NR, CY_MMIO_TCPWM0_CLK_HF_NR);
14071407
#endif /* defined (CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE) */

‎target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_pins.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -840,7 +840,7 @@ const cy_stc_gpio_pin_config_t CYBSP_SMART_IO_OUTPUT_config =
840840
};
841841
const cy_stc_gpio_pin_config_t CYBSP_WIFI_HOST_WAKE_config =
842842
{
843-
.outVal = 0,
843+
.outVal = 1,
844844
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
845845
.hsiom = CYBSP_WIFI_HOST_WAKE_HSIOM,
846846
.intEdge = CY_GPIO_INTR_RISING,

‎target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_pins.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -760,7 +760,7 @@ extern "C" {
760760
#define CYBSP_ETH_TX_CTL_NUM CYBSP_WIFI_HOST_WAKE_NUM
761761
#define CYBSP_WIFI_HOST_WAKE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
762762
#define CYBSP_ETH_TX_CTL_DRIVEMODE CYBSP_WIFI_HOST_WAKE_DRIVEMODE
763-
#define CYBSP_WIFI_HOST_WAKE_INIT_DRIVESTATE 0
763+
#define CYBSP_WIFI_HOST_WAKE_INIT_DRIVESTATE 1
764764
#define CYBSP_ETH_TX_CTL_INIT_DRIVESTATE CYBSP_WIFI_HOST_WAKE_INIT_DRIVESTATE
765765
#ifndef ioss_0_port_11_pin_4_HSIOM
766766
#define ioss_0_port_11_pin_4_HSIOM HSIOM_SEL_GPIO

‎target/infineon/edge-e83/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/design.modus‎

Lines changed: 6 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -2604,7 +2604,7 @@
26042604
<Personality template="pclk_v2" version="1.1" instance="vy6xFOXZU08">
26052605
<Block location="peri[0].group[1].div_16_5[1]" locked="true">
26062606
<Aliases>
2607-
<Alias value="CYBSP_SMARTIO_PWM_CLK_DIV"/>
2607+
<Alias value="CYBSP_PWM_CLK_DIV"/>
26082608
</Aliases>
26092609
</Block>
26102610
<Parameters>
@@ -4305,18 +4305,10 @@
43054305
<Port name="peri[0].group[1].div_16[2].clk[0]"/>
43064306
<Port name="tcpwm[0].group[0].cnt[0].clock_counter_en[0]"/>
43074307
</Net>
4308-
<Net>
4309-
<Port name="peri[0].group[1].div_16[3].clk[0]"/>
4310-
<Port name="tcpwm[0].group[0].cnt[5].clock_counter_en[0]"/>
4311-
</Net>
43124308
<Net>
43134309
<Port name="peri[0].group[1].div_16_5[0].clk[0]"/>
43144310
<Port name="scb[4].clock_scb_en[0]"/>
43154311
</Net>
4316-
<Net>
4317-
<Port name="peri[0].group[1].div_16_5[1].clk[0]"/>
4318-
<Port name="tcpwm[0].group[1].cnt[6].clock_counter_en[0]"/>
4319-
</Net>
43204312
<Net>
43214313
<Port name="peri[0].group[1].div_8[0].clk[0]"/>
43224314
<Port name="scb[5].clock_scb_en[0]"/>
@@ -4370,6 +4362,11 @@
43704362
<Port name="peri[0].mmio[0].clk_pclk_root[5]"/>
43714363
<Port name="srss[0].clock[0].hfclk[9].root_clk[0]"/>
43724364
</Net>
4365+
<Net>
4366+
<Port name="peri[0].group[1].div_16_5[1].clk[0]"/>
4367+
<Port name="tcpwm[0].group[0].cnt[5].clock_counter_en[0]"/>
4368+
<Port name="tcpwm[0].group[1].cnt[6].clock_counter_en[0]"/>
4369+
</Net>
43734370
<Net>
43744371
<Port name="peri[0].group[3].div_8[0].clk_pclk_root[0]"/>
43754372
<Port name="peri[1].group[2].div_8[0].clk_pclk_root[0]"/>

‎target/infineon/edge-e83/m33/applications/main.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
#include <rtdevice.h>
33
#include <board.h>
44

5-
#define LED_PIN_B GET_PIN(16, 5)
5+
#define LED_PIN_B GET_PIN(16, 6)
66

77
int main(void)
88
{

‎target/infineon/edge-e83/m33/applications/pwm_test.c‎

Lines changed: 56 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,56 @@
1+
#include "drv_pwm.h"
2+
#define PWM_DEV_NAME "pwm5"
3+
#define PWM_DEV_CHANNEL 1
4+
5+
struct rt_device_pwm *pwm_dev;
6+
7+
static int pwm_sample(int argc, char *argv[])
8+
{
9+
rt_uint32_t period, pulse, dir;
10+
11+
period = 5000000;
12+
dir = 1;
13+
pulse = 0;
14+
struct rt_pwm_configuration config = {0};
15+
pwm_dev = (struct rt_device_pwm *)rt_device_find(PWM_DEV_NAME);
16+
17+
if (pwm_dev == RT_NULL)
18+
{
19+
rt_kprintf("pwm sample run failed! can't find %s device!\n", PWM_DEV_NAME);
20+
return -RT_ERROR;
21+
}
22+
23+
rt_pwm_set(pwm_dev, PWM_DEV_CHANNEL, period, pulse);
24+
rt_pwm_enable(pwm_dev, PWM_DEV_CHANNEL);
25+
// rt_pwm_disable(pwm_dev, PWM_DEV_CHANNEL);
26+
rt_kprintf("Now PWM[%s] Channel[%d] Period[%d] Pulse[%d]\n", PWM_DEV_NAME, PWM_DEV_CHANNEL, period, pulse);
27+
28+
while (1)
29+
{
30+
rt_thread_mdelay(80);
31+
32+
if (dir)
33+
{
34+
pulse += 50000;
35+
}
36+
else
37+
{
38+
pulse -= 50000;
39+
}
40+
41+
if (pulse >= period)
42+
{
43+
dir = 0;
44+
}
45+
46+
if (0 == pulse)
47+
{
48+
dir = 1;
49+
}
50+
51+
rt_pwm_set(pwm_dev, PWM_DEV_CHANNEL, period, pulse);
52+
rt_device_control((rt_device_t)pwm_dev, PWM_CMD_GET, &config);
53+
rt_kprintf("period %d pulse %d \r\n", config.period, config.pulse);
54+
}
55+
}
56+
MSH_CMD_EXPORT(pwm_sample, <pwm0> channel5 sample);

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