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| 1 | +#ifndef EDGE_IPC_COMMON_H |
| 2 | +#define EDGE_IPC_COMMON_H |
| 3 | + |
| 4 | +#include "cy_ipc_pipe.h" |
| 5 | + |
| 6 | +#define CY_IPC_MAX_ENDPOINTS (5UL) |
| 7 | +#define CY_IPC_CYPIPE_CLIENT_CNT (8UL) |
| 8 | + |
| 9 | +#define CY_IPC_CHAN_CYPIPE_EP1 (4UL) |
| 10 | +#define CY_IPC_INTR_CYPIPE_EP1 (4UL) |
| 11 | +#define CY_IPC_CHAN_CYPIPE_EP2 (15UL) |
| 12 | +#define CY_IPC_INTR_CYPIPE_EP2 (5UL) |
| 13 | + |
| 14 | +#define CY_IPC_CYPIPE_CHAN_MASK_EP1 CY_IPC_CH_MASK(CY_IPC_CHAN_CYPIPE_EP1) |
| 15 | +#define CY_IPC_CYPIPE_INTR_MASK_EP1 CY_IPC_INTR_MASK(CY_IPC_INTR_CYPIPE_EP1) |
| 16 | +#define CY_IPC_INTR_CYPIPE_PRIOR_EP1 (1UL) |
| 17 | +#define CY_IPC_INTR_CYPIPE_MUX_EP1 (CY_IPC0_INTR_MUX(CY_IPC_INTR_CYPIPE_EP1)) |
| 18 | +#define CM33_IPC_PIPE_EP_ADDR (1UL) |
| 19 | +#define CM33_IPC_PIPE_CLIENT_ID (3UL) |
| 20 | + |
| 21 | +#define CY_IPC_CYPIPE_CHAN_MASK_EP2 CY_IPC_CH_MASK(CY_IPC_CHAN_CYPIPE_EP2) |
| 22 | +#define CY_IPC_CYPIPE_INTR_MASK_EP2 CY_IPC_INTR_MASK(CY_IPC_INTR_CYPIPE_EP2) |
| 23 | +#define CY_IPC_INTR_CYPIPE_PRIOR_EP2 (1UL) |
| 24 | +#define CY_IPC_INTR_CYPIPE_MUX_EP2 (CY_IPC0_INTR_MUX(CY_IPC_INTR_CYPIPE_EP2)) |
| 25 | +#define CM55_IPC_PIPE_EP_ADDR (2UL) |
| 26 | +#define CM55_IPC_PIPE_CLIENT_ID (5UL) |
| 27 | + |
| 28 | +#define CY_IPC_CYPIPE_INTR_MASK (CY_IPC_CYPIPE_CHAN_MASK_EP1 | CY_IPC_CYPIPE_CHAN_MASK_EP2) |
| 29 | +#define IPC_DEMO_SEMA_NUM (48UL) |
| 30 | + |
| 31 | +#define RC_CHANNEL_COUNT (8U) |
| 32 | +#define RC_MAGIC_WORD (0x5243444DU) |
| 33 | +#define RC_ROLE_M33 (0x33U) |
| 34 | +#define RC_ROLE_M55_ECHO (0x55U) |
| 35 | + |
| 36 | +/* Stress-test tuning knobs */ |
| 37 | +#define EDGE_IPC_FRAME_POOL_SIZE (64U) |
| 38 | +#define EDGE_IPC_ECHO_QUEUE_SIZE (64U) |
| 39 | +#define EDGE_IPC_STRESS_HZ (1000U) |
| 40 | +#define EDGE_IPC_STRESS_BURST (4U) |
| 41 | +#define EDGE_IPC_SEMA_RETRY_MAX (2U) |
| 42 | +#define EDGE_IPC_PRINT_INTERVAL_MS (1000U) |
| 43 | + |
| 44 | +typedef struct |
| 45 | +{ |
| 46 | + uint8_t client_id; |
| 47 | + uint16_t intr_mask; |
| 48 | + uint8_t role; |
| 49 | + uint32_t magic; |
| 50 | + uint32_t seq; |
| 51 | + uint16_t channel[RC_CHANNEL_COUNT]; |
| 52 | + uint32_t checksum; |
| 53 | +} edge_rc_frame_t; |
| 54 | + |
| 55 | +static inline uint32_t edge_rc_checksum(const edge_rc_frame_t* frame) |
| 56 | +{ |
| 57 | + uint32_t sum = frame->magic ^ frame->role ^ frame->seq; |
| 58 | + uint32_t i; |
| 59 | + |
| 60 | + for (i = 0; i < RC_CHANNEL_COUNT; i++) |
| 61 | + { |
| 62 | + sum ^= ((uint32_t)frame->channel[i] << (i & 0x7)); |
| 63 | + sum = (sum << 3) | (sum >> 29); |
| 64 | + } |
| 65 | + |
| 66 | + return sum; |
| 67 | +} |
| 68 | + |
| 69 | +#endif |
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