11/**
22 * @file ahci.h
33 * @author Pradosh ([email protected] ) 4- * @brief The headers for AHCI Driver.
4+ * @brief Header definitions and structures for the AHCI Driver.
55 * @version 0.1
66 * @date 2023-12-16
77 *
88 * @copyright Copyright (c) Pradosh 2023
9- *
109 */
10+
11+ #ifndef AHCI_H
12+ #define AHCI_H
13+
1114#include <basics.h>
1215
16+ /**
17+ * @brief Base memory address for AHCI ports.
18+ */
1319#define AHCI_PORT_BASE 0x400
1420
15- #define AHCI_PORT_CMD_ST 0x1
16- #define AHCI_PORT_CMD_FRE 0x10
17- #define AHCI_PORT_CMD_FR 0x400
21+ /**
22+ * @brief AHCI port command flags.
23+ */
24+ #define AHCI_PORT_CMD_ST 0x1 /**< Start command. */
25+ #define AHCI_PORT_CMD_FRE 0x10 /**< FIS receive enable. */
26+ #define AHCI_PORT_CMD_FR 0x400 /**< FIS receive running. */
1827
28+ /**
29+ * @brief AHCI device signatures.
30+ */
1931#define sata_disk 0x00000101
2032#define satapi_disk 0xEB140101
2133#define semb_disk 0xC33C0101
2234#define port_multiplier 0x96690101
2335
36+ /**
37+ * @brief Standard sector size in bytes.
38+ */
2439#define SECTOR_SIZE 512
2540
26- // Structure to represent an AHCI command header
41+ /**
42+ * @brief AHCI command header structure.
43+ *
44+ * Represents the command header for a single AHCI port.
45+ */
2746typedef struct {
28- uint16_t cfl :5 ; // Command FIS length in DWORDS
29- uint16_t a :1 ; // ATAPI
30- uint16_t w :1 ; // Write (1 = H->D , 0 = D->H)
31- uint16_t p :1 ; // Prefetchable
32- uint16_t r :1 ; // Reset
33- uint16_t b :1 ; // BIST
34- uint16_t c :1 ; // Clear busy upon R_OK
35- uint16_t rsv0 :1 ; // Reserved
36- uint16_t pmp :4 ; // Port multiplier port
37- uint16_t prdtl ; // Number of PRDT entries
38- uint32_t prdbc ; // Physical region descriptor byte count transferred
39- uint32_t ctba ; // Command table base address (lower 32-bit)
40- uint32_t ctbau ; // Command table base address upper 32-bit
41- uint32_t rsv1 [4 ]; // Reserved
47+ uint16_t cfl :5 ; /**< Command FIS length in DWORDS */
48+ uint16_t a :1 ; /**< ATAPI flag */
49+ uint16_t w :1 ; /**< Write flag (1 = Host to Device , 0 = Device to Host) */
50+ uint16_t p :1 ; /**< Prefetchable */
51+ uint16_t r :1 ; /**< Reset */
52+ uint16_t b :1 ; /**< BIST flag */
53+ uint16_t c :1 ; /**< Clear busy upon R_OK */
54+ uint16_t rsv0 :1 ; /**< Reserved */
55+ uint16_t pmp :4 ; /**< Port multiplier port */
56+ uint16_t prdtl ; /**< Number of PRDT entries */
57+ uint32_t prdbc ; /**< Physical Region Descriptor byte count transferred */
58+ uint32_t ctba ; /**< Command table base address (lower 32 bits) */
59+ uint32_t ctbau ; /**< Command table base address upper 32 bits */
60+ uint32_t rsv1 [4 ]; /**< Reserved */
4261} __attribute__((packed )) ahci_command_header_t ;
4362
44-
45- // Structure to represent a Physical Region Descriptor
63+ /**
64+ * @brief Physical Region Descriptor Table (PRDT) entry.
65+ */
4666typedef struct {
47- uint32_t dba ; // Data base address
48- uint32_t dbau ; // Data base address upper 32 bits
49- uint32_t rsv0 ; // Reserved
50- uint32_t dbc :22 ; // Byte count, 4M max
51- uint32_t rsv1 :9 ;
52- uint32_t i :1 ; // Interrupt on completion
67+ uint32_t dba ; /**< Data base address */
68+ uint32_t dbau ; /**< Data base address upper 32 bits */
69+ uint32_t rsv0 ; /**< Reserved */
70+ uint32_t dbc :22 ; /**< Byte count (maximum 4M) */
71+ uint32_t rsv1 :9 ;
72+ uint32_t i :1 ; /**< Interrupt on completion */
5373} __attribute__((packed )) prdt_entry_t ;
5474
75+ /**
76+ * @brief AHCI command table structure.
77+ */
5578typedef struct {
56- uint8_t cfis [64 ]; // Command FIS
57- uint8_t acmd [16 ]; // ATAPI command (optional)
58- uint8_t rsv [48 ]; // Reserved
59- prdt_entry_t prdt_entry [1 ]; // PRDT entries (can allocate more)
79+ uint8_t cfis [64 ]; /**< Command FIS */
80+ uint8_t acmd [16 ]; /**< ATAPI command (optional) */
81+ uint8_t rsv [48 ]; /**< Reserved */
82+ prdt_entry_t prdt_entry [1 ]; /**< PRDT entries (can allocate more as needed) */
6083} __attribute__((packed )) ahci_command_table_t ;
6184
85+ /**
86+ * @brief AHCI port registers and command header pointer.
87+ */
6288typedef volatile struct {
63- int32 clb ; // 0x00, command list base address, 1K-byte aligned
64- int32 clbu ; // 0x04, command list base address upper 32 bits
65- int32 fb ; // 0x08, FIS base address, 256-byte aligned
66- int32 fbu ; // 0x0C, FIS base address upper 32 bits
67- int32 is ; // 0x10, interrupt status
68- int32 ie ; // 0x14, interrupt enable
69- int32 cmd ; // 0x18, command and status
70- int32 rsv0 ; // 0x1C, reserved
71- int32 tfd ; // 0x20, task file data
72- int32 sig ; // 0x24, signature
73- int32 ssts ; // 0x28, SATA status (SCR0:SStatus)
74- int32 sctl ; // 0x2C, SATA control (SCR2:SControl)
75- int32 serr ; // 0x30, SATA error (SCR1:SError)
76- int32 sact ; // 0x34, SATA active (SCR3:SActive)
77- int32 ci ; // 0x38, command issue
78- int32 sntf ; // 0x3C, SATA notification (SCR4:SNotification)
79- int32 fbs ; // 0x40, FIS-based switch control
80- int32 rsv1 [11 ]; // 0x44 ~ 0x6F, reserved
81- int32 vendor [4 ]; // 0x70 ~ 0x7F, vendor specific
82- ahci_command_header_t * cmd_list ; // pointer to command header array
89+ int32 clb ; /**< Command list base address (1KB aligned) */
90+ int32 clbu ; /**< Command list base address upper 32 bits */
91+ int32 fb ; /**< FIS base address ( 256-byte aligned) */
92+ int32 fbu ; /**< FIS base address upper 32 bits */
93+ int32 is ; /**< Interrupt status */
94+ int32 ie ; /**< Interrupt enable */
95+ int32 cmd ; /**< Command and status */
96+ int32 rsv0 ; /**< Reserved */
97+ int32 tfd ; /**< Task file data */
98+ int32 sig ; /**< Signature */
99+ int32 ssts ; /**< SATA status (SCR0: SStatus) */
100+ int32 sctl ; /**< SATA control (SCR2: SControl) */
101+ int32 serr ; /**< SATA error (SCR1: SError) */
102+ int32 sact ; /**< SATA active (SCR3: SActive) */
103+ int32 ci ; /**< Command issue */
104+ int32 sntf ; /**< SATA notification (SCR4: SNotification) */
105+ int32 fbs ; /**< FIS-based switch control */
106+ int32 rsv1 [11 ]; /**< Reserved */
107+ int32 vendor [4 ]; /**< Vendor specific */
108+ ahci_command_header_t * cmd_list ; /**< Pointer to command header array */
83109} ahci_port ;
84110
85-
111+ /**
112+ * @brief AHCI controller registers.
113+ */
86114typedef volatile struct {
87- int32 cap ; // Host Capabilities
88- int32 ghc ; // Global Host Control
89- int32 is ; // Interrupt Status
90- int32 pi ; // Port Implemented
91- int32 vs ; // Version
92- int32 ccc_ctl ; // Command Completion Coalescing Control
93- int32 ccc_pts ; // Command Completion Coalescing Ports
94- int32 em_loc ; // Enclosure Management Location
95- int32 em_ctl ; // Enclosure Management Control
96- int32 cap2 ; // Host Capabilities Extended
97- int32 bohc ; // BIOS/OS Handoff Control and Status
98- int8 rsv [0xA0 - 0x2C ];
99- int8 vendor [0x100 - 0xA0 ];
100- ahci_port ports [32 ]; // Port control registers
115+ int32 cap ; /**< Host Capabilities */
116+ int32 ghc ; /**< Global Host Control */
117+ int32 is ; /**< Interrupt Status */
118+ int32 pi ; /**< Port Implemented */
119+ int32 vs ; /**< Version */
120+ int32 ccc_ctl ; /**< Command Completion Coalescing Control */
121+ int32 ccc_pts ; /**< Command Completion Coalescing Ports */
122+ int32 em_loc ; /**< Enclosure Management Location */
123+ int32 em_ctl ; /**< Enclosure Management Control */
124+ int32 cap2 ; /**< Host Capabilities Extended */
125+ int32 bohc ; /**< BIOS/OS Handoff Control and Status */
126+ int8 rsv [0xA0 - 0x2C ]; /**< Reserved */
127+ int8 vendor [0x100 - 0xA0 ]; /**< Vendor specific */
128+ ahci_port ports [32 ]; /**< AHCI port control registers */
101129} ahci_controller ;
102130
131+ /**
132+ * @brief Global AHCI controller pointer.
133+ */
103134extern ahci_controller * global_ahci_ctrl ;
104135
105136/**
106- * @brief Probes and detects all the AHCI Devices
137+ * @brief Probes and detects all AHCI devices connected to the controller.
107138 *
108- * @param ahci_ctrl The pointer to the ahci_controller structure or BAR of AHCI
139+ * @param ahci_ctrl Pointer to the AHCI controller structure.
109140 */
110141void detect_ahci_devices (ahci_controller * ahci_ctrl );
111142
143+ /**
144+ * @brief Reads sectors from a port using polling mode.
145+ *
146+ * @param port_number The AHCI port number to read from.
147+ * @param lba Logical block address to start reading.
148+ * @param sector_count Number of sectors to read.
149+ * @param buffer Pointer to the buffer to store data.
150+ * @return int 0 on success, negative on failure.
151+ */
152+ int ahci_read_sectors_polling (int port_number , uint64_t lba , uint32_t sector_count , void * buffer );
112153
113- int ahci_read_sectors_polling ( int port_number , uint64_t lba , uint32_t sector_count , void * buffer );
154+ #endif // AHCI_H
0 commit comments