HVDC feedforward does not work

[yonghongchen8]

In this code: https://github.com/NREL-Sienna/irtoc_experiments/blob/main/SplitArea_ReserveDeliverability/final_run_simulations_3stage_multiline.jl

HVDC flow is set to be fed forward from stage 1 to stage 2 and 3.
But
is_fixed.(uc2c.variables[InfrastructureSystems.Optimization.VariableKey{FlowActivePowerVariable, TwoTerminalGenericHVDCLine}("")])
are all 0.