Modifications in the HW masking machine to improve overscan transmission

Author: rodmarfran

FPGA_Developments/COM_Module_v2/Development/Communications_Module_v2/FEE_DATA_CONTROLLER/MASKING_MACHINE/masking_machine_ent.vhd

@@ -1,5 +1,5 @@
 # Reading C:/intelFPGA/18.1/modelsim_ase/tcl/vsim/pref.tcl
-# OpenFile D:/rfranca/Development/GitHub/SimuCam_Development4/FPGA_Developments/COM_Module_v2/Development/Testbench/comm_v2_testbench.mpf
+# OpenFile C:/Users/rfranca/Development/GitHub/SimuCam_Development_NFEE/FPGA_Developments/COM_Module_v2/Development/Testbench/comm_v2_testbench.mpf
 # Loading project comm_v2_testbench
 # Compile of avalon_mm_spacewire_registers_pkg.vhd was successful.
 # Compile of avalon_mm_spacewire_pkg.vhd was successful.
@@ -75,7 +75,7 @@
 # 71 compiles, 0 failed with no errors.
 vsim work.testbench_top
 # vsim work.testbench_top 
-# Start time: 00:51:50 on Oct 28,2021
+# Start time: 00:11:37 on Feb 02,2023
 # Loading std.standard
 # Loading std.textio(body)
 # Loading ieee.std_logic_1164(body)
@@ -161,161 +161,46 @@ vsim work.testbench_top
 # Loading work.delay_block_ent(rtl)
 # Loading work.cbuf_tb_avs_read_ent(rtl)
 # Loading work.cbuf_tb_avs_write_ent(rtl)
-# ** Warning: Design size of 28953 statements exceeds ModelSim-Intel FPGA Starter Edition recommended capacity.
+# ** Warning: Design size of 28979 statements exceeds ModelSim-Intel FPGA Starter Edition recommended capacity.
 # Expect performance to be adversely affected.
-add wave -position insertpoint sim:/testbench_top/spw_controller_stimuli_inst/*
+add wave -position insertpoint sim:/testbench_top/comm_v2_top_inst/fee_data_controller_top_inst/fee_left_imgdata_controller_top_inst/masking_machine_ent_inst/*
 # ** Warning: (vsim-WLF-5000) WLF file currently in use: vsim.wlf
 #           File in use by: rfranca  Hostname: ACER-AN5-RF  ProcessID: 52292
-#           Attempting to use alternate WLF file "./wlfty0f7xa".
+#           Attempting to use alternate WLF file "./wlfthaw2gr".
 # ** Warning: (vsim-WLF-5001) Could not open WLF file: vsim.wlf
-#           Using alternate file: ./wlfty0f7xa
-add wave -position insertpoint sim:/testbench_top/config_avalon_stimuli_inst/*
-add wave -position insertpoint sim:/testbench_top/comm_v2_top_inst/g_comm_avs_config_testbench_stimulli/comm_config_avalon_mm_stimulli_inst/*
-add wave -position insertpoint sim:/testbench_top/comm_v2_top_inst/rmap_target_top_inst/*
+#           Using alternate file: ./wlfthaw2gr
+add wave -position insertpoint sim:/testbench_top/comm_v2_top_inst/fee_data_controller_top_inst/fee_right_imgdata_controller_top_inst/masking_machine_ent_inst/*
 restart
-# ** Warning: Design size of 10550 statements exceeds ModelSim-Intel FPGA Starter Edition recommended capacity.
+# ** Warning: Design size of 10553 statements exceeds ModelSim-Intel FPGA Starter Edition recommended capacity.
 # Expect performance to be adversely affected.
 run
-# Compile of comm_config_avalon_mm_stimulli.vhd was successful.
-restart
-# Loading work.comm_config_avalon_mm_stimulli(rtl)
-# ** Warning: Design size of 19240 statements exceeds ModelSim-Intel FPGA Starter Edition recommended capacity.
-# Expect performance to be adversely affected.
-run
-# Compile of rmap_target_top.vhd was successful.
-restart
-# Loading work.rmap_target_top(rtl)
-# ** Warning: Design size of 18887 statements exceeds ModelSim-Intel FPGA Starter Edition recommended capacity.
-# Expect performance to be adversely affected.
-run
-# Compile of comm_config_avalon_mm_stimulli.vhd was successful.
-restart
-# Loading work.comm_config_avalon_mm_stimulli(rtl)
-# ** Warning: Design size of 19244 statements exceeds ModelSim-Intel FPGA Starter Edition recommended capacity.
-# Expect performance to be adversely affected.
-run
-# Compile of comm_config_avalon_mm_stimulli.vhd was successful.
-restart
-# Loading work.comm_config_avalon_mm_stimulli(rtl)
-# ** Warning: Design size of 19239 statements exceeds ModelSim-Intel FPGA Starter Edition recommended capacity.
-# Expect performance to be adversely affected.
-run
-# Compile of spw_controller_stimuli.vhd was successful.
-restart
-# Loading work.spw_controller_stimuli(rtl)
-# ** Warning: Design size of 18859 statements exceeds ModelSim-Intel FPGA Starter Edition recommended capacity.
-# Expect performance to be adversely affected.
-run
-# Compile of comm_config_avalon_mm_stimulli.vhd was successful.
-restart
-# Loading work.comm_config_avalon_mm_stimulli(rtl)
-# ** Warning: Design size of 19243 statements exceeds ModelSim-Intel FPGA Starter Edition recommended capacity.
-# Expect performance to be adversely affected.
-run
-# Compile of comm_config_avalon_mm_stimulli.vhd was successful.
+add wave -position insertpoint sim:/testbench_top/*
 restart
-# Loading work.comm_config_avalon_mm_stimulli(rtl)
-# ** Warning: Design size of 19243 statements exceeds ModelSim-Intel FPGA Starter Edition recommended capacity.
+# ** Warning: Design size of 10553 statements exceeds ModelSim-Intel FPGA Starter Edition recommended capacity.
 # Expect performance to be adversely affected.
 run
-# Compile of comm_config_avalon_mm_stimulli.vhd was successful.
+add wave -position insertpoint sim:/testbench_top/p_sync_generator/*
 restart
-# Loading work.comm_config_avalon_mm_stimulli(rtl)
-# ** Warning: Design size of 19243 statements exceeds ModelSim-Intel FPGA Starter Edition recommended capacity.
+# ** Warning: Design size of 10553 statements exceeds ModelSim-Intel FPGA Starter Edition recommended capacity.
 # Expect performance to be adversely affected.
 run
-# Compile of comm_config_avalon_mm_stimulli.vhd was successful.
+# Compile of testbench_top.vhd was successful.
 restart
-# Loading work.comm_config_avalon_mm_stimulli(rtl)
-# ** Warning: Design size of 19251 statements exceeds ModelSim-Intel FPGA Starter Edition recommended capacity.
+# Loading work.testbench_top(rtl)
+# ** Warning: Design size of 18835 statements exceeds ModelSim-Intel FPGA Starter Edition recommended capacity.
 # Expect performance to be adversely affected.
 run
-# Compile of comm_config_avalon_mm_stimulli.vhd was successful.
+# Compile of testbench_top.vhd was successful.
 restart
-# Loading work.comm_config_avalon_mm_stimulli(rtl)
-# ** Warning: Design size of 19251 statements exceeds ModelSim-Intel FPGA Starter Edition recommended capacity.
+# Loading work.testbench_top(rtl)
+# ** Warning: Design size of 18835 statements exceeds ModelSim-Intel FPGA Starter Edition recommended capacity.
 # Expect performance to be adversely affected.
 run
-# Compile of comm_config_avalon_mm_stimulli.vhd was successful.
-# Compile of rmap_target_top.vhd was successful.
-# 2 compiles, 0 failed with no errors.
+# Compile of testbench_top.vhd was successful.
 restart
-# Loading work.comm_config_avalon_mm_stimulli(rtl)
-# Loading work.rmap_target_top(rtl)
-# ** Warning: Design size of 19343 statements exceeds ModelSim-Intel FPGA Starter Edition recommended capacity.
+# Loading work.testbench_top(rtl)
+# ** Warning: Design size of 18835 statements exceeds ModelSim-Intel FPGA Starter Edition recommended capacity.
 # Expect performance to be adversely affected.
 run
-# Compile of avalon_mm_spacewire_registers_pkg.vhd was successful.
-# Compile of avalon_mm_spacewire_pkg.vhd was successful.
-# Compile of avalon_mm_spacewire_read_ent.vhd was successful.
-# Compile of avalon_mm_spacewire_write_ent.vhd was successful.
-# Compile of comm_config_avalon_mm_stimulli.vhd was successful.
-# Compile of windowing_dataset_pkg.vhd was successful.
-# Compile of comm_avm_buffers_pkg.vhd was successful.
-# Compile of comm_avm_buffers_reader_ent.vhd was successful.
-# Compile of comm_avm_buffers_controller_ent.vhd was successful.
-# Compile of windowing_data_sc_fifo.vhd was successful.
-# Compile of windowing_mask_sc_fifo.vhd was successful.
-# Compile of windowing_avsbuff_sc_fifo.vhd was successful.
-# Compile of windowing_fifo_pkg.vhd was successful.
-# Compile of windowing_data_fifo_ent.vhd was successful.
-# Compile of windowing_mask_fifo_ent.vhd was successful.
-# Compile of windowing_buffer_ent.vhd was successful.
-# Compile of spw_codec_pkg.vhd was successful.
-# Compile of spw_mux_ent.vhd was successful.
-# Compile of rmap_target_crc_pkg.vhd was successful.
-# Compile of rmap_target_pkg.vhd was successful.
-# Compile of rmap_target_command_ent.vhd was successful.
-# Compile of rmap_target_read_ent.vhd was successful.
-# Compile of rmap_target_reply_ent.vhd was successful.
-# Compile of rmap_target_write_ent.vhd was successful.
-# Compile of rmap_target_user_ent.vhd was successful.
-# Compile of rmap_target_top.vhd was successful.
-# Compile of fee_data_controller_pkg.vhd was successful.
-# Compile of masking_machine_sc_fifo.vhd was successful.
-# Compile of delay_machine_ent.vhd was successful.
-# Compile of masking_machine_ent.vhd was successful.
-# Compile of data_packet_header_gen_ent.vhd was successful.
-# Compile of data_packet_hk_writer_ent.vhd was successful.
-# Compile of data_packet_data_writer_ent.vhd was successful.
-# Compile of send_buffer_0_sc_fifo.vhd was successful.
-# Compile of send_buffer_1_sc_fifo.vhd was successful.
-# Compile of send_buffer_sc_1k_fifo.vhd was successful.
-# Compile of send_buffer_ent.vhd was successful.
-# Compile of comm_header_errinj_altsyncram.vhd was successful.
-# Compile of comm_content_errinj_altsyncram.vhd was successful.
-# Compile of comm_header_errinj_manager_ent.vhd was successful.
-# Compile of comm_content_errinj_manager_ent.vhd was successful.
-# Compile of error_injection_ent.vhd was successful.
-# Compile of fee_hkdata_manager_ent.vhd was successful.
-# Compile of fee_imgdata_manager_ent.vhd was successful.
-# Compile of fee_hkdata_controller_top.vhd was successful.
-# Compile of fee_imgdata_controller_top.vhd was successful.
-# Compile of fee_data_manager_ent.vhd was successful.
-# Compile of comm_data_transmitter_pkg.vhd was successful.
-# Compile of comm_data_transmitter_manager_ent.vhd was successful.
-# Compile of comm_data_transmitter_housekeep_ent.vhd was successful.
-# Compile of comm_data_transmitter_fullimage_ent.vhd was successful.
-# Compile of comm_data_transmitter_windowing_ent.vhd was successful.
-# Compile of comm_data_transmitter_top.vhd was successful.
-# Compile of fee_data_controller_top.vhd was successful.
-# Compile of comm_irq_manager_pkg.vhd was successful.
-# Compile of comm_feeb_irq_manager_ent.vhd was successful.
-# Compile of comm_rmap_irq_manager_ent.vhd was successful.
-# Compile of comm_statistics_manager_ent.vhd was successful.
-# Compile of comm_sync_manager_ent.vhd was successful.
-# Compile of comm_timecode_manager_ent.vhd was successful.
-# Compile of comm_restart_manager_ent.vhd was successful.
-# Compile of comm_rmap_rw_manager_ent.vhd was successful.
-# Compile of comm_v2_top.vhd was successful.
-# Compile of config_avalon_stimuli.vhd was successful.
-# Compile of spw_controller_stimuli.vhd was successful.
-# Compile of cbuf_tb_avs_pkg.vhd was successful.
-# Compile of cbuf_tb_avs_write_ent.vhd was successful.
-# Compile of cbuf_tb_avs_read_ent.vhd was successful.
-# Compile of comm_tb_avs_right_read_stimuli.vhd was successful.
-# Compile of comm_tb_avs_left_read_stimuli.vhd was successful.
-# Compile of testbench_top.vhd was successful.
-# 71 compiles, 0 failed with no errors.
-# End time: 01:15:56 on Oct 28,2021, Elapsed time: 0:24:06
-# Errors: 0, Warnings: 15
+# End time: 00:34:59 on Feb 02,2023, Elapsed time: 0:23:22
+# Errors: 0, Warnings: 9