Added changes to allow QEMU to expose UART (#3)

Author: philgweber

Dockerfile

@@ -29,7 +29,7 @@ RUN apt-get update && \
         libtpms-dev && \
     rm -rf /var/lib/apt/lists/*
 
-COPY qemu-tpm-patch.patch /tmp/qemu-tpm-patch.patch
+COPY qemu-sbsa-patch.patch /tmp/qemu-sbsa-patch.patch
 
 ARG QEMU_URL="https://gitlab.com/qemu-project/qemu.git"
 ARG QEMU_BRANCH="v10.0.0"
@@ -38,7 +38,7 @@ ARG TARGETARCH
 RUN --mount=type=cache,id=ccache-${TARGETARCH},target=/root/.cache/ccache \
     git clone "${QEMU_URL}" --branch "${QEMU_BRANCH}" --depth 1 qemu && \
     cd qemu && \
-    git apply /tmp/qemu-tpm-patch.patch && \
+    git apply /tmp/qemu-sbsa-patch.patch && \
     PATH="/usr/lib/ccache:${PATH}" ./configure --target-list=aarch64-softmmu --enable-plugins --enable-tpm && \
     PATH="/usr/lib/ccache:${PATH}" ninja -C build qemu-system-aarch64 && \
     ninja -C build install && \

qemu-tpm-patch.patch qemu-sbsa-patch.patchqemu-tpm-patch.patch renamed to qemu-sbsa-patch.patch

@@ -1,5 +1,5 @@
 diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
-index aa09d7a..c579197 100644
+index aa09d7a091..0bb74197d2 100644
 --- a/hw/arm/sbsa-ref.c
 +++ b/hw/arm/sbsa-ref.c
 @@ -28,6 +28,8 @@
@@ -11,26 +11,36 @@ index aa09d7a..c579197 100644
  #include "exec/hwaddr.h"
  #include "kvm_arm.h"
  #include "hw/arm/boot.h"
-@@ -94,6 +96,7 @@ enum {
+@@ -94,6 +96,8 @@ enum {
      SBSA_SECURE_MEM,
      SBSA_AHCI,
      SBSA_XHCI,
 +    SBSA_TPM,
++    SBSA_SECURE_UART_TEST,
  };
-
+ 
  struct SBSAMachineState {
-@@ -132,6 +135,7 @@ static const MemMapEntry sbsa_ref_memmap[] = {
+@@ -132,6 +136,8 @@ static const MemMapEntry sbsa_ref_memmap[] = {
      /* Space here reserved for more SMMUs */
      [SBSA_AHCI] =               { 0x60100000, 0x00010000 },
      [SBSA_XHCI] =               { 0x60110000, 0x00010000 },
 +    [SBSA_TPM] =                { 0x60120000, 0x00010000 },
++    [SBSA_SECURE_UART_TEST] =   { 0x60130000, 0x00001000 },
      /* Space here reserved for other devices */
      [SBSA_PCIE_PIO] =           { 0x7fff0000, 0x00010000 },
      /* 32-bit address PCIE MMIO space */
-@@ -631,6 +635,24 @@ static void create_smmu(const SBSAMachineState *sms, PCIBus *bus)
+@@ -154,6 +160,7 @@ static const int sbsa_ref_irqmap[] = {
+     [SBSA_XHCI] = 11,
+     [SBSA_SMMU] = 12, /* ... to 15 */
+     [SBSA_GWDT_WS0] = 16,
++    [SBSA_SECURE_UART_TEST] = 17,
+ };
+ 
+ static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx)
+@@ -631,6 +638,24 @@ static void create_smmu(const SBSAMachineState *sms, PCIBus *bus)
      }
  }
-
+ 
 +static void create_tpm(SBSAMachineState *sbsa, PCIBus *bus)
 +{
 +    Error *errp = NULL;
@@ -52,12 +62,21 @@ index aa09d7a..c579197 100644
  static void create_pcie(SBSAMachineState *sms)
  {
      hwaddr base_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].base;
-@@ -688,6 +710,8 @@ static void create_pcie(SBSAMachineState *sms)
+@@ -688,6 +713,8 @@ static void create_pcie(SBSAMachineState *sms)
      pci_create_simple(pci->bus, -1, "bochs-display");
-
+ 
      create_smmu(sms, pci->bus);
 +
 +    create_tpm(sms, pci->bus);
  }
-
+ 
  static void *sbsa_ref_dtb(const struct arm_boot_info *binfo, int *fdt_size)
+@@ -810,6 +837,8 @@ static void sbsa_ref_init(MachineState *machine)
+     create_uart(sms, SBSA_SECURE_UART, secure_sysmem, serial_hd(1));
+     /* Second secure UART for RAS and MM from EL0 */
+     create_uart(sms, SBSA_SECURE_UART_MM, secure_sysmem, serial_hd(2));
++    /* Test secure UART */
++    create_uart(sms, SBSA_SECURE_UART_TEST, secure_sysmem, serial_hd(3));
+ 
+     create_rtc(sms);
+