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Commit c717a39

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author
qianbaiquan
committed
arch-riscv: Skip PTW level gating for prefetches
1 parent 4e4e6da commit c717a39

3 files changed

Lines changed: 23 additions & 14 deletions

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‎src/arch/riscv/pagetable_walker.cc‎

Lines changed: 9 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -238,16 +238,19 @@ Walker::retryPtwLevelBlockedStates()
238238

239239
bool
240240
Walker::usePtwLevelLimitForStart(bool from_forward_pre_req,
241-
bool from_back_pre_req) const
241+
bool from_back_pre_req,
242+
bool is_prefetch) const
242243
{
243-
return enablePtwLevelLimit && !from_forward_pre_req && !from_back_pre_req;
244+
return enablePtwLevelLimit && !from_forward_pre_req &&
245+
!from_back_pre_req && !is_prefetch;
244246
}
245247

246248
bool
247249
Walker::canStartPtwLevel(int level, bool from_forward_pre_req,
248-
bool from_back_pre_req)
250+
bool from_back_pre_req, bool is_prefetch)
249251
{
250-
if (!usePtwLevelLimitForStart(from_forward_pre_req, from_back_pre_req))
252+
if (!usePtwLevelLimitForStart(from_forward_pre_req, from_back_pre_req,
253+
is_prefetch))
251254
return true;
252255

253256
panic_if(level < 0 || level >= static_cast<int>(ptwLevelLimit.size()),
@@ -2045,7 +2048,8 @@ Walker::WalkerState::usePtwLevelLimit() const
20452048
{
20462049
return timing && (translateMode == defaultmode ||
20472050
translateMode == twoStageMode) &&
2048-
!fromPre && !fromBackPre;
2051+
!fromPre && !fromBackPre &&
2052+
mainReq && !mainReq->isPrefetch();
20492053
}
20502054

20512055
int

‎src/arch/riscv/pagetable_walker.hh‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -454,9 +454,11 @@ namespace RiscvISA
454454
void recvReqRetry();
455455
bool sendTiming(WalkerState * sendingState, PacketPtr pkt);
456456
bool usePtwLevelLimitForStart(bool from_forward_pre_req,
457-
bool from_back_pre_req) const;
457+
bool from_back_pre_req,
458+
bool is_prefetch) const;
458459
bool canStartPtwLevel(int level, bool from_forward_pre_req,
459-
bool from_back_pre_req);
460+
bool from_back_pre_req,
461+
bool is_prefetch);
460462
void recordPtwMissQueueResourceBlocked();
461463
void recordPtwMissQueueFifoBlocked();
462464
bool enqueuePtwMiss(ThreadContext *tc, BaseMMU::Translation *translation,

‎src/arch/riscv/tlb.cc‎

Lines changed: 10 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1832,6 +1832,7 @@ TLB::L2TLBSendRequest(Fault fault, TlbEntry *e_l2tlb, const RequestPtr &req,
18321832
Addr paddr;
18331833
TlbEntry *e_l2tlbVsstage = nullptr;
18341834
TlbEntry *e_l2tlbGstage = nullptr;
1835+
const bool is_prefetch = req->isPrefetch();
18351836

18361837
if (hitInSp) { //hit sp,obtain PA direatly
18371838
if (fault == NoFault) {
@@ -1841,15 +1842,15 @@ TLB::L2TLBSendRequest(Fault fault, TlbEntry *e_l2tlb, const RequestPtr &req,
18411842
return std::make_pair(true, fault);
18421843
}
18431844
} else { //hit l2l1/l2/l3,trigger PTW
1844-
if (translation != nullptr && !from_miss_queue &&
1845+
if (translation != nullptr && !from_miss_queue && !is_prefetch &&
18451846
walker->hasPendingPtwMiss()) {
18461847
walker->recordPtwMissQueueFifoBlocked();
18471848
walker->enqueuePtwMiss(tc, translation, req, mode, false);
18481849
delayed = true;
18491850
return std::make_pair(true, fault);
18501851
}
18511852
if (translation != nullptr &&
1852-
!walker->canStartPtwLevel(level, false, false)) {
1853+
!walker->canStartPtwLevel(level, false, false, is_prefetch)) {
18531854
walker->recordPtwMissQueueResourceBlocked();
18541855
walker->enqueuePtwMiss(tc, translation, req, mode, from_miss_queue);
18551856
delayed = true;
@@ -2278,7 +2279,7 @@ TLB::doTwoStageTranslate(const RequestPtr &req, ThreadContext *tc,
22782279
PrivilegeMode pmode = getMemPriv(tc, mode);
22792280
bool continuePtw = false;
22802281
int l1tlbtype = H_L1miss;
2281-
2282+
const bool is_prefetch = req->isPrefetch();
22822283

22832284
TLB *l2tlb;
22842285
if (isStage2) {
@@ -2348,7 +2349,7 @@ TLB::doTwoStageTranslate(const RequestPtr &req, ThreadContext *tc,
23482349
return std::make_shared<AddressFault>(req->getVaddr(), 0, code);
23492350
}
23502351
if (translation != nullptr && !from_miss_queue &&
2351-
walker->hasPendingPtwMiss()) {
2352+
!is_prefetch && walker->hasPendingPtwMiss()) {
23522353
walker->recordPtwMissQueueFifoBlocked();
23532354
walker->enqueuePtwMiss(tc, translation, req, mode, false);
23542355
delayed = true;
@@ -2357,7 +2358,8 @@ TLB::doTwoStageTranslate(const RequestPtr &req, ThreadContext *tc,
23572358
int walk_level = req->get_h_gstage() ?
23582359
req->get_two_stage_level() : req->get_level();
23592360
if (translation != nullptr &&
2360-
!walker->canStartPtwLevel(walk_level, false, false)) {
2361+
!walker->canStartPtwLevel(walk_level, false, false,
2362+
is_prefetch)) {
23612363
walker->recordPtwMissQueueResourceBlocked();
23622364
walker->enqueuePtwMiss(tc, translation, req, mode,
23632365
from_miss_queue);
@@ -2608,15 +2610,16 @@ TLB::doTranslate(const RequestPtr &req, ThreadContext *tc,
26082610
if (traceFlag)
26092611
DPRINTF(TLBtrace, "tlb miss vaddr %#x pc %#x\n", vaddr_trace, req->getPC());
26102612
int walk_level = satp.mode == AddrXlateMode::SV48 ? 3 : 2;
2611-
if (translation != nullptr && !from_miss_queue &&
2613+
if (translation != nullptr && !from_miss_queue && !is_prefetch &&
26122614
walker->hasPendingPtwMiss()) {
26132615
walker->recordPtwMissQueueFifoBlocked();
26142616
walker->enqueuePtwMiss(tc, translation, req, mode, false);
26152617
delayed = true;
26162618
return fault;
26172619
}
26182620
if (translation != nullptr &&
2619-
!walker->canStartPtwLevel(walk_level, false, false)) {
2621+
!walker->canStartPtwLevel(walk_level, false, false,
2622+
is_prefetch)) {
26202623
walker->recordPtwMissQueueResourceBlocked();
26212624
walker->enqueuePtwMiss(tc, translation, req, mode, from_miss_queue);
26222625
delayed = true;

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