Ethernet Reset line Deployed (nxp-imx#23)

* Initial sound card integration

* Added reserved memory space for Cortex-M4

* Added corrections to SAI clock pads and removed unnecessary IO settings

* Override the ALSA slot width. reset it to 32-bit

* Fixed wrong bus clock setting

* Corrected the clock sync setting of SAI 1,3 so that the RX follows the bit clock of the TX

* Reactivated HW Crypto accelerator

* Reactivated CAAM

* Ethernet reset line deployed

Author: MUA91

arch/arm64/boot/dts/freescale/mt-connect.dts

@@ -183,9 +183,8 @@
 
 
 &fec1 {
-	pinctrl-names = "default", "sleep";
+	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_fec1>;
-	pinctrl-1 = <&pinctrl_fec1_sleep>;
 	phy-mode = "rgmii-id";
 	phy-handle = <&ethphy>;
 	status = "okay";
@@ -202,8 +201,9 @@
 			interrupt-parent = <&gpio5>;
 			interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
 			reg = <1>;
-			reset-assert-us = <1000>;
-			reset-deassert-us = <1000>;
+			reset-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>;
+			reset-assert-us = <1000>; /*1 ms reset pulse*/
+			reset-deassert-us = <30000>; /*30 ms bootup*/
 			status = "okay";
 		};
 	};
@@ -543,25 +543,6 @@
 		>;
 	};
 
-	pinctrl_fec1_sleep: fec1-sleepgrp {
-		fsl,pins = <
-			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC				0x3
-			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO			0x3
-			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
-			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
-			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
-			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
-			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
-			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
-			MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21			0x1f
-			MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20			0x1f
-			MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19			0x1f
-			MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18			0x1f
-			MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23			0x1f
-			MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22			0x1f
-		>;
-	};
-
 	pinctrl_ethphy: dhcom-ethphy-grp {
 		fsl,pins = <
 			MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3				0x1c4